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Organizing Committee2 Program Committee.3 Welcome Remarks.4 Sponsors...5 Industrial Sponsors7 Keynote Speech 1.8 Keynote Speech 2....10 Tutorial..14 Invited Talk 1.......19 Invited Talk 2...20 Invited Talk 3..22 Technical Program..23 Social Program.....26 Hotel Information..27 Meal Information...31 Workshop Desk Hours32

Contents

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GENERAL CO-CHAIRS

Cheng-Wen Wu National Tsing Hua Univ., Taiwan

cww@ee.nthu.edu.tw

Rochit Rajsuman San Jose State-U, USA r.rajsuman@sjsu.edu

PROGRAM CHAIR

Chih-Tsun Huang National Tsing Hua Univ., Taiwan

cthuang@cs.nthu.edu.tw

FINANCE CHAIR

Meng-Fan Chang National Tsing Hua Univ., Taiwan

mfchang@ee.nthu.edu.tw

PUBLICATIONS CHAIR

Jin-Fu Li National Central Univ., Taiwan

jfli@ee.ncu.edu.tw

REGISTRATION CHAIR

Shyue-Kung Lu Fu-Jen Catholic Univ., Taiwan

sklu@ee.fju.edu.tw

LOCAL ARRANGEMENTS CHAIR

Jen-Chieh Yeh SOC Technology Center, ITRI, Taiwan

jcyeh@itri.org.tw

Organizing Committee

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Robert Aitken, ARM, USA Roger Barth, Intel, USA Johnny J.-E. Ding, Ardentec Corp., Taiwan Christophe Frey, ST Microelectronics, France Xiaogang Du, Mentor Graphics, USA Yamauchi Hiroyuki, Fukuoka Institute of Tech., Japan Charles Hsu, e-Memory Inc., Taiwan Shi-Yu Huang, National Tsing Hua U., Taiwan Andre Ivanov, University of British Columbia, Canada Jerry Shyh-Jye Jou, National Chiao Tung U., Taiwan Ding-Ming Kwai, ITRI, Taiwan Ya-Chih King, National Tsing Hua U., Taiwan Chung Lam, IBM, USA Kuen-Jong Lee, National Cheng Kung U., Taiwan Hongchin Lin, National Chung Hsing U., Taiwan Fabrizio Lombardi, Northeastern U., USA Erik Jan Marinissen, IMEC, Belgium Martin Margala, U. of Massachusetts Lowell, USA Cecilia Metra, U. of Bologna, Italy Saibal Mukhopadhyay, Georgia Tech., USA Sharon Murray, Medtronic Micro, USA Joe Ting, Etron Tech. Inc., Taiwan Joerg Vollrath, Qimonda, Germany Arthur Wang, Winbond, America, USA Chua-Chin Wang, National Sun Yat-Sen U., Taiwan Vyacheslav Yarmolik, BSUIR, Belarus Yervant Zorian, Virage Logic, USA

Program Committee

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Welce to the Memory Technology, Design and Testing Workshop

(MTDT09)! Over the past couple of years, the semiconductor memory,

especially DRAM, industry has been undergoing an agonizing downturn, with a scale never seen before. This is partly caused by the financial tsunami triggered by the subprime mortgage delinquencies and foreclosures in the United States. Over-supply leading to cut-throat competition is another culprit. Last but not least, technology is no longer a scarce resource, so the average selling price (ASP) of semiconductor chips will continue to drop, and smaller companies in all segments of the value chain are likely to suffer more frequently in the future. Restructuring of the industry seems inevitable, and is under way. For researchers and engineers staying in this area, there is no other choice but to continue improving our competitivenesstechnical depth and differentiation. This is achieved by continued investment in R&D, and exchange results and ideas in a technical forum such as the MTDT.

We managed to form a strong and interesting program this year,

albeit the number of submissions is a little bit lower than before, due to the situation mentioned above. The technical program includes 16 papers covering a broad spectrum of the enabling technologies of memory products, including emerging memory devices, advanced memory devices and circuit design, 3D memory technology, memory modeling and testing, etc. In addition, there will be an embedded talk on Overview of IEEE P1450.6.2 Standard, which is for memory modeling in Core Test Language (CTL). Another strong point of this years program is that we have more distinguished invited speakers than ever before. The first Keynote Speech will be on Variation Tolerant SRAM Circuit Design Trend in a Deeper Nanometer-Scale Technology by Prof. Hiroyuki Yamauchi of Fukuoka Institute of Technology. Dr. Michel Renovell from LIRMM will talk about Fault-Model vs. Defect-Model Oriented Testing in the second Keynote Speech. Three Invited Talks will be given by Prof. Ya-Chin King of National Tsing Hua University, Mr. Sreedhar Natarajan of TSMC, and Dr. Sheng-Fu Horng of ITRI, respectively. They will cover timely and interesting topics such as new non-volatile memories, emerging technologies, and 3D integration.

We sincerely hope that you will find this event pleasant and

Welcome Remarks

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relaxed, while informative and inspiring at the same time.

Welcome to Hsinchu and enjoy!

Cheng Wen Wu, National Tsing Hua U. Rochit Rajsuman, San Jose State U.

General Co-Chairs

Chih-Tsun Huang National Tsing Hua U.

Program Chair

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Sponsored by:

National Tsing Hua University http://www.nthu.edu.tw

IEEE Taipei Section http://www.ieee.org.tw/

Co-Sponsored by:

Ministry of Education, R.O.C. http://www.edu.tw

National Science Council http://www.web.nsc.gov.tw

Technically Co-Sponsored by:

IEEE (Institute of Electrical and Electronics Engineers) http://www.ieee.org/

IEEE Computer Society

http://www.computer.org/ Test Technology Technical Council http://computer.org/tttc

Sponsors

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Industrial Technology Research Institute http://www.itri.tw/eng/

Industrial Sponsor

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08:45 09:45, September 1

Title: Variation Tolerant SRAM Circuit Design Trend in a Deeper Nanometer-Scale Technology Speaker: Prof. Hiroyuki Yamauchi Affiliation: Fukuoka Institute of Technology, Fukuoka, Japan Chair: Prof. Chih-Tsun Huang, National Tsing Hua Univ., Taiwan Abstract:

SRAM designers have recognized that threshold-voltage (Vth) variation is the most serious issue to enable further area and operating-voltage (Vdd) scaling. Various circuit design techniques to address this issue have attracted much attention at leading edge conferences since 65nm process node, but their extendibility for 22nm and beyond have not been reviewed and compared. The transition now between 32nm and 22nm technology nodes provides the right opportunity to give an expert evaluation of which techniques will become the mainstream for various applications.

This talk discusses and compares area-scaling-capabilities of

many kinds of SRAM margin-assist solutions for VT variability issues, which are based on various efforts by not only the cell topology changes from 6T to 8T and 10T but also incorporating of multiple voltage supply for cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are reviewed and analyzed in light of an impact on the required area overhead for each design solution given by ever increasing VT-random variation (VT), resulting in a slowdown in the SRAM scaling pace. In order to predict the area scaling trends among various SRAM solutions, two different VT-increasing scenarios of being pessimistic and optimistic are assumed where VT becomes >130mV or suppressed to

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otherwise 10T and 8T with read modify write (RMW) will be needed after VT becomes >85mV and 75mV, respectively.

This talk also gives some examples for a required paradigm shift

in SRAM circuit designs to tackle ever increasing serious issues for further area and Vdd scaling.

Biography:

Hiroyuki Yamauchi is a Professor at the Fukuoka Institute of Technology (FIT) in Fukuoka, Japan. He is now a Director of Computer Science Laboratory in FIT. Previously, he worked for Panasonic in Japan for 20 years, having responsibility as a general manager for developing embedded SRAM, DRAM, and nonvolatile memories. He has invented and developed various SRAM and DRAM circuit design techniques, such as charge-recycling data-bus architecture and a control scheme for elevating SRAM source line potential for leakage reduction and variability tolerance. He holds 87 US patents and has authored over 50 refereed papers in the area of memory circuit design. He received the 1996 Remarkable Invention Award from Science and Technology Agency of Japanese government and the highest ISOCC2008 Best Paper Award. He is a member of the Technical Program Committee of IEEE Symposium on VLSI Circuits 2009, Asia Solid-States-Circuits Conference (ASSCC) 2009, and MTDT2009. He served as a member of Technical Program Committee of International Solid-States-Circuits Conference (ISSCC) from 2002 through 2009. He received his PhD in Engineering in 1997 from the University of Kyushu in Fukuoka, Japan.

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09:00 10:00, September 2

Title: Fault-Model vs Defect-Model Oriented Testing Speaker: Dr. Michel Renovell Affiliation: LIRMM, France Chair: Prof. Chih-Tsun Huang, National Tsing Hua

Unvi., Taiwan Abstract:

With today manufacturing technology, it is not possible to eliminate all defects so that every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. In this situation, the test process consists in identifying defective circuits by applying test vectors in such a way that the presence of the defect can be observed on some circuit outputs.

Traditionally, test generation targets on fault models to produce

tests that are expected to identify defects such as unintended shorts and opens. Test generation does not directly target defects for two main reasons. Firstly, many defects are not easy to analyze and no model exists to completely describe their behavior, thus making inconsistent test generation for these defects. Secondly, there can be a very large number of possible defects in a circuit. Since test generation and test application are limited by available resources such as memory and time, generating tests for all defects is unfeasible.

Consequently, a relatively small set of abstract defects, namely

faults, is constructed and these faults are targeted to generate the tests. With this approach, the test quality relies on fortuitous detection of non-targeted defects. As the quality demands increase, the effectiveness of test generation without any defect consideration becomes questionable. High quality test generation requires a better knowledge of defect behavior.

As a matter of fact, the analysis of defect behavior is a quite

difficult task. One of the main difficulties comes from the presence

Keynote Speech 2

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of random value parameters in the defects, preventing any prediction of the defect behavior. The mechanisms of defect appearance are obviously not controlled, resulting in electrical situations with unknown parameters. As a simple example, how to predict the voltage created by a short-circuit when the value of the short resistance is not known a priori. The classical assumptions such as zero-resistance short can no longer be used and a realistic analysis of defect behavior is required. A challenging but realistic model of defect behavior must now incorporate the random parameters. In the following different fault models for resistive bridging are revisited. 1. Classical Fault models

Historically many fault models have been used to detect bridging defects, each new model generation trying to more precisely describe and represent the real defects.

In the early 80s, the most used fault models were the wired-AND, wired-OR and Dominant models. In fact, these first purely logic fault models did not consider any electrical parameter of the real bridging defect! Obviously, it has been observed that detection of real defects was not very efficient when using these models.

2. Realistic Fault Models

Models have been progressively improved by considering the electrical parameters of the defect. For example, one can find in the literature the series of the socalled Voting models. In these models, it is considered that the defect creates an intermediate voltage on the shorted nodes. As a consequence, the objective of the voting model was to easily compute the intermediate voltage in an efficient way during fault simulation for example. Remember that a model must be easy to manipulate and handle by the test tools and consequently must ensure a reasonable CPU time when implemented in the test tools.

These models usually qualified as Realistic fault models have been used in fault simulation and ATPG for years.

3. Realistic Defect Model

The most recent models take the bridge resistance into account. For this new model, the objective is no longer the computation of the intermediate voltages resulting from the bridging defect. Indeed, the resistance of the bridge is a parameter of the defect that can not predicted. Now, the voltage value of the shorted nodes depends on the random resistance of the bridge. Rather the basic concept of this new model is the evaluation of the range of detectable resistance as illustrated below.

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In the presence of a zero bridge resistance, both nets have the same voltage value and the circuit exhibits faulty logic behaviour. However, as the bridge resistance increases, the voltage of the bridged nets gets closer to the defect free value so that for high resistance values, the circuit operates properly. In this way, there is a critical resistance value (RC) above which the circuit does not show faulty logic behaviour. This behaviour is illustrated in the Figure below. Suppose that the bridge is excited in such a way that VA is set to logic 1 in the defect free case, whereas VB is set to logic 0. The plot in the Figure represents the voltage of the bridged nets as a function of the bridge resistance. For a zero bridge resistance, both VA and VB have the same value. However, as Rb increases, VA increases and VB decreases, to the point that Rb is so high that VA is properly interpreted by NAND3 (RC(NAND3)), and for a higher resistance VB is also properly interpreted by NAND4 (RC(NAND4)). Therefore,

When Rb < RC(NAND3), logic errors are propagated through both NAND3 and NAND4.

When RC(NAND3) < Rb < RC(NAND4), logic errors are propagated through NAND4.

When Rb > RC(NAND4), the circuit does not show faulty logic behaviour.

For a given resistive bridging defect, the proposed model allow to easily compute during fault simulation, the different critical resistances (RC(NAND3), RC(NAND4) which in fact define the range of detectable resistance associated to the defect. This information is used during fault simulation and ATPG to guide the test generation process and to evaluate some quality metrics of the test vectors. 4. Conclusion

The presentation will give details on the definition of these new defect models as well as implementation in fault simulation and ATPG tools. Information may also be found in the references given below.

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Biography: In 1986, Michel Renovell joined the Laboratory of Computer

Science, Automation and Microelectronics of Montpellier where he is a researcher funded by the French National Council for Scientific Research (CNRS). From 1995 to 2005, he served as head of the Microelectronics teams at LIRMM. Since 2006, he is Scientific Advisor for the National CNRS headquarter managing more than 300 labs in France. He is also Director of the French National Network on SOC/SiP Design & Test. He is a member of the editorial board of JETTA, the editorial board of IEEE Design & Test and the editorial board of the VLSI Journal. Michel was general chair and program chair of many conferences , he has published over 150 international papers and has received several best paper awards. His research interests include: Fault modeling, Analog testing and FPGA testing.

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09:00 16:30, August 31

Title: DRAM Challenges in Operation, Test and

Diagnostics Speaker: Joerg Vollrath Affiliation: Qimonda, Germany Chair: Prof. Jin-Fu Li, National Central Univ.,

Taiwan Abstract:

This tutorial is aimed at the system engineer, who has to deal with DRAMs in an application. DRAMS come in densities from 512MBit to 4GBit, operating voltage ranges between 1.35V and 2.5V, as components and modules with 4..64 data lines and have a leaky capacitor for storage. The memory interface has data rates from 233MBit/s/pin up to 2GBit/s/pin. Fundamentals of memories are covered. Theory as well as practical, industrial examples will be discussed. Resources like data sheets to learn more about memories will be presented. Understanding of operational states for initialization, write, read and refresh during this class enables the audience to optimize the use of memories in a system. The class enables the audience to develop typical memory patterns. Typical failure modes in the array and periphery are presented to show how to use different debugging and diagnosis tools to find the root cause. This can help in enabling using a DRAM in an application. The benefits of compressed and full bitfailmaps will be presented. High speed operation of modern memory interfaces is discussed. Strategies for systematic measurements of the data eye and limitations of the measurement equipment will be shown.

The tutorial has 4 sections: 1.1 What kind of DRAMS are available (Introduction)? 1.2 Memory cell, memory architectures and data sheets? 2.1 How do I operate the DRAM and test it (Read, write Patterns)? 2.2 How do I write patterns? 3.1 Memory fails and Diagnosis?

Tutorial

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3.2 Retention fails, bit mapping and scrambling? 4.1 Memory Periphery and Interface. What can go wrong at the

interface? 4.2 Summary, Discussion and Outlook 1.1 What kind of DRAMS are available (Introduction)? DRAMs are changing quickly. The density increases from 512MBits to 4GBit. The memory interface has data rates from 233MBit/s/pin up to 2GBit/s/pin. Operating voltage range is between 1.35V and 2.5V. DRAMs are available as components with 4, 8 and 16 bit wide data bus and as modules with 64 data lines. DRAMs need refresh operation, since they are based on charge storage on a leaky capacitor. There are configuration registers in modern memories (mode registers), which need different settings (array parameters and read write parameters) for maximum performance. The main goal of this section is to enable the engineer to select the right memory for a given application. Key electrical parameters are identified to be able to select a memory according to a requirement specification.

DRAM Architectures: Asynchronous and Synchronous DRAM, DDR, DDR2 and DDR3

SDRAM DDR2 datasheet Operation states The Internal test setup Component Packages and Memory Modules

Types

1.2 Memory cell, memory architectures and data sheet? The memory cell a leaky capacitor defines the functionality of a DRAM. Temperature is a key parameter to change the leakage of the capacitor. All cells have different retention behavior and need characterization. Refresh operation and retention time are key parameters of a DRAM. It is important to understand that each memory cell needs to be tested and bad cells need repair. The memory cell is presented in depth to avoid faulty operation of the memory. Memory architecture defines the access modes and power consumption for a DRAM. The data sheet is discussed as a reference to be able to assess new memory types. Most important sections of a data sheet are highlighted. This enables the audience to get correct and maximum use of a data sheet.

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DRAM Manufacturing Technologies (Stack & Trench)

DRAM Block Diagrams DRAM Design Components: Array and

Periphery DRAM Array Layout Components

2.1 How do I operate the DRAM and test it (Read, write Patterns)? A DRAM requires initialization patterns and has a special command sequence for read and write. Special notations are introduced for memory test. Also array timings and data transport timings are reflected in a given memory pattern. March tests are introduced and test times for testing every cell of a huge memory array are calculated. This gives a feel for the amount of test time needed to ensure proper fail coverage and quality. Different notations are used on low level (vector), medium abstraction level (macro commands) and for complete memory patterns.

Activation and Refresh operation Read operation Write operation

2.2 How do I write patterns? Modern memories can use different read and write latencies for different operation frequency. Manual pattern writing is very error prone. This section presents a method to automatically adapt a pattern for different operation frequencies. This is very efficient and fast for development of a system. March patterns are discussed, retention patterns and signal margin patterns. Also stress mechanisms like voltage, temperature and data topology are discussed. All these patterns address special faults in the memory array. Tests can be very selective for a certain fail type. It is important to understand what kind of fail types a typical component or module test can cover.

Algorithmic Tests for Memory Write/Read and March

Retention tests Disturb tests Leakage tests Signal Margin test

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Internal Timing Tests

3.1 Memory fails and Diagnosis? Designing a system needs also test, debug and diagnosis of memory operation. The fails can be analyzed using different patterns. A practical industrial example will be presented. Diagnosis is also important. Various Memory tests and test conditions can help localizing a fail. These memory test classes are covered in detail so they can be implemented in a BIST or in a memory controller or tester.

Single Cell Fail Analysis Example Block Fail and Analysis

Redundancy Fail and Analysis Failure Analysis Techniques: Soft Defect

Localization for DRAM Defect Modeling and Simulation

3.2 Retention fails, bit mapping and scrambling? Retention fails are typically single bit fails at high temperature. The fail mechanism of retention fails is presented. Bit fail mapping is a very powerful tool for diagnosis. It prevents fault memory overflow of fail vector storage and allows easy classification of memory fails. Bit fail maps show the exact location of a fail. For physical failure analysis the exact location can be found out if the right scrambling is used. Sometimes it is surprising, which areas are mostly effected by faults. This can lead to design improvements. Scrambling maps a fail address to a physical x, y fail coordinate on the chip. This can lead to improved reliability or to improvements in the fabrication process.

Chip Maps, Wafer Maps, Lot Maps Compressed bit fail map compared to fail vector

memory Practical Aspects of Bitmapping Scrambling

4.1 Memory Periphery and Interface. What can go wrong at the interface?

Modern interfaces are high speed. According to the data sheet it is required for the data pin to have certain drive strength, slew rate

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and crossing points. The accuracy requirements are now in the order of the limit of the measurement equipment. This section shows strategies how to measure the data eye and enable high speed memory operation. Jitter and source synchronous operation is discussed.

Decoder Failure Analysis DDR2 Functional Tests Memory Tester Performance Measurement of Device Performance Timing Measurement Correlation

4.2 Summary, Discussion and Outlook In the summary the most import points are summarized and room for questions are given. Open topics can be covered. Biography:

Dr. Ing. Joerg E. Vollrath received 1989 his Dipl.-Ing. and 1994 his Dr.-Ing. in electrical engineering, semiconductor technology at the University of Darmstadt, Germany. He has been working for 15 years in the field of memory product engineering at Siemens and Infineon Technologies, now Qimonda in various locations in the USA and Germany. He has worked in joint ventures with IBM, Toshiba, Motorola and Nanya covering DRAMs, SDRAMs, DDR1,2 and 3 types in 16MBit to 4GBit densities from 0.45um to 46nm feature size. His expertise and interest lies in the field of design, test, characterization, diagnosis, yield, manufacturing, automation and reliability. He has published 24 papers and currently holds 32 patents. (Email: Joerg.Vollrath@ieee.org)

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09:45 10:30, September 1

Title: Development of Logic Non-volatile Memory in Nano-scale Technologies Speaker: Prof. Ya-Chin King Affiliation: National Tsing Hua Univ., Taiwan Chair: Prof. Meng-Fan Chang, National Tsing Hua Univ., Taiwan Abstract:

The increasing demands on embedded non-volatile memories in logic circuits spurred many research activities in the development of low-cost, highly scalable and compatible solutions. Besides full compatibility to standard CMOS logic process, low voltage and power operations, small cell size, and fast programming and accessing speed are all desirable features in logic NVMs. As technology scales, conventional solutions suffer from high power, performance degradation and poor scalability. In this talk, new logic NVM cells developed for advance logic circuit are introduced and compared to provide new design directions for the future. Biography:

Ya-Chin King was born in Taiwan, Republic of China. She received the B.S. degree in electrical engineering from National Taiwan University in 1992, and the M.S. degree in electrical engineering from University of California, Berkeley, in 1994. She received her PhD degree in May of 1999, at University of California, Berkeley, on thin oxide technology and novel quasi-nonvolatile memory. She joined the faculty of National Tsing Hua University at Hsinchu, Taiwan in August 1999. She is currently a professor of the electrical engineering department at NTHU. Her research topics include: advance gate dielectric, CMOS image sensor and non-volatile memory design.

Invited Talk 1

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10:00 10:45, September 2

Title: Emerging Technologies: Trends and

Challenges Speaker: Dr. Sreedhar Natarajan Affiliation: TSMC, Taiwan Chair: Prof. Jin-Fu Li, National Central Univ., Taiwan Abstract:

The complexity of todays applications makes design and scaling of technology ever increasingly difficult and very challenging. Thechallenges are not just from scaling and improving the performance but also with the increased integration density of devices on a SoC and enabling complex functions. Newer memory technologies need to address to improve the integration density with a smaller bit cell, as well as increasing performance, reduced leakage, increased endurance (longer life cycle) and lower active currents. Many new memory technologies have been around for a long time but none seems to have taken mainstream compared to SRAMs, DRAMs or Flash. This talk will address some of the challenges in the newer memory technologies that are evolving, and discuss the requirements of the various applications that can adopt these emerging memory technologies. Biography:

Mr. Sreedhar Natarajan is currently a Director at Design and Technology Platform, TSMC. Prior to joining TSMC, he was the Founder & CEO of EMT Inc, a very successful semiconductor Memory IP company, where he was responsible for the dominant growth and revenue during a very short period. Mr. Natarajan has a combined experience of 18 years in the semiconductor memory industry, his previous experiences includes working for Paradigm Technology, Texas Instruments, MoSys previously in the areas of SOI< SRAM, DRAM, FRAM and Memory Compilers. Mr. Natarajan serves on various international conference committees like ISSCC, CICC, ESSCIRC, ISLPED, SOC, VLSI Symposium. Mr. Natarajan is co-authored the book SOI Design: Analog, Memory and Digital Design. He is a very strong advocate

Invited Talk 2

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on new and emerging Memory Technologies to the semiconductor memory industry. Mr. Natarajan is also co-authored the book on SOI Design, Published by Springer Verilog in 2001.

He has been an invited speaker at various IEEE international conferences and academic institutions and is also served as a Guest Editor for IEEE Journal of Solid State Circuits for many years. Mr. Natarajan is the recipient of the IEEE Circuits and Systems Outstanding Service Award'01 and the past chairman for the Dallas Chapter of the IEEE-Solid State Circuits. Mr. Natarajan obtained his Master's degree in computer engineering from University of Louisiana and is a Senior Member of for the Institute of Electrical and Electrical Engineers. Mr Natarajan is a Associate Editor for IEEE Journal of Solid State Circuits and a IEEE Distinguished Lecturer (2007-2008).

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10:45 11:30, September 2

Title: Recent Progress on Nonvolatile Memory Research and 3D

Integration at ITRI EOL Speaker: Prof. Sheng-fu Horng Affiliation: EOL/ITRI, Taiwan National Tsing Hua Univ., Taiwan Chair: Prof. Jin-Fu Li, National Central Univ., Taiwan Abstract:

Next-generation nonvolatile memories and three-dimensional integrated circuits (3DIC) have been the research focus of Electronics and Optoelectronics Research Laboratories at Industrial Technology Research Institute. The planning and some recent progress of nonvolatile memory research, particularly on RRAM and 3DIC at ITRI EOL will be briefly reviewed. Biography:

Sheng-fu Horng was born in Kaohsiung, Taiwan in 1961. He received the B. S. degree in Electrical Engineering from National Taiwan University in 1983, and the M. S. and Ph.D. degrees in Electrical Engineering from Princeton University in 1988 and 1992, respectively. He joined the Department of Electrical Engineering at National Tsing Hua University since 1992. His current research interest include the growth, physics, and applications of low-dimensional semiconductor structures, the terahertz generation and ultrafast optoelectronic devices, the transport and dynamics of carriers in semiconductors, and conjugated polymer semiconductors.

Invited Talk 3

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T1: Emerging Memories 10:50 12:10, Tuesday, September 1 Chair: Dr. Ding-Ming Kwai, SOC Technology Center ITRI, Taiwan 10:50 T1.1:Voltage-Driven Multilevel Programming in Phase

Change Memories A. Cabrini, S. Braga, A. Manetto, G. Torelli (University of Pavia, Italy)

11:10 T1.2:Circuit Design for Bias Compatibility Investigation of Bulk FinFET Based Floating Body RAM A. Anchlia, M. Garcia Bardon, P. Poliakov, B. Rooseleer, B. De Wachter, N. Collaert, K.van der Zanden, M. Miranda Corbalan, W. Dehaene, D. Verkest (IMEC, Belgium)

11:30 T1.3:A New SRAM Cell Design for Both Power and Performance Efficiency Yen-Ting Chiang,Yen-Jen Chang (National Chung Hsing University, Taiwan)

11:50 T1.4:A Wide-VDD Embedded SRAM for Dynamic Voltage Asynchronous Systems Sue-Meng Yang, Meng-Fan Chang, Kung-Ting Chen, Wen-Chin Wu, Yuan-Hua Chu, Ting-Sheng Chao, Ming-Bin Chen and Ping-Cheng Chen (National Tsing Hua University, Taiwan)

Technical Program

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T2: Advanced Memory Device and Design 13:40 15:20, Tuesday, September 1 Chair: Prof. Meng-Fan Chang, National Tsing Hua Univ., Taiwan 13:40 T2.1:Impacts of Contact Resistance and NBTI/PBTI on

SRAM with High- Metal-Gate Devices Hao-I Yang, Ching-Te Chuang, Wei Hwang (National Chiao Tung University, Taiwan)

14:00 T2.2:High- Hf-based Nanocrystal Memory Capacitors With IrOx Metal Gate for NAND Application W. Banerjee, S. Maikap (Chang Gung University, Taiwan)

14:20 T2.3:A Micro-Watt Multi-Port Register File With Wide Operating Voltage Range Shyh-Chyi Yang, Hao-I Yang, Wei Hwang (National Chiao Tung University, Taiwan)

14:40 T2.4:Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency Wei-Ning Hsu, Tsu-Hsin Wu, Tsung-Chu Huang (National Changhua University of Education, Taiwan)

15:00 T2.5:Variability-Tolerance Binary Content Addressable Memory Cells Sheng-Ping Yong, Jin-Fu Li, Yu-Jen Huang (National Central University, Taiwan)

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T3: 3D Memory Technology 13:30 14:30, Wednesday, September 2 Chair: Prof. Shi-Yu Huang, National Tsing Hua Univ., Taiwan 13:30 T3.1:Memory Repair by Die Stacking with Through

Silicon Vias Yung-Fa Chou, Ding-Ming Kwai, Cheng-Wen Wu (ITRI, Taiwan)

13:50 T3.2:3-D Content Addressable Memory Architectures Yung-Jiun Hu, Jin-Fu Li, Yu-Jen Huang (National Central University, Taiwan)

14:10 T3.3:Cost-Aware Lifetime Yield Analysis of Heterogeneous 3D On-Chip Cache Balaji Vaidyanathan, Yu Wang, Yuan Xie (Pennsylvania State University, USA)

T4: Memory Modeling and Testing 14:30 15:50, Wednesday, September 2 Chair: Dr. Ding-Ming Kwai, SOC Technology Center ITRI, Taiwan

Prof. Hung-Ming Chen, National Chiao Tung Univ., Taiwan

14:30 T4.1:Rapid and Accurate Timing Modeling for SRAM Compiler Yen-Yu Chen, Shi-Yu Huang, Yi-Chung Chang (National Tsing Hua University, Taiwan)

14:50 T4.2:Modeling of SRAM Standby Current by Three-Parameter Lognormal Distribution Ding-Ming Kwai (ITRI, Taiwan)

15:10 T4.3:On Distinguishing Process Corners for Yield Enhancement in Memory Compiler Generated SRAM Chia-Chi Hsiao, Hung-Ming Chen (National Chiao Tung University, Taiwan)

15:30 T4.4:Efficient Characterization using improved Searches, Branching and Automated Pattern Generation Joerg Vollrath, Marcin Gnat (Germany)

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Departure Time: 15:30 ( from the lobby of hotel Ambassador Hotel Hsinchu) Mini-Tour Time: 15:30 18:00 Banquet Time: 19:00 21:00 Mini-Tour: 17K Kilometers Coastline Scenic Area (17)

Imagine a family-friendly waterfront playground with breathtaking views, fresh seafood, places to fly kites, and a weekend and holiday market with everything from a vast array of mouthwatering snacks to colorful kites to carnival-type games. Look no farther: Hsinchu Harbor is the place for you. The Harbor was officially opened in 1991. It covers an area of 91 hectares and has great public facilities and convenient road access. In light of the increasing popularity of recreational fishing and marine tourism, the city government has built a pier for recreational fisherman and a sports park here to attract tourists.

Under the efforts of the City Government, the Hsinchu Citys 17

Kilometers Coastline Scenic Area now boasts eight spectacular scenic spots, including Hsinchu Harbor, Sea Park, Horizon and Sea Viewing Area, the Gangnan Canal, Mangrove Park, the Splendid Coastline, the Haishan Harbor Pier, and the NangangBird Watching Area. A soon-to-be-opened coastal bike lane will link these scenic spots. It will be perfect place to take a pleasant ride along the shore. Whats more, with the Hsinchu Air Force Base nearby, visitors may be able to catch sight of Mirage 2000 fighters in the sky. Thats always fun.

The best time to visit this area is in the late afternoon, after

3:00pm. The sun is not quite so hot then, which makes it the most suitable time for a bike ride. There are pavilions along the way for cyclists to take rests and drink water. The cool ocean breeze and the spectacular ocean views will drive all your worries away. Banquet: Ambassador Hotel, Hsinchu ()

Social Program

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Workshop Ambassador Hotel Hsinchu http://hsinchu.ambassadorhotel.com.tw/HC/ambassador_hsinchu.htm Address: 11F, Ambassador Hotel, Hsinchu Tel: +886-3-515-1111 Fax: +886-3-5151112

Transportation From/to TaoYuan International Airport

Hotel Limousine Service and Taxi The hotel limousine service can be reserved at the same time of hotel bookngs.

(1) Ambassador Limousine service The hotel offers a round the clock Limousine Service, for further arrangement please contact the hotel. (NT$1,800 BENZ)

(2) Taxi Airport taxis charge according to the meter in addition to a 50% surcharge (highway tolls not included) and provide transport to anywhere in Taiwan. (A typical taxi fare to Hsinchu is approx. NT$1,500.) Note that most taxi accepts only cash.

Hotel Information

28

Train and High-speed rail (public transportation)

The following services usually take around 2 hours if waiting time is included. Please note that exact changes are needed for buses departing from the airport. Please change bills for coins at the airport counters.

(1) High-speed rail For more information, please visit HRS Website (http://www.thsrc.com.tw/en/?lc=en)

Routes Departure/Arrival Fare

(NT$)

Frequen

cy

Service

Hours

Journey

Time

Ubus

Co.

Taoyuan Airport / HSR

Taoyuan Station 30 30 Mins. 6:50-21:25 20

HSR HSR Taoyuan Station /

HSR HsinChu Station

Standard

Class

130

30 Mins. 6:50-23:00 14

Free

Shuttle

bus

HSR Hsinchu Station /

DONGMEN Circle 0 30 Mins. 7:00-23:00 60

Taxi

DONGMEN Circle

/Ambassador Hotel

Hsinchu

100 - - 10

(2) Train

For more information, please visit: Railway Website (http://www.railway.gov.tw/en/index/index.aspx)

Routes Departure/Arrival Fare

(NT$) Frequency

Service

Hours

Journey

Time

Taoyuan

Bus Co.

Taoyuan Airport/

Tayuan Railway Station45 30 Mins. 6:50-21:25 40

Railways

Tayuan Railway Station

/

HsinChu Railway

Station

Express

114 30 Mins. 6:30-21:30 40

Taxi

Hsinchu Railway

station

/Ambassador Hotel

Hsinchu

100 - - 10

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Tutorial Industrial Technology Research Institute http://www.itri.org.tw/eng/ Address: 2B Conference Room, Bldg. 51, Chung-Hsing Campus, ITRI, Hsinchu, Taiwan Tel: +886-3-582-0100 Fax: +886-3-582-0045

Transportation Directions by car: (from CKS airport to ITRI Chung Hsing

Compound)

(1) Take Freeway 2 from the airport to the Chung Shan Freeway. (2) Go south on the freeway and exit the freeway at the Hsinchu

exit. The distance from airport to this exit is about 70 km. (3) After exiting the freeway, make a left (east) turn onto to

Kuang Fu Road. (4) When you pass Juchung, Kuang Fu road will be renamed

Chung Hsing Road. (5) After driving approximately 10 km from the freeway exit,

you will see the west gate of ITRI on your right side. Directions by bus: (from CKS airport to ITRI Chung Hsing

Compound) (1) Upon exiting the airport terminal, take a KuoKuang bus to

Hsinchu. The distance is about 70 km.

30

(2) Get off at the Starbucks coffee shop on Kuang Fu road. National Tsing Hua University is across the street.

(3) Walk across the street and take a Hsia Gong Guan bus to Er Chong Pu.

(4) Get off at the west gate of ITRI. Depending on the traffic, the bus ride will take 15 to 20 minutes.

Directions by bus: (from Taipei to ITRI Chung Hsing Compound)

(1) Go over the pedestrian footbridge at the northwest corner of

the Taipei Main Train Station. (2) From there you can take a KuoKuang bus to Hsinchu. The

distance is about 75 km. (3) Get off at Starbucks Coffee on Kuang Fu Road. National

Tsing Hua University is across the street. (4) Walk across the street and take a Hsia Gong Guan bus to Er

Chong Pu. (5) Get off at the west gate of ITRI. Depending on the traffic, the

bus ride will take 15 to 20 minutes Directions by train: (from Taipei to ITRI Chung Hsing

Compound) (1) Go to Taipei Main Train Station and take a train to Hsinchu.

The four classes are: Express, ChuKuang, Fuhsing, and Ordinary. The ride will take about 90 minutes.

(2) Please get on the Hsia Gong Guan() bus located next to the Hsinchu Railway station. Buy a ticket to Er Chong Pu.

(3) Get off at the west gate of ITRI. The distance is about 12km

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Aug. 31 (Mon.) Lunch: Time: 12:00 13:30 Place: 2B Conference Room, Bldg. 51, Chung-Hsing Campus, ITRI, Hsinchu, Taiwan Sep. 1 (Tue.) Lunch: Time: 12:10 13:40 Place: Ballroom B, 10F, Ambassador Hotel Hsinchu () Banquet: Time: 19:00 21:00 Place: Ballroom D, 11F, Ambassador Hotel, Hsinchu () Sep. 2(Wed.) Lunch: Time: PM 11:30 13:30 Place: The Promenade the Western restaurant,

12F, Ambassador Hotel Hsinchu ()

Meal Information

32

For Tutorial Only

08:30 16:00, Aug. 31 (Mon.) Venue: 2B Conference Room, Bldg. 51, Chung-Hsing

Campus, ITRI, Hsinchu, Taiwan

For Workshop Only

08:00 15:00, Sep. 1 (Tue.) Venue: Ballroom D, 11F, Ambassador Hotel, Hsinchu

08:30 12:00, Sep. 2 (Wed.)

Venue: Ballroom D, 11F, Ambassador Hotel, Hsinchu

Emergency Hotlines

0972-521087 0975-014153

Workshop Desk Hours

33

Notes

34

Notes

35

Notes

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