os-aware tuning improving instruction cache energy efficiency on system workloads
DESCRIPTION
OS-aware Tuning Improving Instruction Cache Energy Efficiency on System Workloads. Authors : Tao Li, John, L.K. Published in : Performance, Computing, and Communications Conference, 2006. IPCCC 2006. 25th IEEE International Date of Conference : 10-12 April 2006. - PowerPoint PPT PresentationTRANSCRIPT
OS-aware TuningImproving Instruction Cache
Energy Efficiency on System WorkloadsAuthors : Tao Li, John, L.K.
Published in : Performance, Computing, and Communications Conference, 2006. IPCCC 2006. 25th IEEE International
Date of Conference : 10-12 April 2006
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1.Introduction 2.Experimental Methodology 3.User/OS I-Cache Accesses Characterization 4.OS-aware I-Cache Tuning 5.Power and Performance Evaluation 6.Conclusions
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Outline
Dynamic power dissipation Due to charging and discharging highly
capacitive bit lines and sense amps Static power dissipation
電晶體越做越小 -> 自行導通
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1.Introduction
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半導體規格影響耗能
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15 個 app 耗能表
Dynamic 省電 : OS-aware cache way lookup
Static 省電 : OS-aware cache set drowsy mode
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Modified vision of SoftWatt SimOS OS: SGI-IRI 5.3 商業版 硬體 : 8-issue superscalar processor
split L1 Instruct. ,data cache unified L2 cache memory
實測 15 個 application9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 307
2.Experimental Methodology
Vortex : database manipulation code Gcc : compiler code Sendmail : SMTP, 1KB~1.5MB Fileman : cp, rm, chmod, tar –cvf… …… OS activity ranges from 6% in compress,92%
in fileman
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15 個 application
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3.User/OS I-Cache Accesses Characterization
Dual mode
OS instruc.User instruc.
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A conventional 4-way set associative cache requires four tag comparisons and four data array read-outs for a cache access.
Nevertheless, during user execution, performing tag comparisons and data array read-outs for OS cache lines are unnecessary and waste extra dynamic power.
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OS-aware Cache Way Lookup
Cache way mode bit
Processor status register(PSR)
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OS-aware Cache Way Lookup
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OS-aware Cache Way Lookup
Once generated, they remain unchanged unless a cache line replacement.
The processor switches mode.
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OS-aware Cache Way Lookup
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OS-aware Cache Way Lookup
Due to CMOS technology scaling, static power due to leakage current is gaining in importance in I-cache power dissipation.
These make efforts at leakage control essential to maintain control of I-cache power on current and next generations of processors.
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OS-aware Cache Set Drowsy Mode
State-preserving drowsy cache techniques.(L1)
Gated-Vdd technique.(L2)
Cache way mode bit 9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 17 / 30
OS-aware Cache Set Drowsy Mode
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OS-aware Cache Set Drowsy Mode
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OS-aware Cache Set Drowsy Mode
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OS-aware Cache Set Drowsy Mode
Access-biased classification.
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OS-aware Cache Set Drowsy Mode
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OS-aware Cache Set Drowsy Mode
使用 OS-aware cache way lookup 之後， dynamic power 省電的比例 user execution 能省下 29% OS execution 能省下 30%
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5.Power and Performance Evaluation
合計共能省下 30% 的 dynamic power
dynamic power 的省電與否與 cache way access 的減少有關聯
OS-aware cache way lookup 能省下約 30% 的dynamic power 而不影響其效能 power 而不影響其效能
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5.Power and Performance Evaluation
經測試之後 Residency-based drowsy mode scheme 能省下約 5% - 50% 的 leakage power
Access-based drowsy mode scheme 藉由將部分的 cache 設成 drowsy state 以減少更多的 leakage power ，平均約能省下 37% 的 leakage power
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5.Power and Performance Evaluation
OS-aware cache set drowsy mode method 執行時間會略高於正常值（ <1% ）因： 誤將要用到的 cache set 設成 drowsy mode 的花費相對較低 套用 cache set drowsy policies 能讓存取 drowsy
cache 的機率大幅降低
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5.Power and Performance Evaluation
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為了提升 I-cache 的用電效率，我們將從 user/OS I-cache 在系統執行時的存取方式著手，在 dual-mode operation 中觀察其省電能力
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6.Conclusions
OS-aware cache way lookup 藉由減少 parallel tag comparison 以及 data array readout 來降低 dynamic power 消耗
OS-aware tuning 能有效地減少因 CMOS 製程技術進步產生的額外 static power 消耗 OS-aware tuning 能降低 dynamic power 和
static power 的消耗的目的，且只需做少許的硬體元件更動就能達成。9962111 邱鎮浩 9962306 蘇育毅 9962145 吳修億 / 3029
6.Conclusions
Thanks for your listening
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