outline slave board task of board and its asic (board ~ asic) system, and structure of the asic
DESCRIPTION
Muon Track Trigger Processing on Slave and Hi-pT Boards C.Fukunaga/Tokyo Metropolitan University TGC electronics group. Outline Slave Board Task of Board and its ASIC (Board ~ ASIC) System, and Structure of the ASIC Status, Issues, Development plan Hi-pT Board Task of Hi-pT Board/ASIC - PowerPoint PPT PresentationTRANSCRIPT
14/6/2000 End Cap Muon Trigger Review at CERN
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Muon Track Trigger Processing on Slave and Hi-pT Boards
C.Fukunaga/Tokyo Metropolitan University TGC electronics group
• Outline– Slave Board
• Task of Board and its ASIC (Board ~ ASIC)• System, and Structure of the ASIC• Status, Issues, Development plan
– Hi-pT Board• Task of Hi-pT Board/ASIC• System, Structure of the ASIC• Status,Development plan• Hi-pT Board configuration
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Slave Board (SB) /ASIC
•An on detector board, installed several boards in a PS pack
•Inputs are Bunch crossing identified hit patterns from TRIPLET and two DOUBLETS (pivot(outer most one) and middle)
•Low pT muon candidates (> 6 GeV/c) will be identified
•DAQ(Pipeline, derandomizer) system for TGC coordinates are embedded
•Encoded hit information is sent to Hi-pT Board
•Board functionality is more-or-less the same as one of ASIC
Slave Board ASIC TTL/LVDS
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Low-pT track Identification
•Low-pT CM formation
•among triplet three(two) planes r and
•between two doublets (pivot and middle) rr and
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Slave Board (SB) System
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Variety of SB tasks-classified with input detector-
I nput Output
Sort Hit Pattern (encoded)
Wire Doublet WD (6+32+6)*2 r (5 bit)
X (2+32+2)*2 r (3 bit)
Strip Doublet SD (0+32+0)*2 (5 bit)
X (0+32+0)*2 (3 bit)
Wire Triplet WT (0+32+0) X 3 hit (1 bit), r (5 bit)
Strip Triplet ST (0+32+0) X 2 hit (1 bit), (4 bit)
Red: adjacent hit pattern
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SB ASIC Structure (Doublet)
Main Blocks
MIDDLE,PIVOT-IN
1. Phase Adjust
2. Mask
3. Local Coincidence
MATRIX
Coincidence of Middle and Pivot planes
DECLUSTER
continuous hits to single coordinate
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Local Coincidence
• Doublet two planes are staggered• Resolution of a simple coincidence te
chnique will be the same width as CELL width (wire, strip)
• New logic with relaxed AND– Single hit (a track passed edge)– Double hits (a track passed center)– Effective resolution will be finer
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(Coincidence) Matrixincluding local coincidence
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Primary Encode,Declustering & Encodecommon for all sorts of SBs
• After Matrix operation– Primary Encode to select tra
ck with minimum r and/or
– Declustering• A successive cluster for a tr
ack is shrunk to one hit– Encode 3 bit for r, and 4
or 5 bit for r and
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Triplet SB
Wire (2-out-of-3) Strip (1-out-of-2=OR)
Determination of coordinate
(Center plane of triplet has no strip readout)
Determination of r coordinate
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SB ASIC Status
• Very prototype SB ASIC has been designed for training– ASIC for Wire Doublets part only
• no DAQ staff• INPUS(PIVOT,MIDDLE w/o Phase adjust)• MATRIX with full size(88 x 72))• DECLUSTER,32-5 ENCODER
– Simulation has been done • All blocks installed work fine (except decluster logic)• A bug found in decluster logic if several hits are occurred in boundary of Matrix-A,
and –B. (Double counting) ( will be fixed in the next version)• Max delay estimations are given below for this chip (unit,ns)• The maximum latency allowed for the slave board is 1+3 clock (25+75ns)
– Fabrication has been done for training even if we had known bug.
Max Delay
MATRIX 3.60
ENCODER 1.70
Total 5.92 (ns)
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SB ASICIssues, Development Plan
• Issues– Radiation Tolerance
• Dose 25 Gy (10 yrs)• Neutron 3.9x10^12 (8.1x10^11 for >1MeV) (10 yrs)• We choose normal process for fabrication, but pay lots of
attention for functionality– Magnetic Field
• 100 ~ 1000 Gauss, need confirmation for working• Under investigating
– Future plan• Summarized in the last slide
Soft Tolerant Hard
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Hi-pT board/ASIC• Inputs are encoded data of SB for tri
ple and doublet• All SB processed data are once pass
ed in a Hi-pT system• Hi-pT ASICs on a Hi-pT board are (VM
E 9U module) installed in a Hi-pT crate which is put on a outer rim of the pivot doublet
• Basic relation of board and ASIC
• But number of ASICs/board are different for different trigger purposes
LVDS/TTL Hi-pT ASIC
Opt./E Conv.
Hi-pT track Identification
• pT > 20 GeV/c
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Structure and block diagrams(Wire and Strip)
• For both wire and strip, a common ASIC will serve
• Main Blocks– TRIPLET-IN/DOUBLET-IN
1. Phase Adjust2. Decode
– MATRIX– 2-out-of-6 SELECT– H/L SELECT
(If no Hi-pT, then Low-Pt data are filled in output buffer)
– G-OUT(Serializer/G-link converter)
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Matrix for wire&strip
Wire Input
192 x 232 CM
Wire Input
192 x 232 CM
Strip Input
192 x 192 CM
Strip Input
192 x 192 CM
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Logical Diagram of Hi-pT Matrix
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Main modifications since the last TDR
• OR logic for strip signal(for track signals shared with two(three) chambers)
• DAQ part is removed (SB readout only)
• 2-out-of-6 SELECT 6 tracks are found, but only two highest pT tracks are sent to Sector Logic
• Width of Diagonal lines of CM widen (|15| to |20|)• Identical output format for both strip & wire (9 bits)
OR is needed
direction
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Status,Future Plan for Hi-Pt ASIC
• Complete design, and simulation have been done– Confirmed all blocks work fine– Maximum delay of the ASIC estimated as 2 clock (4 assigned)
• Fabrication with 0.6um Rohm Full custom has been done– Hardware inspection is now being done in Tokyo and KEK
• If we find no problem, then we proceed to produce prototype-0 chip in this year (0.35um 3.3V)
• Number of ASICs is not so large, we can make all with University VLSI Design Education Center (VDEC).
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Hi-pT Board configuration and
production
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One of Hi-pT boards
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Summary
• SB ASIC/Board– Concentrate to complete design– Four sorts of functions into one ASIC– + DAQ system ingredient– We are contacting several companies
• Mask pattern made with VDEC and send to a fabrication company (Rohm,inc,Kyoto,Japan) (to save money)
• Complete order to a companybut difficult to find a company since number of fabrications (~5000) too small for them
– Full Design&simulation must be finalized till Oct,’00
• Hi-pT ASIC/Board– Nearly ready to produce the prototype 0 chip– Will be ready till Oct,’00