output impedance design of parallel-connected ups

1126 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 52, NO. 4, AUGUST 2005

Output Impedance Design of Parallel-Connected UPSInverters With Wireless Load-Sharing Control

Josep M. Guerrero, Member, IEEE, Luis García de Vicuña, José Matas, Miguel Castilla, andJaume Miret, Member, IEEE

Abstract—This paper deals with the design of the outputimpedance of uninterruptible power system (UPS) inverters withparallel-connection capability. In order to avoid the need for anycommunication among modules, the power-sharing control loopsare based on the droop method. Since in these systemsthe power-sharing accuracy is highly sensitive to the invertersoutput impedance, novel control loops to achieve both stableoutput impedance and proper power balance are proposed. Inthis sense, a novel wireless controller is designed by using threenested loops: 1) the inner loop is performed by using feedbacklinearization control techniques, providing a good quality outputvoltage waveform; 2) the intermediate loop enforces the outputimpedance of the inverter, achieving good harmonic power sharingwhile maintaining low output voltage total harmonic distortion;and 3) the outer loop calculates the output active and reactivepowers and adjusts the output impedance value and the outputvoltage frequency during the load transients, obtaining excellentpower sharing without deviations in either the frequency or theamplitude of the output voltage. Simulation and experimentalresults are reported from a parallel-connected UPS system sharinglinear and nonlinear loads.

Index Terms—DC–AC power conversion, pulsewidth-modulated(PWM) inverters, uninterruptible power systems (UPSs).

I. INTRODUCTION

RECENT advances in control of uninterruptible powersystems (UPSs) make possible their independent parallel

operation, avoiding communication links between the units.The advantages of such power configuration include highreliability and no restriction on the physical location of the UPSunits [1]. To achieve this special kind of parallel operation, thedroop method is often adopted. The droop method is basedon a well-known concept in large-scale power systems thatconsists of drooping the frequency of the ac-generator when itsoutput power increases [2]. In the case of parallel-connectedUPS inverters, the active and reactive power supplied to theac bus are sensed and averaged, and the resulting signals are

Manuscript received May 19, 2004; revised December 7, 2004. Abstract pub-lished on the Internet April 28, 2005. This work was supported by the SpanishMinistry of Science and Technology under Grant CICYT DPI 2003-06508-C02-01. This paper was presented in part at the IEEE International Symposiumon Industrial Electronics (IEEE-ISIE’04), Ajaccio, Corsica, May 4–7, 2004.

J. M. Guerrero is with the Departamento d’Enginyeria de Sistemes,Automàtica i Informàtica Industrial (ESAII), Escola Universitària d’En-ginyeria Técnica Industrial de Barcelona (EUETIB), Universitat Politécnicade Catalunya (UPC), 08036 Barcelona, Spain (e-mail: [email protected]).

L. García de Vicuña, J. Matas, M. Castilla, and J. Miret are with the Departa-mento d’Enginyeria de Electrònica, Universitat Politécnica de Catalunya, 08036Barcelona, Spain.

Digital Object Identifier 10.1109/TIE.2005.851634

used to adjust the frequency and amplitude of the UPS inverteroutput-voltage reference[3].

Although the possibility of operation with no communicationsignals between the UPS units is a very attractive feature, theconventional droop method has several well-identified limita-tions [4], [5]: 1) the power sharing accuracy is strongly affectedby line impedance unbalances; 2) the harmonic power in caseof supplying nonlinear loads is poorly compensated; and 3) aninherent tradeoff exists between the power sharing accuracy andthe output voltage regulation.

Usually, the inverter output impedance is considered to be in-ductive due to both the high inductive component of the lineimpedance and the large inductor of the output filter. However,this is not always true, since the closed-loop output impedancealso depends on the control strategy. A possible solution to theline impedance problem consists of adding an inductor in serieswith the inverter output, in order to fix the output impedance [6].Nevertheless, this inductor is heavy and bulky, increasing thesize and the cost of the equipment. With the objective of physi-cally avoiding this inductor, several fast control loops emulatingthe desired output impedance have been proposed [7]–[9].

Some control solutions are also reported in the literature toreduce the harmonic distortion of the output voltage when sup-plying nonlinear loads. In [5], a controller was proposed to sharenonlinear loads by adjusting the output voltage bandwidth withthe delivered harmonic power. However, it uses an algorithmwhich is too complicated to calculate the harmonic current con-tent, and the harmonic current sharing is achieved at the expenseof reducing the stability of the system. In another approach [10],every single term of the harmonic current is used to producea proportional droop into the corresponding harmonic voltageterm, which is added to the output-voltage reference.

Frequency and voltage deviations are inherent to the con-ventional droop method operation. These deviations can be aproblem, since they limit the power sharing accuracy and thesystem stability [11]. In [12], a controller shifts up the droopfunction to restore the initial frequency of the inverters by usingan integrator to avoid frequency deviation. However, in practicalsituations when the inverters are not connected to the ac-bus atthe same time, the integrator initial conditions are different, andas a consequence the power sharing is degraded.

The aim of this paper is to overcome the aforementioneddrawbacks and to synthesize novel control strategies withoutcommunication wires, which could be appropriate to high-per-formance paralleled UPS inverters. The control method hereproposed consists of three main loops: an inner loop that regu-lates the output voltage with no steady-state errors, an interme-diate loop to program a virtual output impedance, and an outer

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GUERRERO et al.: OUTPUT IMPEDANCE DESIGN OF PARALLEL-CONNECTED UPS INVERTERS 1127

Fig. 1. Equivalent circuit of an inverter connected to an ac bus.

loop that achieves accurate active and reactive power sharing.This paper, unlike [3]–[8], takes into account the inner controlloops in the design process, due to their important role in thepower sharing accuracy.

The paper is organized as follows. In Section II, a reviewof the power-flow control theory is presented. In Section III,the inner control loops of a single-phase inverter are derivedusing feedback linearization techniques. Section IV presentsan intermediate control loop, which ensures the desired outputimpedance. Section V proposes the design of the outer controlloops to share active and reactive power without output-voltagefrequency or amplitude deviations. Section VI provides simu-lation and experimental results from a two-1-kVA-UPS invertersystem.

II. REVIEW OF THE POWER-FLOW CONTROL THEORY

Fig. 1 shows the equivalent circuit of an inverter connected toan ac bus. The complex power drawn to the bus can be expressedas

(1)

where and are the active and the reactive power, respec-tively, which are given by [2]

(2)

(3)

where and are the amplitudes of the inverter output voltageand the common bus voltage, is the power angle, and andare the magnitude and the phase of the output impedance.

Fig. 2 shows different situations of two inverters con-nected to a common load, with resistive and inductive outputimpedance. As can be seen, the output impedance affects therelation between the amplitude ( and ) or phase difference

and the active or reactive circu-lating-current components between the inverters. Consequently,this impedance should be investigated to determine the powerflow control strategy.

A. Inductive Output Impedance Case:

A conventional assumption is to consider that the outputimpedance of the inverters is mainly inductive ,which is often justified by the large filter-inductor value [3],[14]. In this situation, the following well-known expressions ofthe active and reactive powers can be derived from (2) and (3):

(4)

(5)

where is the output reactance of the inverter.

From these equations, and considering small phase differencebetween and ( and ), it can be seen thatthe active power is strongly dependent on the power angle ,while the reactive power is mainly influenced by the ampli-tude difference . Consequently, most wireless load sharingcontrollers introduce artificial droops into the output voltage ref-erence. This concept is well-known in large-scale power sys-tems, in which dynamic ac generators drop their frequency whenthe output power increases, due to their own inertia [2]. Thus,in order to reproduce this behavior, a and droopscheme is often adopted (see Fig. 3). The frequency and the am-plitude of the inverter output-voltage reference can be expressedas [14]

(6)

(7)

where and are the output voltage frequency and ampli-tude at no load, and and are the droop frequency and am-plitude coefficients.

B. Resistive Output Impedance Case:

When the output impedance of inverters is resistive[8], the active and reactive powers become

(8)

(9)

where is the inverter-output impedance.Hence, when the output impedance is highly resistive, the

droops exchange their roles

(10)

(11)

Consequently, a control scheme based on the anddroops should be used for inductive impedance, while for resis-tive impedance we should use and droops. Forthis reason, it is important to design the output impedance prop-erly in order to improve decoupling between active and reactivepower and to avoid the line impedance impact over the powersharing.

III. DESIGN OF THE OUTPUT-VOLTAGE REGULATION LOOP

The aim of this section is to derive an inner control loop thatprovides good tracking to the UPS inverter in order to regulateits output voltage. Input–output linearization control techniquesare used to derive this control loop. Subsequently, the outputimpedance of the closed-loop inverter is examined.

A. Average Feedback Linearization Control

Fig. 4 shows the power stage of a single-phase inverter,which includes an insulated gate bipolar transistor (IGBT)bridge configuration and an – filter. The equivalent seriesresistance (ESR) of the filter capacitor is not considered inthe model, since its effect appears far above the frequencyrange of concern [15]. The bilinear differential equations that


Fig. 2. Parallel operation of two inverters. Inductive output inductance: (a) equivalent circuit and (b) circulating current vectors. Resistive output impedance:(c) equivalent circuit and (d) circulating current vectors.

Fig. 3. Block diagram of the conventional power-sharing droop method.

Fig. 4. Power stage of the single-phase UPS inverter.

describe the large-signal dynamic behavior of this converterare presented as follows:

(12)

(13)

where is the control variable, which can take the followingvalues: 1, 0, or 1, depending on the state of the pair ofswitches – and – .

According to nonlinear control and feedback linearizationtheory [16]–[18], the output voltage of this system has a second-order relative degree. Thus, from (12) and (13) the open-loopaveraged output-voltage dynamics can be derived

(14)

where means average value over one switching cycle.


Fig. 5. Thevenin equivalent circuit of the closed-loop system.

Fig. 6. Bode diagrams of the closed-loop transfer function G(s), using aconventional PID (light trace) and the proposed controller (dark trace).

In order to linearize, in a large-signal sense, and to achieve agood tracking of the output voltage, we propose the followingcontroller expression:

(15)

where is the output-voltage reference.By equating (14) and (15), the closed-loop output-voltage dy-

namic behavior takes the form

(16)

where is the Laplace operator. From the above expression, theinverter can be modeled by a two-terminal Thevenin equivalentcircuit of the form

(17)

where is the voltage gain and is the outputimpedance, as shown in Fig. 5.

Fig. 6 compares Bode plots of the corresponding tothe proposed controller and to a conventional proportional–in-tegral–derivative (PID) control, by using the design parameterslisted in Table I. Fig. 7 shows the output current, the output

TABLE IPARAMETERS OF THE UPS INVERTER SYSTEM

Fig. 7. Comparison of output voltage waveforms using a conventional PID andthe proposed controller.

Fig. 8. Bode diagram of the output impedance Z (s).

voltage reference, and the output voltage for both cases. Byusing the proposed controller the output voltage follows the ref-erence perfectly, while with a conventional PID there is a largelag in phase and a considerable steady-state amplitude error.

B. Output Impedance Analysis

In order to allow proper parallel operation, the closed-loopoutput impedance of the inverter must be examined. Fig. 8shows the frequency-domain behavior of the output impedancethrough a Bode diagram. As it can be seen, the impedance is


Fig. 9. Output-impedance sensitivity in front of r variations: (a) k = 0

and (b) k = 2500. For r = 0.2, 0.4, and 0.8 (arrow direction indicatesincreasing value of r ).

near inductive in the frequency range of interest that enclosesthe line frequency.

If we avoid the integral term , the output impedancebecomes almost resistive in the area around the output-voltagefrequency. This fact explains why in parallel inverters that usecurrent mode controllers with finite dc gain, as in [19] and [20],

and depend on amplitude and phase difference, respec-tively, as opposed to the conventional relation.

As shown in Fig. 9, apart from its inductive or resistive nature,the output impedance is very sensitive to the parasitic resistance

. The problem is that this parameter is neither easy to measurenor easy to estimate, since it is determined by the ESR of thefilter inductor and other parasitic elements, such as the on/offresistance of the IGBTs, among others.

IV. INSTANTANEOUS DROOP METHOD: VIRTUAL

IMPEDANCE CONCEPT

The output impedance of the closed-loop inverter affectsthe power sharing accuracy and determines the droopcontrol strategy. Furthermore, the proper design of this outputimpedance can reduce the impact of the line-impedanceunbalance.

In order to program a stable output impedance, we can dropthe output voltage reference proportionally to the output current,using the following instantaneous droop scheme:

(18)

where is the virtual output impedance, and the outputvoltage reference at no load, defined as . Fig. 10illustrates this concept in relation to the rest of the control loops.

If is exclusively resistive , the outputimpedance becomes

(19)

Fig. 11 presents Bode plots of the output impedance using theproposed controller with and without the integral term and withand without instantaneous resistive droop. Notice how the con-trol loop (18) forces a resistive output impedance with low sen-sitivity in relation to variations.

A stable output inductance can be produced by emulating aninductive behavior by drooping the output voltage proportion-ally to the time derivative of the output current. In this sense, if

is purely inductive , the output impedanceis given by

(20)

In this expression, if , the effect of overthe low-frequency output impedance is reduced. However, theoutput voltage THD is normally high when the system sup-plies nonlinear loads, since the output-reactance value is fre-quency dependent [9]. This drawback can be overcome by usinga high-pass filter instead of a pure derivative term of the outputcurrent. This is useful to share linear and nonlinear loads [21],[22]. Thus, the instantaneous droop function (18) now takes theform

(21)

where is the cutoff frequency of the high-pass filter.The output impedance in that case becomes (22), shown at

the bottom of the page.Fig. 12 shows a comparison between the output-impedance

Bode plots resulting from the use of a pure inductive func-tion (20), and those resulting from the use of the high-passfilter approach (22), for two different cutoff frequencies (500and 150 Hz). Notice that with a suitable design of the cutofffrequency it is possible to properly share linear and nonlinearloads, since the output impedance combines inductive behavioraround the output-voltage frequency and resistive behavior forhigh-order current harmonics.

Fig. 13 shows a comparison of the output voltage waveformswhen two inverters are connected in parallel and they share anonlinear load, which confirms the good performance of thehigh-pass filter approach when the pole is over 150 Hz.

(22)


Fig. 10. Block diagram of the closed-loop system with the virtual output impedance path.

Fig. 11. Bode diagram of the output impedance Z (s). Four differentsituations: (a) k = 2500 and (b) k = 0, without instantaneous droop;(c) k = 2500 and (d) k = 0 with instantaneous resistive droop.

V. DROOPLESS POWER-SHARING LOOP

As we stated previously, the conventional droop method hasan inherent tradeoff between sharing accuracy and fre-quency/amplitude output-voltage regulation. From (5), we canobserve that reactive power can be well controlled by either theoutput-voltage amplitude, as in the conventional droop method(7), or by the output impedance, as in variable active–passivereactances in large-power systems [23]. Therefore, taking intoaccount that is reduced when increases, we propose theuse of an adaptive output impedance of the form

(23)

where is the coefficient of the power-reactive term, whichadjusts the inductive output impedance, and is the refer-ence output inductance. The proposed output impedance com-pensates reactive-power differences between the modules dueto output voltage mismatches, component tolerances, or lineimpedance unbalances, without deviations of the output-voltagereference amplitude. Notice that although the active power isalso affected by the output impedance, it can be controlled byadjusting the output-voltage frequency.

In order to avoid the steady-state frequency deviation of theconventional droop method (6), the following control scheme isproposed:

(24)

Fig. 12. Output impedance Bode plot: (a) exclusively inductive, (b) HPF with! = 500 Hz, and (c) HPF with ! = 150 Hz.

where is the active power signal without the dc component,which is determined by the following equation:

(25)

and is the time constant of the transient droop action. Notethat the function has no frequency deviation in steadystate [21].

The transient droop function ensures stable frequency regula-tion under steady-state conditions and at the same time achievesactive power balance by adjusting the inverter frequency duringload transients. Fig. 14 shows the evolution of the frequencyof two parallel inverters sharing a nonlinear load at the startuptransient response. As it can be seen, the proposed controllerachieves good frequency restoration, while the conventionaldroop method results in a static frequency deviation. Fig. 15depicts the output voltage and currents of the inverters, showingexcellent load sharing. This fact is corroborated by the activeand reactive power balance among the modules shown inFig. 16.

VI. CONTROLLER IMPLEMENTATION

Fig. 17 shows a block diagram of the power-sharing con-troller, which includes the transient droop and the adaptiveoutput impedance. The average active power , without the dccomponent, can be obtained by multiplying the output voltage

by the output current and filtering the product using abandpass filter

(26)


Fig. 13. Waveforms of the output voltage for two HPF cutoff frequencies: (a) ! = 500 Hz and (b) ! = 150 Hz.

Fig. 14. Frequency of two UPSs (dark line UPS 1, and light line UPS 2)at the startup, for the conventional droop method and the proposed drooplesscontroller.

Fig. 15. Startup output voltage and current when supplying a nonlinear load.

Fig. 16. Startup waveforms of the active (P and P ) and reactive power (Qand Q ) of two inverters.

To adjust the output-voltage frequency, (24) is used; this cor-responds to the reference frequency drooped by the transientactive power signal .

The average reactive power is obtained by delaying theoutput voltage by 90 and using a low-pass filter. The vir-tual output impedance is implemented by using the adaptivehigh-pass filter expressed in (21), regulated by the reactivepower, as (23) shows. Although not shown in Fig. 17, the con-troller also includes a phase-locked loop (PLL) block in orderto synchronize the inverter with the common bus at startup.When this occurs, the UPS inverter is connected to the commonbus, and the droop-based control is initiated.

The power-sharing controller was implemented by means ofa TMS320LF2407A, 16-bit fixed-point 40-MHz digital signalprocessor (DSP) from Texas Instruments. The voltage samplingfrequency was rated at 10 kHz, and the current sampling fre-quency was 20 kHz. The filters were discretized through infi-nite-impulse response (IIR) solutions.

Finally, the inner control loop that regulates the outputvoltage, expressed in (15), can be implemented by using analog


Fig. 17. Block diagram of the proposed power-sharing controller.

Fig. 18. Block diagram scheme of the output-voltage controller.

circuits or by sharing a low-cost microcontroller. Fig. 18shows the block diagram of the proposed control scheme.The output-voltage derivative term is implemented by using asmall current transformer to sense current, which results in areduction of the high-frequency noise

(27)

where is the nominal value of , for which accuracy is notcritical. The control law can be done by comparing the rightterm of (15) with a triangular waveform scaled by the inputvoltage magnitude, in a unipolar or bipolar approach [17]. Thisresults in a pulsewidth-modulated (PWM) generator that decou-ples output voltage dynamics from input voltage variations.

VII. EXPERIMENTAL RESULTS

Two 1-kVA UPS inverters were built and tested, imple-menting the control loops (15), (21), and (23)–(25) witha TMS320LF2407A DSP. Each inverter consisted of asingle-phase IGBT full-bridge with a switching frequencyof 20 kHz and an - output filter, using the parameters listedin Table I. Following with the coefficients shown in Table II,

TABLE IIPARAMETERS OF THE POWER-SHARING CONTROLLER

the control parameters were chosen to ensure stability, propertransient response, and good phase matching.

Experimental tests were performed by supplying a nonlinearload with a crest factor of 3. The measured total harmonic distor-tion (THD) of the load voltage was about 2.5%. Fig. 19 depictsthe load voltage, the load current, and also the output currentof the two modules, showing very good load-sharing capabilitywhen nonlinear loads are supplied.

The dynamic performance of the parallel system was also ex-perimentally evaluated with respect to the case of sudden loadconnection. Fig. 20 shows the transient response of the outputcurrents of both UPS’s. Initially, the UPS modules operate inparallel without a load, but, due to measurement errors, a littlereactive circulating current appears between the modules. Then,in the case of Fig. 20(a), a 1-kW pure resistive load is connected.


Fig. 19. Experimental results supplying a nonlinear load. (a) Load voltage and current (X axis: 5 ms/div; Y axis: 150 V/div, 30 A/div). (b) Output current of thetwo units (Xaxis: 10 ms/div; Y axis: 10 A/div).

Fig. 20. Dynamic response of the output currents of both paralleled UPSs when a sudden load-connection occurs. (a) Purely resistive load of 1 kW (X axis:20 ms/div; Y axis: 1 A/div). (b) Nonlinear load with a crest factor of three (X axis: 20 ms/div; zoom: 10 ms/div; Y axis: 5 A/div).

In the case of Fig. 20(b), the above-mentioned nonlinear load isconnected. In each case, notice the excellent dynamic behaviorof the system.

VIII. CONCLUSION

In previous work about wireless control for parallel operationof UPSs, the inverters were often modeled as a mere voltagesource with an output inductor, and the design of the inner con-trol loops was sometimes disguised, so control droopswere designed with no consideration of the inner control-loopdynamics.

In this paper, a novel wireless controller was proposed bydesigning three nested loops. The inner control loops are de-veloped by using feedback linearization techniques, obtaining a

nonlinear controller that is able to provide good output tracking.The closed-loop output impedance of the inverter was analyzedand designed to choose the suitable power-sharing strategy. Anintermediate instantaneous droop control loop was applied tofix the output impedance and, hence, achieve excellent powerbalance when sharing linear or nonlinear loads. The whole con-troller is completed with a transient frequency droop loop andan additional adaptive output-impedance loop with the aim ofsharing active and reactive power without frequency or ampli-tude steady-state deviations.

Simulation and experimental results have been reported tovalidate the proposed control approach, showing good loadsharing even when supplying nonlinear loads. The excellentfeatures of this wireless controller highlight the industrialapplicability to distributed UPS systems.


ACKNOWLEDGMENT

The authors would like to express their gratitude to J. Barri,R. Ciurans, D. Montesinos, and A. Sabé of Salicrú Electronicsfor their help with the experimental verification.

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Josep M. Guerrero (S’01–M’03) received the B.S.degree in telecommunications engineering, the M.S.degree in electronics engineering, and the Ph.D.degree in power electronics from the UniversitatPolitència de Catalunya, Barcelona, Spain, in 1997,2000, and 2003, respectively

Since 1998, he has been an Assistant Professorin the Department of Automatic Control Systemsand Computer Engineering, Universitat Politècnicade Catalunya, Barcelona, Spain, where he teachesdigital signal processing, control theory, and mi-

croprocessors. Since 2004, he has also been in charge of the SustainableDistributed Generation Systems and Renewable Energy Research Group. Hisresearch interests include DSP-based control, uninterruptible power supplies,PV inverters, and microgrids.

Dr. Guerrero has acted as Session and Topic Chairs for IEEE IECONand IEEE PESC. He is an Associate Editor of the IEEE TRANSACTIONS ON

INDUSTRIAL ELECTRONICS and is listed in Who’s Who in the World and Who’sWho in Science and Engineering.

Luis García de Vicuña received the M.S. and Ph.D.degrees in telecommunications engineering fromthe Universitat Politècnica de Catalunya, Barcelona,Spain, in 1980 and 1990, respectively, and the Dr.Sci.degree from the Université Paul Sabatier, Toulouse,France, in 1992.

From 1980 to 1982, he was an Engineer withControl Applications. He is currently an AssociateProfessor in the Department of Electronic Engi-neering, Universitat Politècnica de Catalunya, wherehe teaches power electronics. His research interests

include power electronics modeling, simulation, and control, active powerfiltering, and high-power-factor ac–dc conversion.

José Matas received the B.S., M.S., and Ph.D.degrees in telecommunications engineering fromthe Universitat Politècnica de Catalunya, Barcelona,Spain, in 1988, 1996, and 2003, respectively.

Since 1997, he has been an Associate Professor inthe Department of Electronic Engineering, Univer-sitat Politècnica de Catalunya. His research interestsinclude power-factor-correction circuits, distributedpower systems, and nonlinear control.

Miguel Castilla received the M.S. and Ph.D. degreesin telecommunications engineering from the Univer-sitat Politècnica de Catalunya, Barcelona, Spain, in1995 and 1998, respectively.

Since 2002, he has been an Associate Professorin the Department of Electronic Engineering, Uni-versitat Politècnica de Catalunya, where he teachesanalog circuits and power electronics. His researchinterests are in the areas of modeling, simulation, andcontrol of dc-to-dc power converters and high-power-factor rectifiers.

Jaume Miret (M’98) received the B.S. degree intelecommunications and the M.S. in electronicsin 1992 and 1999, respectively, from the Univer-sitat Politècnica de Catalunya, Spain, where he iscurrently working toward the Ph.D. degree in theDepartment of Electronic Engineering.

Since 1993, he has been an Assistant Professorat the Universitat Politècnica de Catalunya. Hisresearch interests include dc–ac converters, activepower filters, and digital control.

output impedance design of parallel-connected ups

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