over molding process development for a stacked wafer-level ... · 125 takahashi et al.: over...

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Transactions of The Japan Institute of Electronics Packaging Vol. 5, No. 1, 2012

Fig. 2 Integrated process flow.

1. IntroductionA stacked die WCSP package solution is introduced,

where a top die with micro-bumps is attached directly to

the exposed TSV tips of a thin WCSP (with TSVs). This

package is referred to as Stacked TSV-WCSP, and is illus-

trated by a schematic drawing in Fig. 1(a), and by cross-

sectional, top and side view photographs in Fig. 1(b). The

integrated process flow, shown in Fig. 2, includes front-

[Technical Paper]

Over Molding Process Development for a Stacked Wafer-level Chip

Scale Package with Through Silicon Vias (TSVs)Yoshimi Takahashi, Rajiv Dunne, Masazumi Amagai, Yohei Koto, Shoichi Iriguchi, Tom Bonifield,

Philipp Steinmann, and David C. Stepniak

Texas Instruments Inc. 12500 TI Blvd. DALLAS USA 75266

(Received August 1, 2012; accepted November 26, 2012)

Abstract

To enable System-in-Package (SiP) solutions for analog products with active ICs or in combination with MEMS, passives

or other components, a stacked Wafer-level Chip Scale Package (WCSP) platform has been developed using Through-

Silicon Via (TSV) technology to create the smallest form factor package. This paper describes the integration flow and

the development of the wafer over molding back-end unit process, using a 3 mm × 3 mm test vehicle on a 100 μm thick

200 mm wafer. Wafer-level over molding is a key development item as it provides support to the thin TSV wafers through

the subsequent processes of debonding, ball attach and package singulation. Various molding materials and processes

(compression, screen printing, film) were investigated. Selection of the mold material is a challenge as it must meet

multiple requirements of processability, warpage, debondability, saw-singulation, and chip picking-up. Experimental

results how to reduce warpage and Si damage by saw-singulation, and modeling results for the different mold materials

and the pros/cons of the various molding processes are explained.

Keywords: WCSP, TSV, Wafer level, Over mold, Compression, Print, Film, Warpage

Fig. 1 Stacked TSV-WCSP Package.(b) Photographs of cross-section and overview of the package

(a) Package structure figure of cross-section

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Takahashi et al.: Over Molding Process Development for a Stacked WL-CSP (2/10)

end, middle-end and back-end processes.

In this paper, an overview of the back-end unit processes

in first presented, followed by a detailed discussion on the

development of the back-end wafer-level over molding unit

process. Over mold is required to avoid wafer handling

issues at subsequent process steps and to provide a robust

package structure. However, the mold compound and

under-fill materials in direct contact with the thin bottom

Si wafer tend to provide a large amount of warpage after

removal from the carrier and, there is the concern of the

thin Si knife edge, as shown in Fig. 3 and 4(a). Since these

concerns pose a significant risk at saw singulation, careful

selection of the mold material and technique is required to

achieve a manufacturable process.

2. Unit Processes2.1 Interconnection

For a good interconnection of the micro-bump to the

exposed TSV tip, flux is desired. However, cleaning of the

flux is difficult due to the narrow size of the gap; therefore,

an interconnection approach without flux is recommended

to avoid oxidation-related bonding issues and flux-related

under-fill silicon delamination issues.

2.2 Under-fillConventional under-fill equipment is applicable. A line

dispense was used for manufacturability reasons. Jet dis-

pense is also an option. In case that under-fill is not ful-

filled with conventional dispensing and cure process, vacu-

uming at under-fill process, vacuuming at cure process or

pressure at under-fill cure process are also the options for

avoiding air trapping and voiding. Material properties of

under-fills are shown in Table 1.

2.3 Wafer level moldingSeveral mold techniques are applicable for wafer level

mold. Compression mold, film lamination, and printing

were evaluated. Material properties of molding com-

pounds are shown in Table 2.

2.3.1 Compression moldPowder and liquid materials were evaluated. The typical

temperature of compression mold is lower than 125°C.

This temperature makes the wafer bond adhesive softer.

The adhesive should keep higher viscosity at molding pro-

cess and lower viscosity at debonding process. On the

adhesive currently selected, too much adhesive will

squeeze out on the outside of the wafer, where it sticks to

the mold die set and stops mold operation. Adhesive thick-

ness which bonds the 100 μm thick TSV wafer to the car-

rier wafer should be chosen properly. The mold die needs

a clamp area on Si substrate, so some exposed Si with

knife edge remains on the outside of the wafer. Clamping

by top die provides feasible mold top side flatness good

enough for the following process.

2.3.2 Film lamination moldA non-conductive film material is laminated over the

wafer. Film materials tend to provide lower modulus and

allow for smaller wafer warpage. Film also has the advan-

tage of being able to cover the whole wafer area including

even the knife edge. It is also applicable on conventional

and typical equipment for the processes that follow. It

becomes the simplest process. Concerns about this pro-

cess are related with the selected material properties; (1)

film material sticks to the top chuck of debonder because

the selected material is too soft, and (2) soft material tends

to cause Si substrate side wall cracks on blade singulation.

2.3.3 Printing moldScreen printing is used with print mask. Liquid material

Fig. 3 Knife edge of TSV wafer after debonding.

Fig. 4 Wafer warpage after debond; 100 μm thick silicon / 200 μm thick mold, no 2nd chip.

(b) Softer molding compound tends to show lower warpage

(a) Harder molding compound tends to show bigger warpage

Table 1 Under-fill properties.

UF-A UF-B UF-C

E Low Middle Middle

CTE Middle Middle Middle

Tg High High High

Filler content None Middle Middle

Table 2 Mold compound properties and mold technique.

MC-1 MC-2 MC-3 MC-4 MC-5

E Middle Low High Low Low

CTE Low Middle Low High Middle

Tg Middle Middle High High Low

Filler content High Low High Low Middle

Technique T1 T2 T2 T3 T2

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or powder melted into solvent is available. A print mask

needs some exclusion area on a wafer for setting a print

mask, so, a full wafer edge covering is not achieved with

this technique. Flatness by printing cannot achieve the

proper flatness for debonding. So, mold grinding is

required with this technique.

2.4 DebondingThe debonding technique used for the evaluation in this

paper is sliding at proper higher temperature with thermo-

plastic adhesive. For the sliding, proper force to hold

wafers is required. For this requirement, top wafer surface

should be flat better than 20 μm. Proper force and proper

melting viscosity of the adhesive at proper debonding tem-

perature are required for achieving smooth sliding. Key

parameters are minimal flatness of over molded wafer and

mold material stability keeping toughness during the

debonding temperature.

2.5 Ball attachIf the molded wafer has a knife edge, the concern in the

ball attach process is that the wafer edge is never touched

by any of the equipment.

2.6 Saw singulationMechanical or blade saw process was evaluated,

because blade saw singulation is only applicable process to

cut Si and molding compound in a same process. Laser

singulation is potentially applicable for Si, but not applica-

ble for molding compound. To minimize side wall cracks in

Si substrate, proper under-fill material selection and mold-

ing compound selection and process condition optimiza-

tion are required.

3. Results and Discussion3.1 Wafer over mold development

The first step during the development focused on wafer

warpage. As mentioned earlier and as shown in Fig. 4 and

5, this is important for managing wafer handling as well for

subsequent process steps.

Various mold materials with different material proper-

ties and process techniques were evaluated. Refer to Table

2 for the molding compound material properties. Figure 6

shows warpage experiments included overmold on bare

wafer, overmold on wafer with stacked chips and exposed

dies. Figure 7 shows a cross-section of the overmold-on-die

and exposed die package structures. In these initial experi-

ments, the 100 μm Si thickness is achieved by back grind-

ing (BG) rather than actual debonding from a carrier, and

the exposed die structure is prepared by grinding after

molding. Refer to Fig. 8 to see the direction of the warpage.

Figure 9 shows warpage results for MC-1, MC-2 and

Fig. 5 Wafer flatness in cassette.

(a) Flat wafer over molded to the 2nd chip with the final under-fill and mold compound combi-nation

(b) Bent wafer with soft material. Solder ball side is up in the cas-sette

Fig. 6 Experimental wafer structure provided by grinding technique, 2nd chip size: 10 × 10 mm.

(a) Exposed chips: 100 μm thick chip and mold / 100 μm thick sili-con

(b) 100 μm thick chip in 200 μm total mold thickness / 100 μm thick silicon

(c) 100 μm thick mold / 100 μm thick silicon

Fig. 7 Package structure with overmold on chip and exposed chip.(a) Over mold type (b) Exposed chip type

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MC-3 mold materials with the different package struc-

tures. The material basic properties and technique are

shown in Table 2. This evaluation was done with grinding

and larger 2nd chip size. The exposed chip tends to show

lower warpage and the 2nd chip reduces wafer warpage.

Based on the results, MC-1 was selected. Mold cap thick-

ness or mold compound volume are potentially adjustable

wafer warpage, so, when wafer warpage needs further

improvement on the final structure, mold volume adjust-

ment can be an option for warpage adjustment.

In the next round, two additional candidates MC-4 and

MC-5 were included. Warpage experiments were repeated

using mold on wafer (w/o stacked chip) samples, and the

debonding process was now included.

Figure 10 shows post-debond wafer warpage for MC-1,

MC-4 and MC-5 with 200 μm mold thickness on 100 μm

thick silicon. Both MC-4 and MC-5 have lower modulus,

but showed different wafer warpage.

This difference is assumed to be related to other proper-

ties and different mold techniques.

MC-1, MC-4, and MC-5 were moved to the next evalua-

tion.

Figure 11, Fig. 12 and Fig. 13 show that the co-relation Fig. 8 Warpage direction in - as concave, + as convex. (JEDEC Standard JESD22-B112)

Exposed chips: 100 μm thick chip and mold / 100 μm thick silicon Over mold: 100 μm thick chip in 200 μm thick total mold thickness /

100 μm thick silicon No chips: 100 μm thick mold / 100 μm thick silicon

Fig. 10 Wafer warpage in mm after debonding with 200 μm thick molding com-pound on 100 μm thick silicon wafer. No 2nd chip.

Fig. 9 Wafer warpage (8 inch wafer) differences due to grind technique. 2nd chip size: 10 × 10 mm.

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Fig. 11 Wafer warpage correlation to material property, Tg.

(a) Si wafer thickness; 725 μm old thickness; 250 μm No 2nd chip

(b) Si wafer thickness; 100 μm Mold thickness; 250 μm No 2nd chip, after debonding

Underfill is not applied to the samples. To compare property with molding compound, the CTE position is shown in the figure.

Fig. 12 Wafer warpage correlation to material property, Modulus.

(a) Si wafer thickness; 725 μm Mold thickness; 250 μm No 2nd chip



Fig. 13 Wafer warpage correlation to material property, CTE.

(a) Si wafer thickness; 725 μm Mold thickness; 250 μm No 2nd chip



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between each material properties and molded Si wafer

warpage. Figure 11 for Tg (glassy-transition temperature),

Fig. 12 for modulus, and Fig. 13 for CTE (coefficient of

thermal expansion). Graph (a) of each Fig. shows warpage

of 250 μm thick over molding to 725 μm full thick silicon

wafer, and graph (b) shows warpage of 250 μm thick over

molding to 100 μm thinned silicon wafer after debonding.

The co-relation tendency of (a) and (b) to wafer warpage is

similar, but warpage level with thinned silicon becomes

huge. Among these three material properties, modulus

shows high co-relation for warpage in Fig. 12. Lower mod-

ulus provides lower warpage.

The marks of UF-A, B and C put in Fig. 11, 12 and 13

show level of each material property of under-fill A, B, and

C, to compare molding compound. Under-fill material

properties affect the blade saw singulation quality that dis-

cusses in the next session.

3.2 Saw singulationQuality of saw singulation of Si wafer is important as it

can affect the package reliability performance.

A success criterion is to saw through the Si + mold +

under-fill without die chipping and side-wall delamination.

Side wall cracks and Si chippings mean damage at the

interface between the under-fill and silicon.

Saw experiments were done for MC-1, MC-4 and MC-5

materials, with and without capillary under-fill, and with

200 μm thick molding and 100 μm thick silicon.

A step cut technique is used where the first is done by

slightly cutting into the under-fill area from the Si surface

and the second cut is done through the remaining under-

fill and mold layers using a thinner blade to minimize dam-

age to the boundary of under-fill and silicon. A higher rota-

tion and lower moving speed is recommended to minimize

side wall cracks. As shown in Fig. 14, the side wall cracks

in the MC-4 and UF-A/MC-5 materials could not be elimi-

nated due to its low modulus. MC-1 was the only material

that met specifications with combination of under-fill UF-C.

MC-4 and MC-5 need further improvement and/or saw

optimization. Looking again Fig. 12, MC-4 is the lowest

modulus material and the next is MC-5, and then UF-A.

MC-4 with the lowest modulus material shows the heaviest

Si crack, then UF-A/MC-5 shows slightly better. This

results that under-fill and molding compound should be

higher modulus, located as middle class in modulus

among all material variations including under-fill and mold-

ing compound. Too high modulus of molding compound

causes bigger warpage. Under-fill and molding compound

should be selected to provide lower warpage and higher

modulus.

To clarify the reason why only MC-1 shows slight Si

cracks and why UF-C/MC-1 shows no cracks, further eval-

uation is needed. The difference is volume and size of sil-

ica filler particles. The filler particles for UF-C is less and

smaller size. Generally speaking, silica filler provides

lower resistance on rotation of saw singulation and cleans

saw blade surface. Therefore, MC-1with many filler parti-

cles is expected to show the best for side wall cracks, but,

bigger filler has more destructive power to silicon when

Fig. 14 Saw results of package outlines for different materials combinations and optimized saw-singulation conditions (a) MC-1, (b) UF-C + MC-1, (c) MC-4, (d) UF-A + MC-5.

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it’s destructed.

3.3 ReliabilityScanning Acoustic Microscope (SAM) after Thermal

Shock (T/S, –55/125°C, 5 min / 5 min) 1,000 cycles is

taken from the mold side and clearly shows delamination

on package outline with the softer molding compound

MC-4 in Fig. 15. SAM for UF-C and MC-1 doesn’t show

delamination in Fig. 16.

Figure 17 shows package warpage as a function of T/S

duration. MC-1 had a stable warpage, but MC-4 showed an

increase in warpage. Reason for the behavior with MC-4

needs to be investigated further, is likely related to filler

particle contents and/or chemical formation change.

As a conclusion, the MC-1 is the best material that meets

warpage, saw and reliability requirements in combination

with the capillary under-fill UF-C.

Full units were assembled with top die size of 2 × 2 mm

and bottom die size of 3 × 3 mm. As shown in Fig. 18, the

warpage for mold-over-die is concave, while that for

exposed die is convex. The material properties of the mold

are contributing to balance the warpage, resulting in

almost zero-warpage at room temperature. Over mold and

silicon substrate behave like a sandwiched package struc-

ture with hard-hard material set. Also, the change in warp-

age during reflow is as expected, with the magnitude too

small to cause any Solder Mount Technology (SMT)

issues.

Component level warpage occurs by the expansion and

shrinkage balance in the package layers. Re-Distribution

Layer (RDL) is assumed to contribute to warpage of the

exposed chip and to be convex at room temperature and

concave on 260°C. Almost zero warpage at room tempera-

ture was due to the balance between molding compound

shrinkage and RDL shrinkage, and convex at 260°C was

due to the balance between molding compound expansion

and RDL expansion.

The conclusion is that the over mold structure is better

for preventing warpage and makes a more robust package.

3.4 Stress modelingTo investigate the influence of material properties and

geometry factors on interfacial stress, finite element mod-

eling was done using a L36 Design-Of-Experiments

(DOE). Table 3 shows the range of values for modeling.

The split parameters are TSV tip height, mold height, die

thickness, top chip size, under-fill and molding compound

properties.

The contributed parameters for each evaluation point

are shown in Fig. 19: as p1 micro-bump top outside, p2

micro-bump joint, p3 TSV bottom crossing to Si substrate,

p4 top chip interface to under-fill, and p5 Si substrate inter-

face to under-fill.

The modeling is first correlated with horizontal displace-

ment of the package top surface and vertical displacement

of the package side surface by Differential Interference

Contrast microscope (DIC). The measurement was car-

ried out from 125°C reference temperatures down to 25°C,

so only relative displacement and deformation were

extracted. Thereafter, the L36 DOE simulation was done. Fig. 17 Component level warpage change of MC-1 and MC-4 during T/S.

Fig. 15 T/S 1000 cycles SAM of 100 μm thick silicon with 200 μm thick MC-4.

Fig. 16 T/S 1000 cycles SAM of 100 μm thick silicon with 200 μm thick MC-1 and UF-C.

Fig. 18 Package warpage (in μm) changes during reflow with overmold-on-die and exposed die package structures.

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Based on the results in Fig. 20, the modeling suggests

harder molding compound is better for 2nd chip interface

to under-fill (p4), but no specific difference on TSV silicon

substrate interface to under-fill on package outline (p5).

One reason for the latter is because the package size is

very small and stacked Si on Si substrate doesn’t have big

material expansion mismatch. This result also suggests

that the stress at p5 is not the likely cause for the under-

fill-to-silicon interface delamination observed in T/S (refer

to Fig. 12), but rather that it is due to the saw singulation

Fig. 19 Models and evaluation points.

Fig. 20 Modeling Result.

Table 3 The range of values for modeling.

# Item Range1 Range2 Range3

1 TSV tip height Low Middle High

2 Mold height Low Middle High

3 Die thickness Thin Middle Thick

4 Top chip size Small Middle Large

5 UF material type UF-A UF-B UF-C

6 Mold material type MC-4 MC-5 MC-1

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process.

The modeling advises some ideas to reduce the package

stress, especially for the interconnection area. Softer

under-fill material, harder molding compound and thinner

2nd chip thickness, and taller TSV tip height are recom-

mended. Softer under-fill might not be a viable option due

to the issue of side wall cracking on blade saw-singulation,

but others are applicable for further evaluation.

4. ConclusionsA stacked TSV-WCSP process flow has been developed

with capillary under-fill, over molding and blade saw-singu-

lation.

Special attention to wafer warpage is critical to assure

robust process capability after debonding. Multiple mold

materials were evaluated to assess capability to meet post-

debond warpage, saw singulation and adhesion require-

ments. For under-fill and molding compound, harder mate-

rials are recommended, with higher filler contents and

other specific properties. Over molding is also recom-

mended to protect the Si chip, again selecting harder

materials close to the properties of the Si substrate.

AcknowledgementsWe’d like to express warmest thanks to all members

related to the stacked TSV WCSP development of Texas

Instruments and suppliers. For material, process and

equipment development- Kazuaki Mawatari, Noboru

Nakanishi, Yasuhiro Fujiwara, Kengo Aoya, Yoko

Yamasaki, Masamitsu Matsuura, Yoshihiro Chayama,

Shuji Ogura, Hiroshi Miyazaki, Eiji Miyata, Shinichi Fuchi,

Fumiyo Utsunomiya, Akitoshi Hayase, Ken Sannomiya,

Kenichi Osugi, Mona Eissa, Asad Haider, Sudtida

Lavangkul, Brain Goodlin and Mike Huber.

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131


Yoshimi TakahashiTexas Instruments, Japan. Yoshimi Takahashi is a Member of Group Technical Staff in the Semiconductor Packaging group. She received the B.S degree of Kyushu Institute of Technology in industrial chemicals in 1983, and joined quality assurance group of

TI in 1986 for quality control of wafer fabrication, reliability con-trol, reliability laboratory, and failure analysis. She has moved to package development group in 1998 in charge of molding process and material, and has been leading advanced packages on espe-cially molding technologies for Tape and laminated substrate based Chip-Scale-Packages, Package-On-Package, Wafer-level-Package, and so on.

Rajiv DunneTexas Instruments. Rajiv Dunne is a Mem-ber of Group Technical Staff in the Semicon-ductor Packaging group at Texas Instru-ments. He has extensive experience in advanced package development and reliabil-ity across multiple package families (FCCSP,

FCBGA, WCSP, QFN, Embedded), with recent focus on the development of Through Silicon Via (TSV)-based package solu-tions for Analog and CMOS applications. He received his Ph.D. in Mechanical Engineering from Georgia Institute of Technology, M.S. in Aerospace Engineering from Boston University, and B.E. in Mechanical Engineering from Birla Institute of Technology and Science. He has 10 US patents and 20 publications in interna-tionally recognized journals and conferences.

Masazumi AmagaiTexas Instruments, Japan. Dr. Amagai is a TI Fellow and a manager of modeling and char-acterization in packaging and wafer fab. His expertise is in mechanics, mechanical mod-eling, reliability and structures. Through modeling and simulation, he led mechanical

designs to many of TI’s important silicon and packaging pro-grams such as flip chip packages, wire bond packages, wafer fab trenches and multilevel metal stacks. He has served on several technical conference committees and editorial boards, and is cur-rently an editorial advisory board of Microelectronics Reliability Journal and a board of IEEE CPMT Japan Chapter. He received a Ph.D degree in mechanical science and engineering from Tokyo institute of Technology.

Yohei KotoTexas Instruments, Japan. Yohei Koto gradu-ated from Oita University in mechanical and energy systems engineering on March 2006. And April 2006, he joined packaged develop-ment engineering group of TI.His working areas are mold process/mate-

rial and package sawing. He has experience of PoP and stacked die package.

Shoichi IriguchiTexas Instruments, Japan. Shoichi Iriguchi graduated from Fukuoka University in the faculty of Electronic and Information Tech-nology department in 2005. He joined pack-age development engineering group in charge of wafer back grinding, wafer sawing

process and material development.

Tom BonifieldTexas Instruments. Tom Bonifield is in pro-cess technology development for 32 years at Texas Instruments especially interconnect processes. He is now in Analog, but previ-ously in CMOS Logic and DRAM technolo-gies. Previous development in the areas of

multilevel metal integration, self-aligned silicide processes and contacts, took plasma etch and plasma CVD from infancy to pro-duction in the ‘80s, understanding physical failure analysis, and SRAM and DRAM yield and reliability fail mechanisms. He received PhD. in Physics from Rice University, 1979.

Philipp SteinmannTexas Instruments. Philipp Steinmann received his PhD in Phys-ics in 1998 from the Technical University of Munich, Germany, with a thesis in optoelectronics on the monolithic integration of a semiconductor laser and modulator. He then joined the Analog Technology Development department of Texas Instruments, Dallas, USA, working on complementary bipolar technologies, notably the first complementary SiGe-BIC-MOS technology. He also specialized in advanced passive compo-nents like thin film resistors and high performance analog capaci-tors and TSVs.He has co-authored some 25 patents and some 20 publications.

David C. StepniakTexas Instruments. David Stepniak has 23 years of industry experience, including seven years at TI. His current role is manag-ing development and execution for packag-ing across CMOS and Analog devices. Before joining TI, he was vice president of

engineering and licensing for FlipChip Technologies and bump process engineering manager at Delphi/Delco Electronics. David holds a BSEE from Case Western Reserve and an MBA from But-ler University.

over molding process development for a stacked wafer-level ... · 125 takahashi et al.: over...

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