Signal Integrity Effects in System-on-Chip Designs - A Designer's Perspective

LAURENCE H. COOKE (Independent Consultant), MARTIJN GOOSSENS (Philips Research, Netherlands),PAUL HOXEY (ARM, UK), TAKAHIDE INOUE (Japanese Special Interest Group, VSIA),

DAVID OVERHAUSER (Simplex Solutions, USA), PRASHANT SAXENA (Intel Corp, USA),RAMINDERPAL SINGH (IBM, USA)

Abstract - In this paper, we present a designer's perspective to the signal integrity issues that affect authorsand integrators of blocks used in System-on-Chip designs. In particular, after presenting typical processparameters used for such designs, we focus on signal integrity issues in the context of power grid noise,interconnect crosstalk and substrate coupling. In each case, we describe the problem from the point of viewof System-on-Chip designers (both block authors and block integrators), and briefly discuss standardtechniques that are used to alleviate the problem.

1 INTRODUCTION

System-on-Chip (SoC) design has taken many meanings for IC designers. However, for all of them, the issues ofIntellectual Property (IP) block integration and verification are important problems. As technologies scale, itbecomes very difficult to both design (or "author") IP blocks and then integrate them. In this paper, a background ispresented on the Signal Integrity (SI) problems that designers face and the overall need to tackle them in SoCdesigns.

It is important for the designer to understand the design process of IP block authoring to integration, and theprocesses that System-on-Chip Designers typically design within. The following subsections cover these topics.These are followed by sections on the issues of power grid noise, interconnect crosstalk, and substrate coupling.This paper complements the material presented in this book, and although much of the content in this paper involvesa basic understanding of SI, advanced knowledge is not a prerequisite.

1.1 The Process of System-on-Chip Design

Today’s semiconductor fabrication technology can manufacture chips containing tens of millions of gates, thusallowing full systems to be integrated onto a single semiconductor chip. Using current Electronic DesignAutomation (EDA) techniques, creating such SoCs from scratch would require an army of engineers. As a result,there has been considerable effort on the development of methodologies centered on design reuse in order tominimize the amount of re-engineering of each new chip. Most of these SoC methodologies involve the selectionand integration of appropriate existing internal or third party IP blocks - called Virtual Components (VCs) - basedon an architecture which meets the original product requirement.

This SoC methodology effort involves the specification of standard formats and interface requirements that willensure the successful reuse and integration of such VCs. This allows the separation of VC creation and SoCintegration, and has helped legitimize the emerging third party IP business. As a result, most SoC designmethodologies focus on the creation of IP libraries containing appropriately collared VCs, along with the techniquesto extract and integrate these existing, qualified VCs into an SoC. By the very nature of these methods, there isconsiderable data hidden within the VCs. The key to successful integration is the provision of sufficient informationabout each VC to the integrator to allow successful integration of these components. If the components are all soft(i.e., in an RTL format such as VHDL or Verilog), such data hiding is minimized and the blocks may be physicallyimplemented together. On the other hand, if the VCs are hard (i.e., polygons in a layout in, for example, GDSIIformat), a form of block-based implementation must be used. In this case, the VCs are viewed as black boxes thatmust be physically integrated together. Their functional, clock, test and physical requirements must be sufficientlydelineated to properly integrate such VCs with the rest of the SoC design.

As a VC block author completes the design, there is a need to "package" the design so that it is useful to theintegrator. In this packaging process, the design remains unchanged, but several data views are prepared for thedesign. It is these views that allow the integrator to understand and integrate the design into a larger system withoutrequiring complete visibility into the design. As SI issues become increasingly important with process scaling, the SIview of the design is also becoming an important part of the VC design. This paper therefore focuses on the datatransfer involved in the creation of this view, as well as on design issues in the integration of the VC block. Figure 1shows some of the views required for successful integration of analog (and custom) VCs.

For a detailed background (excluding SI effects) to SoC design and verification, refer to [1] and [2].

1.2 Target Process

SoC designs tend to be a generation or two behind leading edge designs. To help provide some context for theprocess parameters within which such designs are created, Table 1 shows some data in terms of current and nextgeneration process technologies, as well as its usage model for high-performance and cost-performance applications.Most of this data has been extracted from the 1999 version of the International Technology Roadmap forSemiconductors ([3]).

The table clearly shows why there is a growing SI problem as designs move toward 0.13 micron processes. More ofthe wire surface is in the side walls (with aspect ratios growing from 1.8 to 2.1) and the pitch is reducing (from 0.56to 0.39 microns) while the switching frequencies are increasing (from 30 to 40 GHz) and chip size, which is relatedto wire length, grows (from 340 to 430 mm2). All of these factors aggravate the already significant crosstalk issuesin 0.18 micron processes. Similarly, the reduction in voltage (from 1.8 to 1.5 Volts) coupled with the increase inpower (from 90 to 130 Watts) is equivalent to a 73% increase in current (from 50 to 87 amps). This coupled with afaster clock (from 1.2 to 1.6 GHz) further stresses power distribution design. Similarly, the tripling of the logicdensity (from 6.2M to 18M tranistors/cm2) and memory (from 256M to 768M transistors/cm2), and their associatedincreases in charge and current densities, further aggravates substrate coupling issues. Thus, as shown by thesecomparisons, all the parameters which are thought to be improving the semiconductor processing also unfortunatelyworsen the SI issues.

1.3 Snapshot of SI Problems with Scaling Technologies

Table 2 shows a snapshot of the SI effects designers experience (or expect to experience) in various design types andtechnologies. For System-on-Chip design, these problems refer to the various IP blocks that are provided forintegration. As is evident from this table, problems that are considered “esoteric” and applicable only to high-endcustom designs such as microprocessors often move successively to Application Specific Integrated Circuit (ASIC)designs within a couple of process generations. Thus, one can safely predict that signal integrity issues that havebeen plaguing high-end microprocessor designers for several years now will also become a significant headache forASIC and SoC designers in the near future. Figure 2 shows a snapshot of interconnect performance parameters as

Figure 1: Packaging of an Analog VC

Final Layout

AMS Virtual Component Block

Generate physical block description

(GDSII)

Generate static timing model

Generate functionalmodel of Digital

interface

Generate NetlistGenerate Layout Abstract

technologies scale. This data helps show the relative importance of the delay of the interconnect compared to thegate delay, using Aluminum and Copper metal routing with SiO2 and Low-K dielectrics.

Table 1: Snapshot of Process Data Parameters for SoC Designs

Year of First Production Shipment 1999 2002Process Generation 0.18µ 0.13µ

High Performance CostPerformance

High Performance Cost Performance

Dense Lines (DRAM half-pitch) 0.18µ 0.13µIsolation Lines (MPU gate) 0.14µ 0.10µ Gate Thickness 3-4 nm 2-3 nmMetal layer 6-7 7Maximum interconnect length logic(meters/chip) exclude top two layers

1,700 3,300

Minimum metal effective resistance 2.2 µΩ-cm 2.2 µΩ-cmMinimun interlevel metal insulatoreffective dielectric constant

2.5 - 4.1 2.0 - 2.5

Logic transistor/cm2 6.2M 18MMemory bit/cm2 256M 768MUsable Transistor/cm2 (autoLayout) 14M 24MChip Size 340 mm2 800mm2 430mm2 900mm2Maximum Substrate Diameter 300mm 300mmMaximum mask count 24 22 24 24Number of Pads/Chip maximum 1867 934 2553 1277

Number of Package Pins/Balls 1400 700 1915 957Short Wire Pitch 0.36 µm 0.56 µm 0.26 µm 0.39 µmMetal aspect ratio ( H/W) 1.8 2.1Minimum Supply Voltage 1.5 - 1.8 V 1.2 - 1.5 VMaximum Power 90 W ( heat sink) 1.4 W (Portable) 130 W ( heat sink) 2 W (Portable)Gate Delay 12-13 ps 9-10 psVT 3sigma 50mV 40 mVOn Chip Across-Chip Clock 1200 600 1600 800On Chip Local Clock 1250 2100Chip to Board speed 1200 480 1600 885Transmit/Receiv Frequency (GHz) 3.5 2.5 7 5Transistor ft (GHz) 30 40Transistor NF ( db) 1.5 1.2Signal Isolation (S21) < -120 db < -120db Gain (db) > 20 > 20 db IIP (dbm) -4 -2.5 NF (db) 1.5 (Low noise

Amp)4 (Mixer) 1.2 ( Low noise

Amp)3 (Mixer)

ASIC• IR Drop• Design around

inductance• Crosstalk

• IR Drop• Inductance (some

design around)• Crosstalk

ASSP• IR Drop• Design around

inductance• Crosstalk

• IR Drop• Design around

inductance• Crosstalk

• IR Drop• Inductance (some

design around)• Crosstalk

µP• IR Drop• Design around

inductance• Crosstalk

• IR Drop• Design around

inductance• Crosstalk

• IR Drop• Design around

inductance• Crosstalk

• IR Drop• Inductance• Crosstalk

Analog/RF All the above issues and substrate coupling; Issues are very design dependent

0.35µ 0.25µ 0.18µ 0.13µ

Table 2: Snapshot of SI issues for SoC Designers

Al 3.0 µΩ -cmCu 1.7 µΩ -cmSiO2 κ = 4.0Low κ κ = 2.0Al & Cu .8µ Thick

Al & Cu Line 43µ Long

(Printed with permission of Prof. Schutte-Aine, University of Illinois)

0

5

10

15

20

25

Delay(ps) 30

35

40

45

650 595 540 485

Generation (nm)

SPEED/PERFORMANCE ISSUE

Gate Delay

Sum of Delays, Al & SiO2

Sum of Delays, Cu & Low K

Interconnect Delay, Al & SiO2

Interconnect Delay, Cu & Low K

430 375 320 265 210 155 100

Gate wi Al & SiO2

Gate

Figure 2: Snapshot of Interconnect PerformanceParameters for SoC Designs

2 POWER GRID

The trend of increasing design size and power consumption and decreasing supply voltage (thus increasing current)is resulting in an increase in the amount of power grid IR drop and ground bounce on chips. This trend is critical asthe IR drop and ground bounce noise margins are decreasing along with the supply voltage. Chip failures due topower grid issues, whether IR drop or electromigration, are already being discovered by chip designers. Since theseissues are related to the number and way components are assembled on a chip and are primarily a globalphenomenon, power grid analysis is becoming a required addition to many design flows. Of course, not all designsrequire power grid analysis, but increasing numbers are susceptible to problems.

In many designs the approach is to overdesign the power grid of the chip at the cost of metal consumption, whichwould otherwise be used for signal routing. The challenge facing designers is in determining how much of a powergrid is actually overdesign, especially if there is no testing of the grid. As the use of more and larger componentsincreases, this challenge becomes greater. In fact, even overdesigned grids can experience problems if the logicunder the grid is not sufficiently connected to the grid (for example, due to insufficient vias from the global grid tocomponent pins).

When components of a design do not see the specified power rail voltage, functional or timing failures will result.Functional failures result from insufficient power for the component to operate properly. Timing failures result fromgate delays increasing beyond the timing requirements of the paths (and ultimately cause setup or hold failures).These failures can be intermittent if the power voltage assumption is violated only under certain operatingconditions. Electromigration failures could even result in the failure of the chip at a customer site. Because powergrid issues are due to interactions between components and the global integration of components, a set of interfacespecifications are necessary to permit the verification of the power grid by the chip integrator.

Another signal integrity issue that will soon become significant while designing power grids is that of providingadequate current return paths to counter inductive coupling. Note that the operating frequency for the purposes ofinductance analysis is decided by the signal rise time and not the clock period. As ASIC and SoC designs movetowards the gigahertz domain and inductive reactances start becoming comparable to resistances, it will becomeimportant to extend the current role of the power grid as a capacitive crosstalk shield to also provide shielding forinductive noise. Although solutions as extreme as power planes that have been used in some high-endmicroprocessor designs will probably not migrate to ASIC and SoC methodologies, recent work on templated andinterdigitated routing in which a track is reserved for power after every few signal tracks seems promising forinductive noise handling in these contexts.

2.1 Power Grid Design: IP Block Author’s Perspective

Component authors generally have very little information about the quality of the power supply at the pins of thecomponent. A common methodology for SoC designs is for the component author and component integrator toagree ahead of time on the voltage to be applied to the component pins given the maximum current required by thecomponent. A typical approach is to assume a fixed level, say 5%, of power degradation to the component. Thecomponent author then ensures that the component operates to specifications under this assumption. As componentsincrease in size and are constructed hierarchically, it is the responsibility of the component author to modify thepower degradation assumption in order to ensure that the assumptions of the sub-components are maintained as theyare used in the larger components. Assuming uniform power degradation, results in conservative design (in manycases) because not all components see the fully-degraded power supply voltage. As designs increase in frequency,this conservatism leads to challenges in meeting timing closure on the chip, because the resulting overlyconservative gate delays inherently limit the operational frequency of the design. Of course, for hold-time checks,one should assume best-case IR drops rather than the worst case ones that are used to determine the operationalfrequency.

Components are also generally designed assuming that power enters only from the power pins. A growing trendtoday is that this assumption is not always valid – power commonly flows through components as well. Since theamount of current flowing through a component cannot be determined until chip integration, it should be possible to

specify current limits on the component pins to make sure electromigration limits of the component will not beviolated when integrated in the design.

A model is required to represent the power grid behaviors of a component. The model is created by the componentauthor and is applied by the chip integrator. The model must provide some visibility into the component’s internals.Because IR drop issues can be investigated in either a static or dynamic sense, various models of a component arepossible. In a static analysis, only power grid resistance data is required of the component. In a dynamic analysis,RC data of the component is required. The model of component power consumption must be a function of theloading on the component, so that the total power consumption of the component as well as any dynamic behaviorscan be derived once the component environment is determined. The component model must also be able to specifyacceptable ranges of input characteristics and output loading. Dynamic modeling will result in larger data sets torepresent the model.

2.2 Power Grid Design: IP Block Integrator’s Perspective

In general the design of the supply nets on chip level is based on a static DC model and guided by rules to avoid“hard to analyze” complications. Depending on the application, one might need some level of AC analysis but it isquite difficult to define a general approach.

Integrators have little knowledge of the internals of components, so they might not be aware of operatingassumptions the component designer made when designing the component. A common assumption is that powercomes into the component, and none passes through – this is not true in practice and has been the source of somefailures.

Another common source of disconnect is related to how power ports are specified for a component. If a largecomponent has a single long power port passing over the component, there can be questions as to how the portshould be used; the various options include only a single connection at one end, connections at both ends, oradditional connectivity midway as well. Since the way the component is connected to the global grid can even alterthe power grid characteristics in the component (for instance, a power rung of a component can be supplemented byadditional metal by the integrator), there must be some way of resolving power port usage models.

Integrators need to be able to assume that if the power noise requirements for a component are met, then thecomponent will function properly. In order to test this, the integrator needs appropriate models of the power grid ofthe components as well as how the components consume power about the component. The component author mayalso need to be able to provide specifications as to IR drop or electromigration at various points in the component.

Figure 3: Hook-up of Power for AnalogComponents in SoC Designs

Power and ground rings

Power and ground pins

SingleI/O

DoubleI/O

Collar+

Analog block

The integrator’s need for tools that are fast enough in analyzing the behavior of the chip after the components areassembled is also of utmost importance.

Finally, the power hook-up for analog components are often separate from those of the digital blocks, as shown inFigure 3. This prevention methodology is very effective.

3 INTERCONNECT CROSSTALK

Interconnect crosstalk can be defined as any deviation from the ideal signal waveform propagating in aninterconnect wire caused due to the influence of signal transitions in other wires in the neighborhood. This influenceis usually due to the capacitive coupling between the victim net and one or more aggressor nets, although inductivecoupling is also beginning to show up in cutting edge custom designs. Since ASIC and SoC designs tend to lagcutting edge designs by a generation or two, inductive noise is not yet a problem for these designs. Therefore, wewill focus solely on capacitive crosstalk in this section, since it is felt that the detailed analysis of inductive noise inthe context of SoC designs over the next few years will be important only for power grid and clock design, withinductive noise in signals being adequately controllable by a fine-grained templated power grid.

Capacitive crosstalk is manifested either as a degradation of interconnect delays resulting in a lowered operatingfrequency for the chip, or in outright failure of the chip. When two neighboring signals transition simultaneously,they can affect each other’s slew rate (and consequently, transition delay) depending upon their transition directions,relative driver strengths and wire parasitics. Thus, two signals transitioning in the same direction will tend to speedeach other up, whereas two signals transitioning in opposite directions will slow each other down. Delay degradationon critical nets can lower the operating frequency of the chip appreciably. In contrast, the failure effect is caused bythe voltage pulse induced on a quiescent victim net due to one or more aggressor nets switching in its neighborhood.This pulse can cause failure due to spurious transitions in non-restoring logic such as domino circuits. Failure canalso occur due to hold time violations in sequential elements caused due to signals being sped up due to crosstalk, orthese accelerated signals racing through open latches.

The problem of interconnect crosstalk is getting worse with each process generation due to non-ideal scaling ofwires. Since wires grow relatively narrower and taller with each generation (in order to keep their resistancemanageable), the ratio of the coupling capacitance of a wire to its total capacitance is increasing with eachgeneration. Although the move from aluminum to copper can halt this deterioration for a generation, successivegenerations will again have to tackle the same issues. Therefore, it is becoming increasingly important to account forcoupling during timing analysis. Besides forcing the timing analysis to deal with considerably more data (onneighboring nets), the unpredictability of the transition state of neighboring nets also has the secondary undesirableeffect of widening the transition windows of the signals. Furthermore, the larger error margins required insuccessive generations because of larger fractions of the total capacitance being (unpredictable) couplingcapacitance also makes the convergence of high performance designs more and more difficult. In contrast, thenumber of layers does not have much of an impact on the capacitive aspects of crosstalk noise (because of therelative shielding provided to a layer by adjacent layers). However, with increasing layer count, the analysis ofcurrent return paths and inductive noise becomes more complicated.

3.1 Interconnect Crosstalk: IP Block Author’s Perspective

Crosstalk coupling can occur within any pair of adjacent signals, irrespective of whether they belong to the samelogical/physical hierarchy or not. Thus, crosstalk noise can occur between IP block signals routed next to each other,between chip level wires lying next to each other, or between a chip level wire routed next to a IP block wire. It isthe third of these three cases that is unique to SoC designs. In each of the other two cases, the designer/integrator hassufficient design visibility and available data to analyze the crosstalk effects completely (although she may still haveto deal with the data overload issue). However, in the third case, the chip integrator may not have visibility insidethe IP block, and the block author may not have knowledge about the chip level environment of the block.

From a designer’s perspective, unexpected crosstalk coupling from outside the IP block shows up either throughincreased/decreased signal delays or in functional failures. The former effect arises due to simultaneous switching ina victim net within the block and one or more aggressor net(s) in the vicinity of the block, that results in thetransition within the victim being slowed down or sped up due to the coupling between the nets. The failure effectarises due to the voltage pulse induced on a quiescent victim net within the block due to the switching in one ormore aggressor net(s) in the vicinity of the block. All the usual problems of interconnect crosstalk are exacerbated inSoC designs, where IP block authors may not even be aware of the aggressors that will eventually lie in the vicinityof the block.

Although the techniques used to combat crosstalk noise vary from one design/integration house to another, it ispossible to abstract the issues that are common to all interconnect crosstalk scenarios. The data that needs to becommunicated for effective control of crosstalk noise effects across the boundary of the IP block can be listed at alevel high enough to be largely independent of the signal integrity methodologies and algorithms employed by thedesigners and integrators. Ideally, it includes some metrics for the maximum permissible noise (including slew andtransition window requirements) at the input ports and the maximum noise possible at the output ports (includingslews and transition windows and their variation with external load). The IP block author can also specify externalno-fly zone/shielding requirements or the locations of crosstalk sensitive interconnect polygons (and potentialaggressors, if any, for external wires). The goal is to present a simplified yet reasonably accurate model for the IPblock while still preserving its gray/black box nature. In a similar vein, although crosstalk due to the board andpackaging is out of the scope of this document, it is important to note that some interface modeling may be requiredeven for these levels of the hierarchy in order to analyze and optimize crosstalk accurately.

3.2 Interconnect Crosstalk: IP Block Integrator’s Perspective

From the integrator’s point of view, the main difficulties in analyzing the crosstalk noise effects accurately are thelack of visibility into the IP block and the massive amount of electrical and physical interconnect data andlogical/timing window data required for accurate analysis. The second of these problems is not specific to the SoCcontext, and must be dealt with even in flat designs (or with soft/firm IPs). However, as outlined above, one canabstract the data that should be communicated between the IP block author and the integrator in order to enable thelatter to get around the first problem (viz., lack of visibility) while analyzing crosstalk effects.

Since capacitive crosstalk noise is largely a local phenomenon, the physical design of the IP block has a huge impacton the seriousness of the noise problem. If the IP is firm or soft, there are two approaches that can be used to handlecrosstalk noise issues. The conservative approach is to increase the delay error bars and flag every gate that can be apotential failure in the worst possible physical realization of the IP block. However, not only is this undulypessimistic, but it also suffers from the fact that the “worst possible physical realization” can often not be identifiedeasily. Thus, a more realistic approach to handling firm or soft IP is for the block author to identify the set of signals(if any) that the author feels may be critical, and then communicate maximum coupling ratio or required shieldingconstraints for them. The integrator must then take these constraints into account while doing the physical design ofthe chip; the integrator's added visibility into the IP blocks will allow the application of the standard crosstalk noisemethodology to the entire chip (including the IP blocks).

3.3 General Techniques for Handling Interconnect Crosstalk

The basic approaches to handling crosstalk noise are either by controlling the signal slew (by driver/receiver sizingor repeater insertion), or by reducing the ratio of bad coupling capacitance of a net to its total capacitance (by wireengineering). The first approach is usually used for timing optimization of the circuit, with its noise optimizationbeing a secondary objective function, whereas the second approach is used specifically for noise optimization whenthe sizing and repeater insertion is insufficient by itself to overcome noise effects. Wire engineering can includetechniques like the insertion of additional power lines for use as shields, permutation of the order of the signals in arouting region to exploit logically or temporally exclusive signals as relative shields, wire spacing, and, to a smallereffect, wire tapering. (As with sizing, the primary role of tapering is to optimize the RC delay of the wire, with noisebeing a secondary objective if needed). Since exact analysis and optimization of each wire is often too expensive tobe practical (and is often not possible across the boundary of the IP block due to lack of visibility/information aboutneighboring wires), coarse level techniques like reserving an entire layer as a shielding layer around the block, oridentifying specific no-fly zones above the block can be used. Furthermore, feedthroughs (due to over the block

wiring) in layers that are also used by the block may be restricted to tracks that have been expressly reserved forthem and certified by the block author as being safe (rather than being routed opportunistically wherever tracks areavailable).

A general observation is that since coupling is only going to get worse with shrinking geometries, it is moreimportant to have a design style that focuses on reducing coupling rather than relying on measuring it accurately andthen fixing problems as they occur. As mentioned earlier, capacitive crosstalk can be handled at each stage from pre-layout sizing to global routing to detailed routing. In general, crosstalk problems are difficult to identify but easy tofix early on. In contrast, they become much easier to identify as one moves down the physical design flow; however,there is correspondingly less flexibility available to fix them at these later stages.

The primary problem in analyzing crosstalk effects accurately (especially during timing analysis) is dealing with ahuge amount of data (pertaining to the neighbors of victim nets). This exacerbates the data overload problemsignificantly, requiring a practical tradeoff between accuracy and timing analyzer capacity. Since it is usually onlythe largest few aggressors that result in the majority of the coupling experienced by a victim, all but the largest fewaggressors of a victim can usually be ignored. Similarly, given the error bars due to the unpredictability of worstcase coupling, one can usually survive with simplified 2D models for coupling (except for the most critical nets orbusses that may require 2.5D or 3D modeling). Decisions about the precise number of aggressors (or the precisepercentage of coupling that should be accounted for by the aggressors selected from the list of aggressors sorted indecreasing order) usually vary from design to design. Similarly, the choice of the coupling model is also usually aproprietary issue with each design house. In fact, multiple models may be used within the same design based on netcriticality. However, it is often useful to handle the majority of nets that are non-critical through a simplified statictiming flow and just add a margin for coupling-caused delay/speedup. Accurate analysis of the timing effects ofcrosstalk is considerably difficult with the static timing tools widely deployed today; one is forced to rely onheuristic weighting of the couplings (through Miller Coupling Factors) to estimate the effect of crosstalk. Therefore,critical nets need to be analyzed in more detail using dynamic timing tools (although there is the non-trivial problemof ensuring that vectors used by the dynamic validation flow indeed correspond to the worst case).

4 SUBSTRATE NOISE COUPLING

Substrate coupling occurs in many types of circuits, from small Radio Frequency (RF) designs to large embeddedmemories. The key aspect of the problem is the flow of AC currents in the substrate. These currents are generatedby fast-switching (typically) digital devices. For designers, typically designs where problems occur includeembedded Data Converters or memories in large ASIC or ASSP ICs.

Many designers today still design with Standard BULK (EPI) heavily-doped CMOS processes to avoid latch-up,which leads to a substrate voltage equivalent to the digital ground bounce. However, as technologies scale below0.18 microns, designers either are deciding to design around latch-up or the supply voltage is becoming so low thatlatch-up becomes very hard to occur. Therefore, many designers have now returned to high-ohmic bulk substratematerial. The additional benefit, next to lower process costs, is that noise propagation through the substrate is muchlower, and partly controllable by guard rings. However, the rapidly increasing need for higher levels of analog andRF block integration in SoC designs - especially functional blocks such as wireless communication RF receivers at900+ MHz - drive the substrate coupling problem up rapidly.

With all this in mind, designers are faced with a difficult problem of authoring accurate analog blocks in a digitalprocess which will function in unknown substrate environments. This problem inherently limits how aggressive thespecifications of the analog blocks can be. Moreover, the integrator of the blocks must be able to verify that thesubstrate noise will not cause certain blocks to fail - or at least the verification of the integrated block must beaccurate and efficient - before the integrator will consider integrating the block. Currently, very little technologyexists in the way of CAD (EDA) tools and methodologies, that the designer can rely upon for verification ofsubstrate coupling in the SoC design process. This is because SoC designs tend to be large IC's, and the extraction(and then analysis) problem is mathematically intense - and sometimes complex, depending on the substrate dopinglayers. Thus, the practice is to use design techniques, which are discussed in this section.

4.1 Substrate Coupling: IP Block Author's Perspective

A block author needs to be careful to plan for guard rings and provide clear guidelines for the integrator to follow toallow for more robust design (see Block Integrator's Perspective below). Each of these ideas has an associateddollar cost that makes them not always possible. Often, circuits are just designed to be robust (through overdesignand differential techniques) and a lot of slack is built into the required performance specifications. However, this isvery difficult to do with upcoming standards such as Bluetooth and 3G where the analog and RF blocks are verydifficult to design even by themselves (since they operate at 2.45 GHz).

Many foundries are introducing options such as triple-well process for isolation on their Standard CMOS process toallow Analog/RF block integration,. Such options are very practical, although expensive. The block author canstipulate such options to the integrator, but this may limit the number of customers for the block, since not all SoCdesign houses are willing/able to use such options.

4.2 Substrate Coupling: IP Block Integrator's Perspective

As integration levels rise for analog, RF, and sensitive custom digital blocks, the skill base of the integrator needs tochange - from predominantly understanding issues in Standard Cell ASIC block integration, involving a smallnumber of analog blocks, to understanding the multitude of intricate power, interconnect, and substrate issues withmany highly sensitive blocks. The whole parasitic model for the IC (including the package and possibly the PCBback to the power supply) needs to be modeled. Figure 4 shows a simplified view of such a model. In practice, thismeans that designers, typically experienced in the timing-area trade-off, now need to be equally experienced in SIissues right from the initial spec-ing phase.

4.3 General Techniques for Handling Substrate Coupling

There are a number of useful methods for reducing substrate coupling in uniform non-EPI processes:1. Place multiple guard rings around the sensitive IP blocks to isolate them. Note that these guard rings can be

noise generators themselves if poorly designed (for instance, if they are left ungrounded).2. Ground the guard rings on dedicated bond pads and even dedicated package pins. This is not always possible,

but some intelligent hook-ups can still be made to avoid connecting sensitive and noisy nets.3. Use floorplanning intelligently to keep noisy digital IP blocks away from sensitive blocks - see Figure 5.4. Plan the frequencies of the noisy digital clock and the analog circuitry to be different (including possible

overlaps in harmonics). This is possible in the substrate, but not so much in the supply rails.

Figure 4: Simple Model of the Parasitics inSoC Designs

Package, RLC

Substratemodel, R (C)

Bond padand bond

wire, RLC

Interconnectcoupling, C (RL)

Interconnect,RC(L) π model

Guardring, with very

low R

High speeddigital circuits

Low speeddigital circuits

High amplitudeanalogue circuits

Medium amplitudeanalogue circuits

Low amplitudeanalogue circuits

Digital outputbuffers

P+ Guard Rings

5. ACKNOWLEDGEMENTS

Much of the content of this paper has been derived from ongoing work in the Virtual Socket Interface Alliance(VSIA) on the determination of Signal Integrity Specifications and Standards for SoC designs [4]. The authorswould like to thank Henry Chang, Chair of the Analog Mixed-Signal Development Working Group of the VSIA, forsupporting this work.

6. REFERENCES

[1] Surviving the SoC Revolution, by H. Chang et al, Kluwer Academic Publishers, 1999.[2] System-on-a-Chip Verification: Methodology and Techniques, by P. Rashinkar et al, Kluwer AcademicPublishers, 2000.[3] International Technology Roadmap for Semiconductors, http://public.itrs.net[4] Virtual Socket Interface Alliance, http://www.vsi.org

Figure 5: A Simplistic Approach to Substrate-aware Floorplanning in SoC Designs