page 1el/ccut t.-c. huang nov. 2003 tch ccut introduction to ic design tsung-chu huang ( 黃宗柱 )...

EL/CCUT T.-C. Huang Nov. 2003

TCH

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Introduction to IC DesignIntroduction to IC Design

Tsung-Chu Huang(黃宗柱 )

Department of Electronic Eng.Chong Chou Institute of Tech.

Email: [email protected]

2003/11/24


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Clocking Strategies1. Clocked System 2. Latch and Registers3. System Timing (Constraint)4. Single-Phase Memory5. Phase Locked Loop Clock Techniques6. Metastability and Synchronization Failure7. Single-Phase Logic Structure8. Two-Phase Clocking9. Two-Phase Memory Structure10.Two-Phase Logic Structures11.Four-Phase Clocking12.Four-Phase Memory Structures13.Four-Phase Logic Structures14.Clock Distribution


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Clocking StrategiesHuffman Model for a Finite State Machine (review)

Q DQ DQ DQ D

CombinationalCircuit

PI: Primary Inputs

PPI: Pseudo PI

PO: Primary Outputs

PPO: Pseudo PO

Clk

M

L

N

M

MS 2Count State


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Clocking StrategiesBasic Loop Timing Constraints (review)

Q DQ DQ DQ D

C

QDDQp ttt :n timePropagatio

DCCDs ttt : timeSetupCQQC tt : timeQ-to-Clock

T

1 : timeCycle DCQDCQ tttTf

setup

hold


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Clocking StrategiesTiming Constraints Considering Jitter & Skew (review)

SKJTDCQDCQ tttttTf

1

Q DQ DQ DQ D

Clk

JitterSkew


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LatchFunction (review)

1. Level-Enabled (E, EN, Enable, Clk)2. Function: Q=D if E=1

No Change if E=0

D Q

EN

ENHigh-Level Enabled

D Q

EN

ENLow-Level Enabled


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RS Latch(review)

S

RQ

Q S

RQ

Q

S

R

Q

Q

EN


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D Latch(review)

1

0

D

EN

Static:

0

1

D

EN

Dynamic:

Clk Clk

D QWeak-Static:


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Multiplex(review)

A

B

0

1

A

B

C

CBACZ

A

B

CZ

C


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Transparent Output

D Q

EN

D Q

EN

tPG

1Φ 2Φ

1Φ

2ΦtPG


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Flip-FlopsFunction (review)

1. Edge-Triggered2. Usually consisted of a low- and a high latches

D Q

EN

Clk

D Q

EN

D Q

EN

Clk

D Q

EN

D Q

Clk

D Q

Clk


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Flip-Flops without Transparency

D Q

EN

Clk

D Q

EN

ClkΦ 1

ClkΦ 2

Fully self-constrained!


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Flip-FlopsA static positive-edge D Flip-flop (Vdd>2Vt) (review)

D

Clk

Q


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Synchronous v.s. Asynchronous ControlSettable, Resettable, etc.

Synchronous Asynchronous

Structural

Behavioral

Control Q

No Clk in the path to Q

Control Q

With Clk in the path to Q

always @(posedge Clk or posedge Control)if(Control) Controlled_state;else Clocked_circuit;

always @(posedge Clk)if(Control) Controlled_state;else Clocked_circuit;


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Clock BufferingClock Tree with a branchDegree of 3 or 4 (~ 2.718)without consideration of route

A single large buffer:


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H-Tree


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Contra-data Direction Clock

Clk

D QD QD QD Q D QD Q

RC

Data

CQDCRC ttt

Clk

D QD QD QD Q D QD Q

RC

Data

PGCQDCSKRC ttttntT Generally,


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Phase Lock Loop (PLL)

PhaseDetector

ChargePump LPF VCO

FrequencyDivider

U

D

nfo /

of

nfo

if

1. Skew Reduction; Synchronization2. Frequency Multiplier3. Data Recovery


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A Typical VCO

Current mirror

180-degree oscillator

Vc

fo


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VCDLVoltage Control Delay Line

Vc

toti


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PLL Clock Generator

ClockPLL

D Q

PLL

D Q


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PLLs Applied to Different DomainsSkew (ps)

Equivalent Distance (ps)Max Skew PLL1

PLL2

PLL3

CLK


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Metastability & Synchronization Failure

Wanted D

ataN

ext Data

Clock

Setup

Hold

Wanted D

ataN

ext Data

Wanted D

ataN

ext Data

Wanted D

ataN

ext Data

Q

Q

Q

Q

Logic Error!


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Skew-Tolerant Design

1. Reverse Order of Clocking for only scan 2. Skew-Tolerant Dynamic Circuit3. Skew-Tolerant Domino4. Clock Domain Ranging


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Single-Clock Complementary PhaseCombinational

Circuit LCombinational

Circuit H

DHQL DL QH

Clk

XL XH

TL

TH

CDLt

HCQt

HHDQt

CDHt

LCQt

LLDQt T


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Single-Clock Complementary Phase

CDLt

HCQt

HHDQt

CDHt

LCQt

LLDQt T

Timing Diagram

DL

Clk

DH


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Single-Clock Double Edge

1. Can slack the master clock only. 2.

TL

TH

Q DQ DQ DQ D

CombinationalCircuit

SKJTDCQDCQHLHL tttttTTTTf

) ,min( ;1


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Single-Clock Complementary PhaseLatch System

CombinationalCircuit L

CombinationalCircuit H

DHQL DL QH

Clk

XL XH

TL

TH

Data Transparency!


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Single-Clock 2 Phase

1Φ

2Φ

CombinationalCircuit 1

CombinationalCircuit 2

D2 Q2

X2 X2

1Φ2Φ

Q1 D1


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Comparison of some DFF’s

D

Clk

Q

Q

Q

D

Clk

ClkClk

21

1:11:1

21static

dynamic#clock

1

1

1

1

1

#phase

1

1

C

2

2

local load

contention

Vt degrading


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N-Phase Clock Notations

divisions. into divided is cycle a e,conveniencFor N

NN 1or )1(0

division.th in theonly levelhigh a hasit that denotes iΦi

1Φ

2Φ

3Φ

4Φ

23Φ


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4-Phase FF

1Φ

2Φ

D

3Φ

4Φ

Q

12Φ 34Φ

PrechargePrecharge

Redistribute

Evaluate

PrechargePrecharge

Redistribute

Evaluate1Φ 3Φ


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Johnson Counter

0D 1

1D 1

2D 2

3D 2

4D 3

5D 3 D 4

n

-22n

D 4n

-12n

C lk= 1

(a )

0D 4

n

1D 1

2D 1

3D 2

4D 2

5D 3

-22n

D 4n -1 D 4

n

-12n

C lk= 0

(b )


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Multiple Phase Clock Generator

0D Q

Q1

D Q

Q

D Q

Q-2n

2

D Q

Q-1n

2DD Q

Q

C lkR ese t

n -2n -30n -1 -2n2-3n

2n2-1n

2

C lk /2


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Clock Domain Programming

Ske w

Frequency

multiplicity

Phase


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Clock Domain InterfaceLatch-base

BuferLeading Phase

LogicLagging Phase

Logic

Latch-baseBufer

Lagging PhaseLogic

Leading PhaseLogic with

1 cycle delay

SIPOInteger-TimesFrequency

Low--FrequencyCircuit

PISOLow-FrequencyCirciut

Integer-TimesFrequency

PLLData Recovery

Skewed or Remote

Clock recoveredBut delayed


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Clock Gating Problem

D3 Q3

1Φ

Gating

D1 Q1

D2Q2

3Φ

2Φ

GatedUngated

CQt

QDtDCt

Discussed in advanced topic and should be careful!


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A Simple Clock Gating Condiction

1. Single Clock, Single Phase, Positive-Edge Trigger for Ungated and Gated Circuits

2. Gating Signal can be synchronized at negative edges and generated from the complementary clock domain.

3. Assme Clock Gating delay: tCG

CGSKJTDCQDCQ ttttttTf

2 1

page 1el/ccut t.-c. huang nov. 2003 tch ccut introduction to ic design tsung-chu huang ( 黃宗柱 )...

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