paper 33-fpga triggered space vector modulated voltage

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FPGA Triggered Space Vector Modulated Voltage Source Inverter Using MATLAB/System Generator® P.Geeth Prajwal Reddy SSN College of Engineering International Conference on Advances in Power Electronics and Instrumentation Engineering 1

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Page 1: Paper 33-FPGA Triggered Space Vector Modulated Voltage

FPGA Triggered Space Vector Modulated Voltage

Source Inverter Using MATLAB/System Generator®

P.Geeth Prajwal Reddy

SSN College of Engineering

International Conference on Advances in Power Electronics and Instrumentation Engineering 1

Page 2: Paper 33-FPGA Triggered Space Vector Modulated Voltage

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Voltage Source Inverter (VSI) VSI is a power electronics topology of switches that facilitates the conversion of Direct Current (DC) to Alternating Current (AC) While the VSI has six switches, it is mandatory that only one switch in each leg can be turned on at any instant, thus 8 different switching states are possible, i.e. the combination in which the switches are turned ON. However the use of the VSI in the conventional manner or normal Pulse Width Modulation (PWM) gives rise to an AC of a Sine wave with large harmonics

Objective of Space Vector Modulation(SVM)

International Conference on Advances in Power Electronics and Instrumentation Engineering

Ib Vb

VDC+

S1

Ia Va

VDC

VDC-

S3

S2

S4

S5

S6

Ic Vc

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3 International Conference on Advances in Power Electronics and Instrumentation Engineering

Switching States of VSI

At any instant, it is mandatory that only one switch in each leg of the VSI can be ON, to prevent short circuit of the source. Each switching state is represented by ON-OFF status (1-0) of the upper arm switches of the VSI, while the status of the lower arm switches would be their complement. The possible switching states of the VSI are listed

VSI Switching State Vectors

Type Vector 𝑆1 𝑆2 𝑆3𝑆4 𝑆5 𝑆6

Va Vb Vc 𝑉𝑂𝑈𝑇 ∠𝑉𝑂𝑈𝑇

Active

V1 [100] 1 0 00 1 1

2

3𝑉𝐷𝐶 −

1

3𝑉𝐷𝐶 −

1

3𝑉𝐷𝐶

2

3𝑉𝐷𝐶 0

V2 [110] 1 1 00 0 1

1

3𝑉𝐷𝐶

1

3𝑉𝐷𝐶 −

2

3𝑉𝐷𝐶

2

3𝑉𝐷𝐶

𝜋

3

V3 [010] 0 1 01 0 1

−1

3𝑉𝐷𝐶

2

3𝑉𝐷𝐶 −

1

3𝑉𝐷𝐶

2

3𝑉𝐷𝐶

2𝜋

3

V4 [011] 0 1 11 0 0

−2

3𝑉𝐷𝐶

1

3𝑉𝐷𝐶

1

3𝑉𝐷𝐶

2

3𝑉𝐷𝐶 𝜋

V5 [001] 0 0 11 1 0

−1

3𝑉𝐷𝐶 −

1

3𝑉𝐷𝐶

2

3𝑉𝐷𝐶

2

3𝑉𝐷𝐶

4𝜋

3

V6 [101] 1 0 10 1 0

1

3𝑉𝐷𝐶 −

2

3𝑉𝐷𝐶

1

3𝑉𝐷𝐶

2

3𝑉𝐷𝐶

5𝜋

3

Zero V0 [000] V7 [111]

0 0 01 1 1

1 1 10 0 0

0 -

Active Vectors alter the Phase angle of the output AC Zero vectors are used to make the magnitude variation of the output AC sinusoidal

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Space Vector Modulation (SVM) Using Clark Transform, the resultant Three Phase AC is modeled as a single Phase AC

𝑉𝛼𝑉𝛽

=2

3.1

−1

2

−1

2

03

2

− 3

2

𝑉𝑎𝑉𝑏𝑉𝑐

Where, Vα is the Magnitude Vβ is the Phase Angle of the 1φ AC

Plotting Vα and Vβ we get a rotating vector, this is called the Space Vector, as shown below

1

2

3

5

6 4

Va

Vb

Vc

V1(100)

V2(110) V3(010)

V4(011)

V5(001) V6(101)

Output AC waveform on application of switching states of VSI

V1(100)

V2(110)

V3(010)

V4(011)

V5(001)

V6(101)

V0(000)

International Conference on Advances in Power Electronics and Instrumentation Engineering

Page 5: Paper 33-FPGA Triggered Space Vector Modulated Voltage

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Space Vector Modulation (SVM) Modeling of 3 Phase Alternating Current as a Space Vector

International Conference on Advances in Power Electronics and Instrumentation Engineering

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Ideology of Space Vector Modulation Thus in order to obtain a sinusoidal AC with minimal Harmonics, SVM utilizes the “Equal Area Theorem”

A reference vector is taken to rotate around the Switching State Hexagon at a frequency of the required value. Based on the position of the Reference Vector, the Switching states are applied for a specified time period

𝛿1 = 𝑚𝑣 . sin 𝜋

3− 𝜃𝑟

𝛿2 = 𝑚𝑣 . sin 𝜃𝑟

𝛿0 = 1 − 𝛿1 + 𝛿2

Vx

Vy

δ2Vy VREF

δ1Vx

θr

SVM Inductor

International Conference on Advances in Power Electronics and Instrumentation Engineering

Page 7: Paper 33-FPGA Triggered Space Vector Modulated Voltage

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Timing Diagram of Switching Vectors

δ1

δ1+δ2

T1

2

T0

TS

Vx

Vy

V0

Triangular Wave (Carrier)

Zero Vector

Active Vectors

Time

Duty

Cycl

e

T2

2

T2

2 T1

2

International Conference on Advances in Power Electronics and Instrumentation Engineering

SVM in Symmetric switching

Page 8: Paper 33-FPGA Triggered Space Vector Modulated Voltage

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Digital Implementation of SVM- Block Diagram

International Conference on Advances in Power Electronics and Instrumentation Engineering

Reference Vector Angle

Triggering Pulses

Duty Cycle Calculation

Time Period Calculation

Internal Theta

Gating Pattern

Switching State Vectors

Sector Number

v

3 Phase AC Voltage

DC Voltage Source

Voltage Source

Inverter

v

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Stages of Implementation

1

3

2

Reference Vector has magnitude constant but angle alone changes, thus a counter is used to generate the change in angle from 0 to 360 degrees

Sector Number or the sector in which the Ref. Vector is currently in, is identified by comparing the value of the counter with the angles of the sectors and passed on to the next block

1

2

3

5

6 4

Va

Vb

Vc

V1(100)

V2(110) V3(010)

V4(011)

V5(001) V6(101)

Vx

Vy

δ2Vy VREF

δ1Vx

θr

The vector pair enclosing that sector are then identified, i.e. the Switching state vectors that govern the output AC in that sector

International Conference on Advances in Power Electronics and Instrumentation Engineering

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Stages of Implementation

4 Based on the Switching state Vector , the corresponding Gating Pattern, or the indication of which switches of the Inverter are to be turned ON are generated.

Consider a switching state vector V1(100) whose sequence (100011) is treated as a binary number, 1000112 and is represented by its equivalent decimal value, 3510

Switching Vectors

Decimal Equivalent

V1 35

V2 49

V3 21

V4 28

V5 14

V6 42

International Conference on Advances in Power Electronics and Instrumentation Engineering

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6

In order to calculate the duty cycles, Internal ϴ , i.e. the angle the reference vector makes within a sector, this is done as follows

The Carrier Wave, for modulation, is a triangular wave of high frequency

Stages of Implementation

5

International Conference on Advances in Power Electronics and Instrumentation Engineering

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Stages of Implementation

7 With all the required parameters available, the duty cycles for each switching vector are calculated.

Sin ϴ Calculation using CORDIC Sin-cos block

Duty Cycle Calculation

International Conference on Advances in Power Electronics and Instrumentation Engineering

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Stages of Implementation

8 Finally the appropriate Gating pattern is generated and using ‘Bit slice’ option, individual bits of the gating pattern are obtained and applied to the switches of the Voltage Source Inverter

International Conference on Advances in Power Electronics and Instrumentation Engineering

Important Parameter

Explicit Period : The time period of the operations of the digital circuits are determined by the value of the explicit period, which is given by :

𝑅𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑇𝑖𝑚𝑒 𝑃𝑒𝑟𝑖𝑜𝑑 = 𝑀𝑎𝑥 𝐶𝑜𝑢𝑛𝑡 𝑣𝑎𝑙𝑢𝑒

𝑅𝑒𝑠𝑜𝑙𝑢𝑡𝑖𝑜𝑛× 𝐸𝑥𝑝𝑙𝑖𝑐𝑖𝑡 𝑇𝑖𝑚𝑒 𝑃𝑒𝑟𝑖𝑜𝑑

Where ‘x’ bits give the maximum digital value that can be accounted in the circuit and ‘y’ binary point bits provide the necessary resolution for the transition of digital values Thus for a given required digital value, resolution and time period of operation, the explicit period is calculated and entered in the parameters of the appropriate block of the Xilinx Blockset.

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Digital Implementation of SVM using Xilinx Blockset

International Conference on Advances in Power Electronics and Instrumentation Engineering

Shown above is the working layout that is used to implement the SVM algorithm in Matlab using the Xilinx Blockset of Simulink

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15 International Conference on Advances in Power Electronics and Instrumentation Engineering

Simulation Results The simulation results not only proved the success of Space Vector Modulation (SVM) in producing sinusoidal AC with minimal harmonic distortion but also confirmed the proper functioning of the digital implementation of the SVM

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Real Time Implementation of SVM

Field Programmable Gate Array (FPGA), one of the most recent additions to the family of Logic Devices, is highly user reconfigurable and possess very high processing speeds. Thus apt for implementation of SVM algorithm.

Since the FPGA is capable of generating digital output pulses, it is used to generate the triggering pulses to ON/OFF the switches of the Inverter as per the SVM algorithm. FPGA uses Very high-speed integrated circuits Hardware Descriptive Language (VHDL) coding

System Generator/ Xilinx Blockset These are two utilities present in Matlab, similar to the Powergui and SimPower blockset. With the help of the Xilinx Blockset, digital circuits can be simulated and the System Generator Converts that circuit into its equivalent VHDL code International Conference on Advances in Power Electronics and Instrumentation Engineering

Page 17: Paper 33-FPGA Triggered Space Vector Modulated Voltage

17 International Conference on Advances in Power Electronics and Instrumentation Engineering

Using the System Generator (SG) utility, the digital logic simulated using the Xilinx Blockset of Matlab Simulink is converted into the VHDL code. This code is compiled in Xilinx ISE Design Suite to generate the ‘bit file’ which is loaded into the FPGA using the software Adept. Thus the FPGA now is capable of generating the triggering pulses for the switches of the VSI to generate sinusoidal AC from DC.

Current and Voltage waveform as observed on the Agilent DSO on real time implementation of SVM using FPGA

Real Time Implementation of SVM

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18 International Conference on Advances in Power Electronics and Instrumentation Engineering

On application of the 3- Φ output voltage of the inverter to the induction motor load, rated at 1HP, 1.8A, 50Hz, 1430 RPM, the following results were tabulated.

Comparison of Results

Comparison of Results

Matlab Simulation Practical Implementation

Line-to-Line Voltage (Peak)

415 V 400V

Line Current (rms) 1.1 A 0.8A

Frequency 50 Hz 50.0 Hz

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19 International Conference on Advances in Power Electronics and Instrumentation Engineering

Advantages of Using FPGA • Economically, FPGAs are lot more cheaper than DSP processors • Easily reconfigurable • Comparatively more user friendly in terms of programming and implementation, which

is further more simplified with the help of Xilinx Blockset and System Generator of Matlab Simulink

• FPGAs are very high processing power to size ratio, i.e. even small FPGA boards are capable of high Processing capabilities.

Advantages of Space Vector Modulation

• Very low Value of harmonic distortion (THD) can be achieved in the output waveform • Robust Dynamic response • SVM enables more efficient use of the DC Voltage Space Vector Modulation provides excellent output performance, optimized efficiency, and high reliability compared to similar inverters with conventional Pulse Width Modulation.

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20 International Conference on Advances in Power Electronics and Instrumentation Engineering

References • Dorin O. Neacsu, "Space Vector Modulation-An Introduction", Proc.IEEE/IECON, 2001,

pp 1583-1592. • Application Guidelines- Integrating Xilinx System Generator and Simulink HDL Coder. • B.K.Bose, 1986, Power Electronics and AC Drives, Prentice-Hall. • Jin-Woo-Jung, (2005), "Space Vector PWM Inverter", DECE, The Ohio State University. • System Generator for DSP Getting Started Guide. • www.mathworks.com • Harrison, C.G.; Jones, P.L.;, "Xilinx FPGA design in a group environment using VHDL and

synthesis tools," Digital System Design Using Synthesis Techniques (Digest No: 1996-029), IEE Colloquium On , vol., no., pp.5/1-5/4, 15 Feb 1996.

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Thank you and a pleasant evening to all

“True knowledge exists in knowing that we know nothing.” - Socrates

“Learning will be my life, my tombstone will be my diploma” - Eartha Heart