PART-A

1. What is radix? Give the radix for binary, octal, decimal and

hexadecimal

Radix is the total number of digits used in a particular number

system

Binary - 2 (0,1)

Octal - 8 (0 to 7)

Decimal - 10 (0 to 9)

Hexa Decimal - 16 (0 – 9 and A= to F)

2. Expand ASCII and BCD

ASCII – American Standard Code for Information Interchange

BCD – Binary Coded Decimal

3. Give the one‟s and two‟s complement for 1010

One‟s complement = 0101

Two „s complement = 0110

4. Perform the simple binary addition for

(1) 1011 +1001

(2) 1011+110

Add 1011+1001 Add 1011+110

1 0 1 1

+ 1 0 0 1

1 0 1 0 0

1 0 1 1

+ 1 1 0

1 0 0 0 1

5. Perform simple binary multiplication Multiply 1100 x101

6. Perform Binary Division

Divide

11011 / 100

Ans: (110.11)2

7. What do you mean by positive and negative logic

There are two ways of assigning the Boolean values 0 and 1 to the two voltage levels Low and High of a circuit.

1 1 0 0 x

1 0 1

1 1 0 0

0 0 0 0

1 1 0 0

1 1 1 1 0 0

1 1 0 . 1 1

1 0 0 1 1 0 1 1

1 0 0

1 0 1

1 0 0

1 1 0

1 0 0

1 0 0

1 0 0

0

In the positive logic interpretation, LOW = 0 and HIGH = 1 In negative logic, LOW = 1 and HIGH = 0 . 8. Draw the symbol of X-NOR gate and give its truth table.

EX-NOR GATE:

The EX-NOR operation is the complement of XOR operation. The

output of EX-NOR is HIGH only when the logic values of both inputs

A and B are same ie. either both are 1 or both are 0. Its output is 0

when its inputs are different.

The truth table and the symbol are shown below. Here A and B

are two inputs and the output is BA = A. B +B . A

9. Explain NOR and AND

NOR as AND Gate:

INPUT OUTPUT

A B Y= BA

0 0 1

0 1 0

1 0 0

1 1 1

INPUT OUTPUT

A B Y=A.B

0 0 0

0 1 0

1 0 0

1 1 1

Here, the first two NOR gates inverts the input variables as A

and B . Then, the two input NOR gate produces an output as A + B

which gives the output of AND gate as A . B =A.B

10. Give associate law and commutative law of Boolean postulate

with proof

Commutative Laws

Commutative laws states that the order of adding or multiplying

is not important. In other words, we get the same answer by adding

X to Y as we do by adding Y to X. Similarly in multiplication also

X.Y=Y.X

1. X+Y=Y+X

2. X.Y=Y.X

Associative Laws:

The expression can be expanded by multiplying term as in

ordinary algebra. The associative laws states that we can group any

two terms of a sum or any two factors of a product. In other words,

give X+Y+Z. we can first add X and Y, and then add the result to Z.

In other words, we can add Y and Z and then add the result to X.

3. X.(Y.Z)=(X.Y).Z=X.Y.Z

4. (X+Y)+Z=X+(Y+Z)=X+Y+Z

11. Explain minterm and maxterm with examples

A minterm is a product of all the variables within the logic

system, complemented or not. Thus, if x and y are the

variables, then the minterms are xy, x y, x y , x y .

A maxterm is a sum of variables within the logic system,

complemented or not. If x,y,z are all the variables within a

system, the following are the maxterms. Eg. (X+ Y‟), (X+ Y)

12. Define Quad, Pair

Quad: Four adjacent one‟s in Karnaugh Map

Pair : Two adjacent one‟s in karnaugh map

13. Discuss two variable map

TWO Variable map: The first row is for B the second row is

the first column is for A for B. Similarly

and the second column is for A.

To identify the square, the variables in both row and

column are identified. For the first square of the first row, the

variables are B & A and it represents the product term A B .

A A

B A B A B

B A B AB

14. Simplify the following Boolean Expressions Using

Karnaugh Map A BC +ABC + A BC+ABC+A B C + A B C

C

B Solution: B+C

15. Show that Show that: (A+B)(A+C)=A+BC

=AA+AC+BA+BC

=A+AC+BA+BC

=A(1+C)+BA+BC

=A+BA+BC

=A(1+B)+BC

=A+BC

16. What is don‟t care ?

The minterm is a combination of variables, whose logical

value is not specified. It cannot be marked with a 1 in the map

because it would require that the function should always be a 1

for such a combination. Putting 0 on the square requires the

function to be 0. To distinguish, the don‟t care condition from

1s and 0s, the multiplication symbol “x” is used. Thus an “x”

inside a square in the map indicates that we don‟t care whether

the value of 0 or 1 is assigned to the function for that particular

minterm.

A B A B AB A B

C 1 1 1 1

C 1 1

17. What is prime implicant?

In a “Sum of Product” expression, each product term is known

as implicant. On a K-Map, each implicant relates to a single „1‟

square or a group of adjacent „1‟ squares. A prime implicant is an

implicant which cannot be wholly enclosed by a larger implicant on a

Karnaugh Map. A non-essential prime implicant can be removed

without leaving any „1‟ square and enclosed.

A B A B AB A B

C D 1 1 1 1

C D

CD 1

C D

Prime Implicant

18. Draw the circuit and truth table for half adder

In half adder, There are two inputs A and B and two

outputs sum and carry . Sum column is labeled with

summation symbol Σ and the carry column is labeled with C0

A Sum

B Carry

Boolean expression for sum ( Σ ) and output of the half

adder is A B = A B +B A (ie) The two input XOR gate is

Half Adder

needed to produce the sum output. The two input AND is

needed to produce carry output. A.B.

The half adder circuit adds only the LSB column

(1s column ) in a binary addition problem.

19. What do you mean by combinational and sequential circuit?

A combinational circuit performs a specific operation which

is fully specified logically, by a set of Boolean functions.

Eg: Adders, Multiplexer, Encoder, Decoder , Demultiplexer etc

Sequential circuits include memory elements (binary cells)

in addition to logic gates. Their outputs are functions of the inputs

and the state of the memory elements, which is a function of the

previous inputs. As a result, the outputs of a sequential circuit

depend not only on the present inputs but also on the past inputs,

Eg: Flip flop, Registers, Counters etc.

20. Give the truth table for RS flip

flop.

INPUTS OUTPUTS

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Input Output

S R Q Q

1 0 1 0

0 0 1 0

0 1 0 1

0 0 0 1

1 1 0 0

21. What is a counter? Give its types.

Counter is a sequential logic circuit that counts the number

of incoming clock pulses. It consists of an array of flip fops

Counters do jobs like dividing frequency, addressing and serving

as memory units.

There are two types of counters.

(1) Parallel counter (or) synchronous counters

(2) Ripple counter (or) Asynchronous counters

22. What is a shift registers? What are the its different types?

Shift register is a register that shifts its contents within

itself without changing the order of the bits. It may be designed

to shift the data either to the left or to the right. The data is

shifted one bit at a time when a clock pulse is applied. The shift

register is used for temporary storage of data. It is used for

multiplication and division where bit-shifting is required. Here

the output of one flip flop is connected to the input of the

following flip-flop. Depending on the modes of loading and

reading data, there are FOUR types of shift registers.

1. Serial-in Serial-out

2. Serial-in Parallel-out

3. Parallel-in Serial-out

4. Parallel-in Parallel-out

23. Define Preset and Clear

When Power is switches on, the flip flop goes to random

state. So, presetting or clearing is required before applying

inputs. For such a purpose, preset PR and clear CLR terminals

are provided. Small bubbles shown at PR and CLR terminals

indicate that they are effective when they are low. A low PR

sets Q to „1‟. Similar a low CLR resets Q to „0‟. PR and CLR

cannot be made to low at the same time.

24. What do you mean by positive edge and negative edge

triggered flip flop ?

Positive edge triggered flip flops SET/RESET at the

positive (rising or leading) edge of the clock pulse depending

upon the state of the input signals. The SET/RESET state of

the output remains steady for one clock period and the clock

again samples the input signal on the next positive edge of the

clock.

Negative edge triggered flip flops SET/RESET at the

negative (falling or trailing) edge of the clock pulse. A small

circle known as bubble is placed before the arrow head to

show the negative edge triggering.

25. Define Microprocessor

A microprocessor is a computer processor that incorporates

the functions of a computer's central processing unit (CPU) on a

single integrated circuit (IC). It is also the brain of the system.

26. What are the components of microcomputer?

Arithmetic and Logical Unit, Timing and Control Unit,

Registers,

27. List the types of semiconductor memory?

Random Access Memory, Read Only Memory, EPROM,

EEPROM

28. List out the general and special purpose registers in 8085

Accumulator ,B,C,D,E,H and L

29. What is a bus? What are the different types of buses. Define

The group of lines used for connecting input/ output

devices and memories with the CPU is called bus.

Data Bus, Address Bus

Data Bus: 8 bits of data are transmitted to the

in parallel D0-D7

Address Bus: Transmit Address and Data at different moments

in a multiplexing technique AD0-AD15

30. Explain : INTR, IO/M‟ , HLDA, ALE

INTR : Interrupt request signal . It is sampled in the last state of

the last machine cycle

IO/M‟ : It is the status signal that distinguishes whether the

address is for memory or IO

HLDA: It is the signal for Hold Acknowledgement, that

indicates the HOLD request has been received

ALE : It is an Address Latch Enable that enables the lower 8

bits of the address to be latched either to IO or memory

31. What is Interrupt? Which has the highest priority?

The request signal that affects the normal sequence of

the program. TRAP has the highest priority

32. What are the different types of flags?

Carry Flag(C)

Auxilliary Carry Flag(AC)

Zero Flag (Z)

Parity Flag (P)

Sign Flag (S)

33. Give two examples for two byte instruction . Explain

MVI A,05 Moves the immediate data 05 to Acc

IN 08 Reads the port value 08 to Accumulator

34. Write down the five different types of instruction set.

Data Transfer group

Arithmetic group

Logical group

Branch group and

Stack , I/O and Machine Control group

35. Define Addressing mode

The instruction requires certain data on which it has to

operate have various techniques called Addressing

modes .

36. Write an ALP for 8-bit simple addition(without carry)

LXI H, 8850

MOV A,M

INX H

ADD M

STA 8852

37. What is PSW?

Program Status Word . 5 status flags and three

undefined bits is called PSW.

38. What is program counter?

The PC stores the address of the next instruction that is

going to be executed.It is a 16 bit register.

39. Define Stack Pointer?

Stores the address of the Stack Top . It is a 16 bit

register

40. What is PUSH and POP?

Inserting and Deleting an item to and from the stack.

PART – B

1. Convert the following binary numbers into their equivalent

decimal numbers

(10.110)2 = ( ) 10 (1.1110)2 = ( ) 10

1 0 . 1 1 0 1 . 1 1 1 0

0 x 2

-3= 0.00

0 x2-4

= 0.000

1 x 2

-2= 0.25

1 x2-3

= 0.125

1 x 2

-1= 0.50

1 x2-2

= 0.250

1 x2-1

= 0.500

0 x 2

0= 0.00

1 x 21= 2.00

1 x2

0=

1.000

2.75

1.875

(10.110)2 = ( 2.75) 10 (1.1110)2 = ( 1.875) 10

(11.10)2 = ( ) 10

1 1 . 1 0

0 x2-2

= 0.0

1 x2-1

= 0.5

1 x20= 1.0

1 x21= 2.0

3.5

(11.10)2 = ( 3.5) 10

2. Convert the following hexadecimal numbers into their

equivalent binary numbers

A4 1010 0100

A2B7 1010 0010 1011 0111

ABE2 1010 1011 1110 0010

12A3 0001 0010 1010 0011

3. Convert the following binary numbers into their equivalent

hexadecimal numbers

101010110 1 / 0101 / 0110 =1 5 6

101100010001 1011 / 0001 / 0001 = B11

11101010 1110 / 1010 = E A

11111 0110 1 / 1111 / 0110 = 1 F 6

4. Write about ‘NAND’ GATE: with truth table

A NAND gate has two or more inputs and only one output. The symbol shows the

standard 2 input NAND gate. The output is given by Y= BA. . The NAND operation can be

performed by the combination of AND gate and INVERTER. This function can also be

performed by the combination of inverter and one AND gate. As the inverter is frequently

used, it is represented by a small circle known as bubble.

The NAND gate has logical completeness. It means that any other logical operations can

be performed using only NAND gates. It is easier to fabricate NAND gates using IC technology.

NAND gates consumes less power. Hence, NAND gates are known as UNIVERSAL gate

because other basic gates (AND, OR, NOT) can be realized using NAND gates.

When both the inputs or any one of the input is 0, the output is 1 and when both the input

is 1, the output is 0.

Equivalent Circuit and its Symbol with Truth Table:

Explanation:

Case:1 If A=0 and B=0 then BA. = 0.0 = 0 =1

Case :2 If A=0 and B=1 then BA. = 1.0 = 0 =1

Case:3 If A=1 and B=0 then BA. = 0.1 = 0 =1

Case :4 If A=1 and B=1 then BA. = 1.1 = 1 = 0

5. What is EX-OR gate? Explain with truth table

EXCLUSIVE – OR gate:

The Exclusive-OR operation is same as OR operation with the exception that the output is

0 when both inputs A and B are 1. For all other cases, the outputs of EX-OR and OR are exactly

same. The symbol and the truth table are as follows. Here Exclusive means A. B +B . A

Case:1 If A=0 and B=0 then = BA = 00 = 0

Case :2 If A=0 and B=1 then = BA = 10 = 1

INPUT OUTPUT

A B Y= BA.

0 0 1

0 1 1

1 0 1

1 1 0

INPUT OUTPUT

A B Y= BA

0 0 0

0 1 1

1 0 1

1 1 0

Case:3 If A=1 and B=0 then = BA = 01 = 1

Case :4 If A=1 and B=1 then = BA = 11 = 0

An Ex-OR gate can be used for binary addition. The output of an Ex-OR gate is equal to

the sum of two binary bits. The carry can be obtained by using AND gates. The output of

an AND gate is equal to carry resulting from binary addition.

6. Write any 5 basic laws of Boolean Algebra

BOOLEAN POSTULATES:

Principles of AND Operation

1. 0.X=0

2. X.0=0

3. 1.X=X

4. X.1=X

Principles of OR Operation

5. X+0=X

6. 0+X=X

7. 1+X=1

8. X+1=1

Combining a variable with its complement

9. X.X=X

10. X. X =0

11. X+X=X

12. X+ X =1

Double complementation

13. X =X

Commutative Laws

Commutative laws states that the order of adding or multiplying is not important. In

other words, we get the same answer by adding X to Y as we do by adding Y to X. Similarly in

multiplication also X.Y=Y.X

14. X+Y=Y+X

15. X.Y=Y.X

Associative Laws:

The expression can be expanded by multiplying term as in ordinary algebra. The associative

laws states that we can group any two terms of a sum or any two factors of a product. In other

words, give X+Y+Z. we can first add X and Y, and then add the result to Z. In other words, we

can add Y and Z and then add the result to X.

16. X.(Y.Z)=(X.Y).Z=X.Y.Z

17. (X+Y)+Z=X+(Y+Z)=X+Y+Z

Distributive Laws:

18. X.(Y+Z)= X.Y+X.Z

19. X+Y.Z=(X+Y).(X+Z)

Absorption Laws:

20. X+XY=X

21. X(X+Y)=X

22. XY+XY =X

23. (X+Y)(X+ X )=X

24. X+ X Y=X+Y

25. XZ+Z X Y=ZX+ZY

26. (Z+X)(Z+ X +Y)=(Z+X)(Z+Y)

27. XY+ X Z+YZ=XY+ X Z

28. (X+Y)( X +Z)(Y+Z)=(X+Y)( X +Z)

29. XY+ X Z=(X+Z)( X +Y)

30. (X+Y)( X +Z)=XZ+ X Y

7. Show that (A+B+C)(A+B+ C )=A+B

= AA+AB+A C +BA+BB+BC +CA+CB+C C

=A+AB+ A C +BA +B+ B C +CA+CB

=A(1+B)+ A C +B(1+A)+ BC +CA+CB

=A+ A C +B+ B( C +C)+CA

=A(1+ C )+B+CA

=A+B+CA

=A(1+C)+B

=A+B

8. Show that X+ X Y = (X+ X )(X+Y)

Taking RHS

(X+ X )(X+Y)

=XX+XY+ X X+ X Y

=X+XY+ X Y

=X(1+Y)+ X Y

=X+ X Y

9. F(A,B,C,D)=∑(1,3,7,11,15) and the don’t care conditions are d(A,B,C,D) = ∑(0,2,5)

F(A,B,C,D) = CD+ A D+ A B

10. Explain and Rolling Map and Redundant Map

ROLLING MAP:

We can also roll and overlap to get the largest groups that can be found. For example

Here, an Octet is formed with 8 adjacent 1’s and a quad with 4 1’s is rolled.

CD

AB

C D C D CD C D

A B x 1 1 x

A B 0 x 1 0

AB 0 0 1 0

A B 0 0 1 0

C B D

REDUNDANT GROUPS:

After encircling groups, there is one more thing we should do before writing the simplified

Boolean equation ie eliminate any group whose 1s are completely overlapped by other groups.

C BD CD (we can omit due to repetition)

11. Explain Full Adder Circuit with neat diagram and truth table

FULL ADDER:

It is a combination of two half adders. It has got three inputs and two outputs. It can add

3 digits at a time. The bits A and B which are to be added come from the two registers and the

third input come from the carry generated by the previous addition.

CD

AB

C D C D CD C D

A B 1 1 0 0

A B 1 1 0 1

AB 1 1 0 1

A B 1 1 0 0

CD

AB

C D C D CD C D

A B 1 1 0 0

A B 1 1 1 0

AB 1 1 1 0

A B 1 1 0 0

A circuit called a full adder must be used for the 2s, 4s, 8s, 16s and higher places in

binary addition. The truth table shows all the possible combinations of A,B and Cin (carry in).

Full adders are used for all binary place values except the 1s place. It is used for an extra carry

input. It has three inputs Cin, A,B . It has got two outputs sum (Σ ) and carry (C0 ).

Full Adder circuit can be connected with 2 half adder circuits and an OR gate.

The expression for sum is Σ = A B C

The expression for carry is AB+BC+CA

The eight rows under the input variables, represent all the possible combinations of 1s and 0s.

The output variables are determined form the arithmetic sum of the input bits. When all input

bits are 0s, the output is 0. The S output is equal to 1 when only one input is equal to 1 or when

all three inputs are equal to 1. The C output is equal to1, if two or three inputs are equal to 1.

Explanation: Sum: S = A B +Ci

Carry C0 = (A B). Ci + A.B

= (A B + B A ) Ci + A.B

INPUTS OUTPUTS

A B C Sum Carry

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

= A B Ci + B A Ci + A.B

12. With neat diagram discuss encoder circuit

An encoder is considered to be a circuit which has multiple inputs and generates a particular

address as the output. If there is only one active input, it is easy to encode. If more than one

input is active at the same time, we have to establish some priorities and such a device is called

priority encoder. The priority is established according to the position of the input.

An encoder has 2n input lines and m output lines. The output lines generate the binary

code for the 2n input variables.

13. Explain Multiplexer in detail

A multiplexer is a circuit that has more number of inputs but only one output. A digital

multiplexer is a combinational circuit that selects binary information from one of the many input

lines and directs it to a single output line. The selection of a particular input line is controlled by

a set of selection (control) lines. In general, there are 2n input lines and n selection lines whose

bit combinations determine which input is to be selected.

Block Diagram m control signals

……..

n

input signals : 1 output signal

The multiplexer has n input signals, m control signals and 1 output signal. Each of the

four input lines I0,I1,I2 and I3 is applied to one input of an AND gate. Selection lines S1 and S0

are decoded to select a particular AND gate. The following function table lists the input-to-

output path for each possible bit combination of the selection lines.

Explanation: When S1=0 and S0=0 (ie) 10, the AND gate associated with input I2 has two of its

inputs equal to 1 and the third input connected to I2. The other three AND gates have at least one

input equal to 0, which makes their output equal to 0. The OR gate output is now equal to the

values of I2, thus providing a path from the selected input to the output. A multiplexer is also

called a data selector, since it selects one of the many inputs and steers the binary information to

the output line.

S1 S0

I0

inputs to 1 output (Y)

I3

Multiplexer

Multiplexer

(4 x 1)

Function Table for 4 x1 multiplexer

The AND gates and inverters in the multiplexer resemble a decoder circuit and indeed, they

decode the input selection lines. The 2n –to-1 line multiplexer is constructed form an n-to 2n

input line, one to each AND gate.

The output of the AND gates is applied to a single OR gate to provide the 1-line output.

The size of the multiplexer is determined by the number 2n of its input lines and the single

output line. It is often abbreviated as MUX.

14. Explain RS Clocked Flip flop with its truth table

THE CLOCKED RS FLIP FLOP:

It consists of a basic NOR flip flop and two AND gates When the clock pulse (CP) is

zero, the outputs of the two AND gates remain at 0 regardless of what the input values S and R

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

are. On the other hand, when the clock pulse goes to a 1, the input vales of S and R are allowed

to reach the basic flip flop. For example, when S=1, R=0 and CP=1, the set value (S=1) is

allowed to reach the basic flip flop. Similarly, the reset value (R=1) will reach the basic flip flop

when S=0; R=1 and CP=1. However, when both s=1 and R=1, the occurrence of a clock pulse

makes both the outpus of the flip flop may go to either a 1 or a 0. (ie) it cannot be predicted and

this state of the flip flop is called indeterminate. Which output state would result, depends upon

whether it is set or the reset input of the basic flip flop remains a 1 longer before the transition of

the clock pulse to 0.

Symbol: RS flip flop:

The symbol of clocked RS flip flop is shown. IT has got three inputs-S,R, and CP. The

CP input is marked by a small triangle. This triangle is a symbolic representation for a dynamic

indicator. It is meant to denote that the flip flop responds to an input clock transition from a low

level (binary 0) to a high level (binary 1) signal.

The truth table for the RS flip flop is shown.

In this table Q is the present value of the binary

state of the flip flop at a given time and the S and R

Input Output

S R Q Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 X

1 1 1 X

S Q

R Q

as usual give the possible values of the inputs and Q(t+1) represents the next state of the flip

flop after the occurrence of a clock pulse.

15. What is JK Flip Flop? Explain with its suitable diagram and truth table.

J-K flip flop:

The JK flip flop is the improved version of the RS flip flop. The indeterminate state of

the RS flip flop gets defined in JK type flip flop. The inputs J and K behave like the inputs S and

R to the SET and CLEAR the flip flop respectively. (ie) the input J sets the flip flop and the

input K resets the flip flop. When both the inputs J and K are applied simultaneously, the flip

flop switches to its complement state. (ie) Q=1, it switches to Q-0 and vice versa.

Symbol

This flip flop is very useful in counter circuits. It has two control signals J an K and the

function of the flip flop is determined by these signals when a clock pulse arrives,. When both J

and K are low, both the AND gates are disabled and there is no effect of the clock pulse and the

output remains what was before the arrival of the pulse. When J is a low and K is high, the

lower gate is disabled and the flip flop cannot be reset if Q is low. In this case if Q is high, as

J Q

K Q

soon as a clock pulse arrives the upper gate will pass a reset trigger forcing Q to become 0. Ie .

when J=0 and K=1 it will reset the counter, if nor already reset, on the arrival of a clock pulse.

When J is a high and K is a low, the upper gate will be disabled and flip flop cannot be

set if Q is low. In this case, if Q is high, as soon as a clock pulse arrives, the lower gate will

pass a set trigger and will force the output Q to be a 1. Thus J=1 and K=0 will set the flip flop.

When both J=1 and K=1(forbidden state in RS flip Flop), we can set or reset the flip flop

depending upon its present position. IF Q is low, the lower gate passes a set trigger on the

arrival of the next clock pulse and Q will be changed from Q=0 to Q=1. If Q is high, the upper

gate passes a reset signal on arrival of the next clock pulse will force Q from 1 to become a 0. Ie.

If it is 0 will become a 1 and if it is a 1 it will become a 0. ie the flip flop will toggle on the

occurrence of the next pulse. In either case, the output state of the flip flop is complemented.

Input Output

Q J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

16.

PART – C

1. Convert the following decimal numbers into their equivalent binary

numbers

a. Decimal number = 24 b. Decimal number = 237 c. Decimal number = 46

(72.2342)10

2. Convert the following Decimal numbers into their equivalent

hexadecimal numbers

Decimal number = 140 Decimal number = 26

2 24

12 -- 0

6 -- 0

3 -- 0

1 -- 1

0 -- 1

(24)10 = (11000)2

2 46

23 -- 0

11 -- 1

5 -- 1

2 -- 1

1 -- 0

(46)10 = (101110)2

2 237

118 -- 1

59 -- 0

29 -- 1

14 -- 1

7 -- 0

3 -- 1

1 -- 1

(237)10=(11101101)2

Integer part Decimal part

2 72

36 -- 0 0.2342 x 2 = 0.4684 0.4684 with a carry of 0

18 -- 0 0.4684 x 2 = 0.9368 0.9368 with a carry of 0

9 -- 0 0.9368 x 2 = 1.8736 0.8736 with a carry of 1

4 -- 1 0.8736 x 2 = 1.7472 0.7472 with a carry of 1

2 -- 0

1 -- 0

0 -- 1

(72.2342)10 = (1001000.0011)2

16 26

1 -- 10-A

0 -- 1

(26)10 = (1A)16

16 140

8 -- 12-C

0 -- 8

(140)10 = (8C)16

Decimal number = 729 Decimal number = 1272

3. Explain 9‟s and 10‟s complements with example

9’s complement: To form the 9‟s complement of decimal

number each digit of a decimal number is subtracted from 9.

the result so obtained is known as 9‟s complement of the

number.

16 729

45 -- 9

2 -- 13-D

0 -- 2

(729)10 = (2D9)16

16 1272

79 -- 8

4 -- 15-F

0 -- 4

(1272)10 = (4F8)16

Example : Give the 9’s complement of the following

1. 46 2. 462

10’s Complement: The 10‟s complement of a decimal number is equal

to the 9‟s complement of the number plus 1. 10‟s complement = 9‟s

complement +1

Example : Give the 10’s complement of the following:

1. 38

2. 346

9 9

- 4 6

5 3

9 9 9

- 4 6 2

5 3 7

9 9

- 3 8

6 1 9’s complement

+ 1

6 2 10’s complement

9 9 9

- 3 4 6

6 5 3 9’s complement

+ 1

6 5 4 10’s complement

4. Explain the conversion of Binary to Gray code with example on your own

Binary to Gray Conversion:

The first Gray digit is the same as the first binary digit. Add each pair of adjacent binary

bits to get the next Gray digit. The carries, if any are discarded.

This form of addition is formally called the mode-2 addition or exclusive OR addition.

The four rules for this kind of addition are

0+0=0

0+1=1

1+0=1

1+1=0

Example : 1 Covert binary number 1001 into its Gray code

Step:1 The first Gray digit is the same as the first binary digit.

1 0 0 1 Binary number

1 Gray code

Step:2 Add the first 2 bits of the binary number using the rules of mode-2 addition . The carry,

if any, is discarded.

1 0 0 1 Binary

1 1 1 Gray

Step : 3 Add the next two binary digits to get the next gray digit

1 0 0 1 Binary

1 1 0 1 Gray

Step 4: Add the last two binary digits to get the Gray digit.

1 0 0 1 Binary

1 1 0 1 Gray

Therefore 1101 is the gray code equivalent of the binary number 1001.

Example: 2 Convert binary number 1101 into its gray code

1

1

0 1 Binary

1 0 1 1 Gray

So the conversion of 1101 Binary to the Gray code is 1011

Example : 3 Convert binary number 10101110011 into its gray code

So, the conversion of 10101110011 binary to the Gray Code is 11111001010

1 0 1 0 1 1 1 0 0 1 1 Binary

1 1 1 1 1 0 0 1 0 1 0 Gray

5. Explain NOR as Universal Gate?

NOR gate as a Universal building block

NOR as INVERTER:

A NOT gate can be made out of a NOR gate by connecting all its inputs together.

If input A is 0, then the output of the NOR gate is AA. = 0.0 =1= A

If input A is 1, then the output of the NOR gate is AA. = 1.1 =0= A

NOR gate as OR gate:

NOR gate can be used to construct an OR gate. The output of the first NOR gate is

BA . The second NOR gate in turn complements the given input giving double complement ie

BA . The double complement of a quantity is the quantity itself. Therefore the output is A+B

which represents the output of the OR gate.

NOR

INPUT OUTPUT

A Y= A

0 1

1 0

INPUT OUTPUT

A B Y=A+B

0 0 0

0 1 1

1 0 1

1 1 1

as AND Gate:

Here, the first two NOR gates inverts the input variables as A and B . Then, the two

input NOR gate produces an output as A + B which gives the output of AND gate as A . B

=A.B

NAND Gate:

Here, the first two NOR gates inverts the input variables as A and B . Then, the two

input NOR gate produces an output as A + B , which gives the output of OR gate A . B =A.B,

again the output is sent as input to another NOR gate, thus producing the output as BA. which

represents the output of NAND gate.

The logic circuit and the truth table is given below.

INPUT OUTPUT

A B Y=A.B

0 0 0

0 1 0

1 0 0

1 1 1

INPUT OUTPUT

A B Y= BA.

0 0 1

0 1 1

1 0 1

1 1 0

6. State and prove Demorgan’s Theorem

Demorgan’s Theorem

1. ZYX = X .Y . Z

2. ZYX .. = X +Y + Z

Demorgan’ First theorem: Circuit implications

1. It states that ZYX = X .Y . Z

The left side of the above equation represents an OR gate followed by an inverter. Originally

called a NOT-OR gate, this combination of two gates is now referred to as a NOR gate and its

abbreviated logic symbol is shown.

The right side of Demorgan’s first theorem is X .Y . Z ; this represents an AND gate

whose inputs are inverted as shown.. An AND gate with inverted inputs is shown as bubble

AND gate.

LHS = RHS

Hence, Demorgan’s first theorem thus established with the equivalent of the NOR gate and

bubbled AND gate.

To prove ZYX = X .Y . Z

Case :1 X=0 Y=0 Z=0

Left Side 000 = 0 =1

Right Side .0 0 . 0 =1.1.1=1

Case:2 X=0 Y=0 Z=1

Left Side 100 = 1 = 0

Right Side .0 . 0 .1 = 1.1.0 =0

Case :3 X=0 Y=1 Z=0

Left Side 010 =1 =0

Right Side .0 .1 . 0 = 1.0.1=0

Case:4 X=0 Y=1 Z=1

Left Side 110 = 1 =0

Right Side .0 1 .1 = 1.0.0 = 0

Case:5 X=1 Y=0 Z=0

Left Side 001 = 1 =0

Right Side 1 . .0 .0 = 0.1.1 = 0

Case:6 X=1 Y=0 Z=1

Left Side 101 = 1 =0

Right Side 1 . .0 1= 0.1.0 = 0

Case :7 X=1 Y=1 Z=0

Left Side 011 = 1 =0

Right Side 1 .1 . .0 = 0.0.1 = 0

Case :8 X=1 Y=1 Z=1

Left Side 111 = 1 =0

Right Side 1 .1 .1 = 0.0.0 = 0

Demorgan’s Second Theorem states that

ZYX .. = X +Y + Z

The left side of the second theorem is shown. The NOT-AND gate combination is

referred to as NAND gate, for which the abbreviated logic symbol is shown .

The right side of the second theorem states that the inputs are inverted before reaching

the OR gate as shown. This combination is used so often that it has an abbreviated logic symbol

which is shown. Here the triangles are deleted and the bubbles are moved directly to the inputs,

This abbreviated logic symbol is also called a bubbled OR gate.

Demorgan’s theorem are useful in changing Boolean expressions to equivalent forms, To

apply Demorgan’s theorems, change the plus signs to multiplication signs or vice versa, and take

the complement of an individual term rather than that of the entire expressions.

Demorgan’s second theorem: ZYX .. = X +Y + Z

LHS=RHS

To change ZYX

Step:1 Change the plus sign to . sign to X.Y.Z

Step :2 Take the complement of each term to get X .Y . Z

ie. ZYX = X .Y . Z

We can prove the Demorgan’s theorem by means of truth table also. Let us prove the

second theorem by truth table method

To Prove ZYX .. = X +Y + Z

7. Simplify the following Boolean function into Sum of Products form

F(A,B,C,D) = ∑ (0,1,2,5,8,9,10)

F(A,B,C,D)=

B C + B D + B C D

INPUTS LHS RHS

X Y Z X.Y.Z ZYX .. X Y Z X +Y +

Z

0 0 0 0 1 1 1 1 1

0 0 1 0 1 1 1 0 1

0 1 0 0 1 1 0 1 1

0 1 1 0 1 1 0 0 1

1 0 0 0 1 0 1 1 1

1 0 1 0 1 0 1 0 1

1 1 0 0 1 0 0 1 1

1 1 1 1 0 0 0 0 0

CD

AB

C D C D CD C D

A B 1 1 0 1

A B 0 1 0 0

AB 0 0 0 0

A B 1 1 0 1

Product of Sums

F=AB+BC+CD

8. Discuss Demultiplexer in detail

De multiplexer means one into many. A De multiplexer is a logic circuit with one input and

many outputs. By applying control signals, we can steer the input signal to one of the output

lines..

Block Diagram

CD

AB

C D C D CD C D

A B 1 1 0 1

A B 0 1 0 0

AB 0 0 0 0

A B 1 1 0 1

m control signals

……..

1

input signal : m output signals

A de multiplexer is a circuit that receives information from a single line and transmits this

information to one or more possible output lines. The selection of a specific output line is

controlled by the bit values of n selection (control) lines. The number of selection lines is 2 for

a 1-4 De multiplexer , 3 for a 1-8 De multiplexer and so on.

Let us consider a demultiplexer which has two selection lines A and B and four output lines

D0, D1, D2 and D3 along with the one enable line E. The truth table is also given

A Selection Lines B

input D0 to D3

E output

Function Table for 1 x 4 De multiplexer

Enable Input Output

IN A B OUT0 OUT1 OUT2 OUT3

0 0 0 1 0 0 0

0 0 1 0 1 0 0

0 1 0 0 0 1 0

0 1 1 0 0 0 1

De multiplexer

DeMultiplexer

(1 x 4)

9. Explain Decoder in detail

DECODERS: A decoder is a combinational circuit that converts binary information from n

input lines to a maximum of 2n unique output lines

3 to 8 Decoder:

The 3 to 8 decoder circuit is shown in the figure. The three inputs are decoded into eight

outputs, each output representing one of the minters of the 3 input variables. The three inverters

provide the complements of the inputs, and each one of the eight AND gates generates one of

the minterms.

Circuit Diagram

Input Output

A2 A1 A0 Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z7

0 0 0 1 0 0 0 0 0 0 0

0 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

Explanation:

For example, when A2A1A0 = 111, only Z7 AND gate has all high inputs, therefore, only

the Z7 output is high. If A2A1A0 = 101, only Z5 AND gate has all high inputs, therefore, only the

Z5 output is high.

A decoder is a combinational circuit that converts binary information from n input lines to a

maximum of 2n

unique output lines. If the n-bit decoded information is not used or if there are

don’t care combinations , the decoder output will have less than 2n outputs.

The decoders represented here are called n-to-m line decoders, where m<=2n. The main

purpose is to generate the 2n minterms of n input variables. The name decoder is also used in

conjunction with some code converters such as a BCD to seven segment decoder.

10. Explain Ripple Counter with diagram

RIPPLE COUNTER

Counting in binary and decimal is illustrated in the figure. With four binary places

(D,C,B,A) . We can count from 0000 to 1111 ( 0 to 15 in decimal ) column A is the 1’s binary

place or LSD (least significant digit) The column D is the 8s binary place (or) MSD (Most

significant digit). A counter to count from 0000-1111, a device need 16 different states; a

modulo (mod-16) counter. Modulus of a counter is the number of different states the counter

must go through to complete its counting cycle.

A mod-16 counter using 4 JK flip flops is shown in the figure. Each JK flip flop is in its

toggle position ( J and K both at 1) .

Assume the outputs are cleared to 0000. As clock pulse 1 arrives at the clock (CLK)

input of flip flops 1 (FF1), it toggles and display shows 0001 ( on the negative edge – toggling).

Clock pulses 2 causes FF1 to toggle again, returning output Q to 0, which causes FF2 to toggle to

1. The count on the display no w reads 0010. The counting continues, with each flip flop

output triggering the next flip flop on its negative going pulse. Column A (1’c column ) must

change state on every count. This means that FF1 must toggle for each clock pulse. FF2 must

toggle only half as often as FF1, as in column B.

CLOCK OUTPUT

D C B A

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

16 0 0 0 0

The counting of the mod-16 counter is shown up to a count of decimal 10 (binary 1010)

by waveforms. The CLK input is shown on the top line. The state of each flip flop

FF1,FF2,FF3,FF4 is represented on the waveforms. The binary count is shown across the

bottom of the diagram. Vertical line shows that the clock triggers only FF1. FF1 triggers FF2;

FF2 triggers FF3 and so on. Because one flip flop affects the next one, it takes some time to

toggle all the flip flops. For instance, at point ‘a’ on pulse 8, notice that the clock triggers FF1,

causing it to go to ‘0’. In turn FF2 to 1 to 0; in turn FF3 to 1 to 0., in turn FF3 reaches 0 it

triggers FF4, which toggles from 0 to 1.

The changing of states is a chain reaction that ripples through the counter. Hence this

counter is called as RIPPLE COUNTER.

11. Explain any one type of Shift register with neat diagram and truth

table

Serial in Serial Out Shift Register:

Here, D flip is used to shift the serial data from one flip flop to the another flip flop . FF0

is the first flip flop and the serial input fed is shifts to the second flip flop FF! though Q0 , and

from Q1 to FF2 , and from Q2 to FF3 and so on. Clock has been sent simultaneously to all the

four flip flops.

Parallel Load Shift Registers

The inputs for parallel loading of 4 bits are QA,QB,QC,QD. This system also incorporates

a re circulating feature that puts the output data back into the input so that it is not lost. This shift

registers uses 4 – D flip flops. At first all the flip flops are put to 0 through a CLR signal. When

the inputs given to QA,QB,QC,QD are 0000, then the output will 0000 in parallel output section

denoted by PA PB PC PD as shown in the diagram. If the input to QA,QB,QC,QD are 0101 then

the output PA PB PC PD will be 0101.(ie) the parallel output is the replica of the parallel input .

CONCLUSION:

Thus, we have learnt RS, JK flip flop and the pulse triggering of positive and negative

edge with the PRESET and CLEAR inputs. Also, we have learnt the shift registers to shift the

data from one flip flop to another flip flop in serial and parallel form. We have learnt

synchronous and Asynchronous from of counters to count the pulses in octal and decimal form