pebs electronics - epfl

5 Feb 2007 Waclaw Karpinski 1

PEBS Electronics

W. KarpinskiI. Physikalisches Institut

Aachen, 10 January 2007


Outline

An overview of the PEBS Electronics

Subdetector Readout:

- TRD

- Tracker

- ECAL

- ToF

- TGB (Trigger Box)

Summary


PEBS Electronics


AMS Electronics

M.Capell Jan 04GlobalPower 120V

Detector ADCMUX

DataReduction

(H)V Detect. Vdd(Digital)

Subd. Power

28 V

Digitization& HoldSample

DC-DC Converters(28 -> 5,3.3,+-2)

(High Efficiency) 28V Filter (I/O)

CustomASIC

LinReg

Vdd (Analog)

DSP

Memories

Gate

Slave M&C

GA

DSP

Mem

Trigger

LRS

AMSWireMAINDATA

HRDL

LRDL

2x CAN

Array

CDDC Command Distrib, Data Collect.

Am

sW

Global DAQSubdetector DAQ

CDDC

Am

sW

Gate BusySequence

Trigger Input

Comp

PartDigital

CDP: Common


• 16 layers, 7 chambers/layer =112 chambers

• 16 “straw tubes” per chamber• 1792 channels in total• the readout schema could be the same

as in AMS2• the available spare boards can be used

in PEBS-TRD readout

PEBS -TRD


AMS2-TRD Readout

UFE = front endUTE = tube endUHVD = high voltage distribution

UPSFE = power supply for UFEUDR = data reduction boardJINF = interface board for higher DAQ UHVG = high voltage generator


U-Crate UPD

AMS2-TRD Readout

UDR2 UPSFE JINF UHVG

not a

vaila

ble

for P

EBS


Front-End Electronics : UFE

VA 1

VA 2

12 bit ADCAD7476

Hybrid Control Circuit & Logic Unit

DC shift VΣ

SSBH

HB

+2.0 A -2.0 A

GND +2.0 D -2.0 D

ESD-ProtectionIC and Network

Ch 1 - 32

Ch 33 - 64

Airborn ConnectorsMA231-032-125-5000

Dreset1, Dreset6, ShiN1, ShiN2, CLK_FF, Dreset5, hold, hold_b, test_on

CAL

+2.0 A-2.0 A

+-

-+SDATA+

SDATA-

SCLK+

SCLK-

+2.0 D

-2.0 D

+2.0 D-2.0 D

Micro D-SubConnector 21 pol.Schematic Diagram of UFE

65.8mm

118m

m


Data Reduction UDR2

Ho

t S

ide

Gate ArrayDSP

Analog::DigitalIsolation Barrier

7x 64x IN

OUT

Co

ld S

ide

Digitized Data

Performs:• buffering of the raw data• data reduction in the DSP• data transmission to the Global DAQ


Equipment needed:

28x UFE, 4x UDR, 2x UPSF, 4xUHVD, 1x C&DI

TRD Power Consumption = UFE(7W) + Ucrate(13W) + UPD(11W) =31W

Structure of the PEBS -TRD Readout


PEBS -TRD CRATE

UDR -data reduction boardUPSFE -power supply for UFEC&DI - interface for higer DAQUHVD - high voltage generator


PEBS -Tracker

• 4 disks á 46 modules = 184 Modules • readout using SiPMSiPM arrays with 32 strips• 4 SiPM arrays on each module end

⇒ two Front End Hybrids/module á 128 channels• in total 47104 channels

arrangement of the SiPMSiPM arraysarrays on the module end

SiPM array with 16 channels


•• SiPMSiPM specifications- channel size: 1 mm x 0.25 mm- pixel size: 0.043 x 0.043 mm2

= 135 pixels/channel ⇒ 8 bit ADC- operating voltage: ~ 40V- gain = 0.8 x 106 ⇒ preamplifier with large dynamic range necessary- SiPM gain varies with bias voltage: 40% / 1V

Do we need gain adjustment for individual channels ?If yes, it must be implemented on chip level (DAC)⇒ new chip design necessary

⇒ significant increase of cost and development time- dark current =500 nA/channel- dark count ~ .5 MHz (40V, T=22°C)

⇒ fast shaping time required to reduce pile up⇒ ac coupling between detector and preamplifier

or active leakage current compensation on the chip

PEBS -Tracker


SiPM- Behaviour

Temperature depandance from Nakamura (KOBE)(7th ACFA workshop on Physics and Detector at the Linear Collider)

• gain shift by 1.5% /°C• gain variations with bias voltage by 80%/1V• increase of noise rate by factor of 70%/10°C

⇒ the operation temperature of SiPM should be well controlled⇒the operation temperature should be low⇒ precise voltage control for good gain stability


ROCs possibly adequate for SiPM signal processing


MAROC : 64 ch MAPMT chip for ATLAS lumi

• Characteristics64 PMT channels input (50-100 Ω)Variable gain current conveyor (0-2)

6 bits : 2, 1, 1/2, 1/4, 1/8, 1/1664 discriminator outputs (GTL)100% sensitivity to 1/3 photoelectron(50fC). Counting rate up to 2 MHzCommon threshold loaded by internal 10bit DAC1 multiplexed charge output with variable shaping 20-200ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pC)Crosstalk < 1%

• Technology : AMS SiGe 0.35µmSubmitted 13 june 05 Area 12 mm2

Dissipation 130 mW @ VDD=3.5V

Synoptic diagramm of MAROC1

Hold signal

Variable

GainPream

p.

VariableSlow

Shaper

S&H

BipolarFast Shaper

64 Triggeroutputs

Gain correction6 bits/channel

discriminatorthreshold

10 bits DAC

Multiplexedcharge output

64 PMinputs

10 bit DAC

©N. Seguin (LAL)


ILC SiPM Chip

• 18-channel 8-bit DAC (0-5V)• 18-channel front-end readout :

Variable gain charge preamplifier (0.67 to 10 V/pC)

Variable shaping time CRRC2 shaper (12 to 180 ns)

• Track and hold 1 multiplexed output• Power consumption : ~200mW (supply : 0-5V)• Technology : AMS 0.8 µm CMOS• Chip area : ~10mm²• Package : QFP-100


Channel architecture for SiPM readout

100nF

10pF

Charge Preamplifier :Low noise : 1300e- @40ns

Variable gain :

4bits : 0.67 to 10 V/pC

CR-RC² Shaper :Variable time constant : 4 bits (12 to 180ns)

12ns photoelectron measurement (calibration mode)180ns Mip measurement (physics mode)

compatibility with ECAL read-out

12kΩ

4kΩ 24pF

12pF

3pF

in

8pF 4pF 2pF 1pF

40kΩ

8-bit

DAC

0-5V

ASIC

Rin =

10kΩ50Ω

100MΩ2.4pF

1.2pF

0.6pF

0.3pF

0.1pF

0.2pF

0.4pF

0.8pF

6pF


Prospective for A-HCAL SiPM Chip

• Similar developments for AHCALChip fully dedicated to SiPMsInternal DAC for SiPM gain adjustment (5V range)Auto-trigger (fast shaper + Discriminator)Internal TDC, 1 ns stepInternal 12 bit ADCPower pulsing

T&Hx1

Variable gain Preamplifier

DiscriTDC

12-bit ADC

8 bit DAC (0-5V)

in

Fast Shaper

Shaper tp~30-40ns

Auto-trigger

12-bit DACThreshold

Capacitance for AC

coupling

…

Analogue Memory

Charge Ouput

Time Ouput


PEBS-Tracker Readout

• FE Hybrid consists of:- biasing network - 2 VA64 chips- 1 amplifier- readout control- expected power consumption2 mW / channel

- readout time ~85 µs/event

FE-Hybrid Ver.2


Tracker Front-End Hybrid

SiPMs Arrays

Biasing & AC coupling

VA64-chip


Data Reduction TDR2 Boards

+80V

Gate

A

rray

DS

P

2x A

DC

AD

C

An

alo

g::D

igita

lIso

latio

n B

arrie

r

640x IN

384x IN

OU

T

TDR2Analog

Receivers Data ReductionData Compresion

• The readout of PEBS-Tracker can be realized using modified TRD2boards from AMS

• Architecture- on FE-Hybrid analog signalprocessing only

- TRD2 performs digitizationcalibration and data reduction for 2048 channels

• 6 analogue inputs and 6 ADCs per board


PEBS-Tracker Readout • 16 FE-Hybrids á 128 channels connected to 1 TDR =2048 channels/TDR• 368 FEHs, 23 TDRs and 2 crates á 12 TRDs necessary for Tracker readout

Power consumption: 85W on FEHs +94W in TDRs +47W in PSs = 226W


PEBS-Tracker Crate

TDR -data reduction boardTPSFE -power supply for Front EndC&DI - interface for higer DAQTBIAS - bias voltage generator


PEBS ECAL Electronics

• 80 Layers, 95 modules/layer• Two modules will be readout by one SiPM ⇒ 3800 channels in total• Readout using SiPMs with the size 3mm x 3mm, ~8100 pixels / SiPM• The same readout architecture as for the PEBS-Tracker• Could be the same ASIC (VA64-SiPM)

SiPM

3 mm

3 mm


PEBS ECAL Electronics• Front-End Board with 6 VA64-SiPM chips • One board collects the signals from one side of 2 super layers = 384 channels• 5 Front-End Boards controlled by 1 modified TRD board = 1920 channels/TDR

Power consumption: 7 W on FEHs +8 W in TDRs + 4 W in PSs = 19 W


PEBS-ECAL Crate

EPSFE -power supply for Front EndEBIAS - bias voltage generatorTDR -data reduction boardC&DI - interface for higer DAQ


Scintillator Electronics• 4 ToF planes á 8 scintillator paddles• 32 scintillators in total with

- (4 SiPMs ) per end ⇒ 256 channels or

- one PM per end ⇒ 64 PMs in total

Provides:Provides:

• fast (~30ns) coincidence between at least 3 out of 4 ToF planes to select particles within the main PEBS acceptance

• measurement of the particle velocity including the direction of the particle, (resolution of 100ps)

• measurement of the absolute charge of particles

• rejection of protons with E<1GeV at the trigger level


PM vs SiPM

High Voltage (2000V)

Influenced by magnetic fields

Influenced by vibrations

Fragile and heavy

Low noise

Good temperature stability

Better gain stability

Low voltage (30V-60V)

Tested up to 4 Tesla

Not influenced by vibrations

Light and robust

High noise

Sensitive to temperature variation

Gain sensitive to voltage variation


TOF Readout in AMS2 for 24 PMTs (20 ToF and 4 ACC ) consists of:- SDR2SDR2: data collection and reduction & slow control - 4 x SFET24 x SFET2: charge and time measurement of TOF anodes (5 PMs/ board)- SFEA2SFEA2: charge and time of ACC- SFECSFEC: dynode charge - SPT2SPT2: pre-trigger unitfast trigger input

- TSPDTSPD: DC/DC converters- SHVSHV: high voltage box

AMS2 Scintillator Electronics


PM-PEBS Scintillator Electronics

TOF Readout in PEBS for 64 PMTs will consist of three crates:

- 1 x1 x SDR2SDR2: data collection and reduction & slow control

- 5 x SFET25 x SFET2: charge and time measurement TOF anodes (5 PMs/ board)

- 1 x1 x SPT2SPT2: pre-trigger unit, fast trigger input - 3 x3 x SHV boxes:SHV boxes: high voltage generator- 3 x3 x TSPDTSPD: DC/DC converters

SHV-Box

TSPD


Potential ROCs for ToF with SiPms


OPERA_ROC (2002)32 channelsVariable gain preampAutotrigger on ¼ p.e.BiCMOS 0.8µ3 000 chips

64 ch front-end board (BERN)

(S. Blin, T. Caceres, CdLT, G. Martin, L. Raux)

• Readout ASIC for multi-anodePhotomultiplier (Hamamatsu)

ASIC production for OPERA target tracker


MAROC : 64 ch MAPMT chip for ATLAS lumi

• Characteristics64 PMT channels input (50-100 Ω)Variable gain current conveyor (0-2)

6 bits : 2, 1, 1/2, 1/4, 1/8, 1/1664 discriminator outputs (GTL)100% sensitivity to 1/3 photoelectron(50fC). Counting rate up to 2 MHzCommon threshold loaded by internal 10bit DAC1 multiplexed charge output with variable shaping 20-200ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pC)Crosstalk < 1%

• Technology : AMS SiGe 0.35µmSubmitted 13 june 05 Area 12 mm2

Dissipation 130 mW @ VDD=3.5V

Synoptic diagramm of MAROC1

Hold signal

Variable

GainPream

p.

VariableSlow

Shaper

S&H

BipolarFast Shaper

64 Triggeroutputs

Gain correction6 bits/channel

discriminatorthreshold

10 bits DAC

Multiplexedcharge output

64 PMinputs

10 bit DAC

©N. Seguin (LAL)


Next version – MAROC2

Hold signal

Photomultiplier64 channels

Photons

Variable Gain

Preamp.

VariableSlow Shaper

20-100 ns

S&H

BipolarFast Shaper

Unipolar Fast Shaper

Gain correction64*6bits

3 discri thresholds (3*12 bits)

MultiplexedAnalog charge output

LUCID

S&H

3 DACs12 bits

80 MHz encoder

64 Wilkinson 12 bit ADC

64 trigger outputs

MultiplexedDigital charge output 64 inputs

• Substrate separation • Unipolar fast shaper • 3 discriminators• 80MHz encoding • 12bits Wilkinson ADC

New features:


SPIROC for AHCAL SiPM

• Si PM Integrated Read Out Chip (Mar 07)Chip fully dedicated to SiPMs developped after ECAL chipInternal DAC for SiPM gain adjustment (5V range)Auto-trigger (fast shaper + Discriminator)Internal TDC, 1 ns stepInternal 12 bit ADCPower pulsing

T&Hx1

Variable gain Preamplifier

DiscriTDC

12-bit ADC

8 bit DAC (0-5V)

in

Fast Shaper

Shaper tp~30-40ns

Auto-trigger

12-bit DACThreshold

Capacitance for AC

coupling

…

Analogue Memory

Charge Ouput

Time Ouput


SiPM-PEBS-TOF Crate

C&DI - interface for higer DAQSDR - data reduction boardSFE - charge and time measurementSPT - pre-triggerSPSFE - voltage supply for Front EndSBIAS - bias generator for SIPM


PEBS Trigger Electronics

•generates Fast Trigger: 50-70 ns after the hit based on a coincidence between at least 3 out of 4 ToF planes

•evaluates signals from ToF and ECAL• if any of predeterminated patterns of these signals occurs generates Level-1 trigger 1µs after the hit

•starts digitization and data flow for all subdetectors•controls the BUSY signal to ensure that the event is collected from the complete detector


PEBS-Trigger Crate

TLV1 - level 1 triggerTTBX - fast trigger, fast in/out and logicJINJ - intermediate DAQ, 1CDDC,

24 links to sleeves4 links to masters


Summary


Summary

Power Consumption (ToF readout with PMs)

Subsystem Channels Power FE [W]

Power DAQ [W]

Power PS [W]

Power Total [W]

TRD 1792 7 13 11 31

Tracker 47104 94 94 47 236

ECAL 3800 8 8 4 19

TOF 64 11 68 32 112

Trigger 5

Slow Control 2 1 3

Main DAQ 45

PDS 60

Contingency 100

∑≈ 610


Summary• TRD Readout boards used in AMS02 can be utilized without any

changes for PEBS-TRD readout

• For Tracker and ECAL Front End new developments are necessary:investigation of adequate readout chip Front-End Hybridsmodifications of voltage supply boards for front endnew design of bias voltage generator boardsnew backplanes

• Readout Architecture of TRD2 boards can be applied in PEBS Tracker and ECAL but the design of the readout boards must be slightly modified to much the detector granularity

• Two version of TOF electronics possible:readout using PMs; AMS2 TOF electronics can be easily adapted to

PEBS needsreadout using SiPMs; new designs necessary


• Expected total power dissipation amounts to ~ 600 W, including 100 W contingency

• Interfaces for power and interface for data transfer to Earth must be investigated

Summary

pebs electronics - epfl

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