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Performance Analysis of Interconnect Drivers forUltralow Power Applications

S.D.Pable, Mohd. HasanDepartment of Electronics Engineering

Zakir Husain College of Engg. and TechnologyAligarh Muslim University, Aligarh, U.P., India

Abstract—ultralow power consumption requirement of lowthroughput applications needs to operate circuits insubthreshold region where subthreshold leakage current is usedas active current for necessary computations. This paperinvestigates the impact of interconnect drivers on digital circuitperformance in subthreshold region. In particular, we haveinvestigates the performance of Si-MOSFET and CNFETs at32nm deep submicron technology node. Performance Analysisis carried out for different interconnect drivers driving globalinterconnect. We have proposed an optimized CNFET driverwhich gives the significant improvement in delay and PDP overconventional CNFET in subthreshold for global and semi-globalinterconnect length. HSPICE device model files generated from“Nano CMOS” tool are use for Si-MOSFET to analyze theimpact of Process and Temperature (P, T) variations onrobustness of circuit for fair comparison with CNFET.Variability of design metric parameters is evaluated by applyingGaussian distribution using Monte Carlo simulation run.

Index Terms— Subthreshold, Ultra-low power, CNFET, Monte-Carlo analysis.

I INTRODUCTION

Minimizing power consumption is a challengingtask to the researchers for designing digital circuits with ultralow power (ULP) digital portable applications. Due toaggressive scaling of transistor size according to Moore’slaw, gate leakage, drain substrate junction band to bandtunneling current and subthreshold current increasessignificantly in super threshold, limiting further scaling downof devices for ULP applications. Recently, subthresholdoperating region is of very much interest to reduce the energyup to the ultralow levels. Subthreshold operation of transistorcan have order of magnitude power saving over superthreshold circuits [1]. In subthreshold operating regionleakage current is used as drive current. This small leakagecurrent, however limits the maximum performance at whichthe subthreshold circuit can be operated. Since supply voltage(VDD) is less than threshold voltage (Vth), delay increasesexponentially [1]. Subthreshold circuits operation uses lowVDD to minimize the energy consumed by digital circuits andhas thus become popular option for research in ULP.

As CMOS process scales into the deep submicronregion, lithography limitation, electro migration and delayof copper interconnect has driven the need to find alternativeinterconnect solution [2]. In order to overcome

these limitations, the use of the bundles of metallic carbonnanotubes (CNT) as interconnect has been proposed as apossible replacement for Cu interconnect [3][4].Electromigration is negligible in Cu interconnect withsubtheshold circuits because of low current density but higherresistance of driver degrades interconnects performances.With reported current density of around 109 A/cm2, CNThave larger current carrying capabilities than traditional Cuinterconnect of the order of 103 A/cm2. For Nanotube basedinterconnects previous research primarily focused on impactof RLC on power dissipation and delay [5][6]. In this workequivalent RLC parameters of the interconnect line areextracted from PTM [7] tool for Cu. The equivalent RLCparameters of CNT interconnect are extracted using CarbonNanotube Interconnect Analyser (CNIA) [8] withinterconnect geometry suggested in [9].

Performance analysis of different interconnectdrivers is carried out for CNT and copper wire interconnectfor different semi-global and global interconnect lengths.For fair comparison between MOSFET and Carbon NanoTube Field Effect Transistors (CNFET) drivers same Vth isselected. For simulation purpose, we have used PTM modelparameter of Si-MOSFET at 32nm technology node [7]. Highperformance Stanford CNFET device model files whichsuccessfully accounts for CNFET practical non-idealities,such as scattering, effects of the source/drain extensionregion, and inter-CNT charge screening effects [6] are usedfor CNFET simulation.

The rest of the paper is organized as follows. Insection II, basic structure of CNFET is explores. In sectionIII, CMOS and CNFET device performance analysis carriedout to obtain optimal parameter for CNFET to achieve higherdrive current. Section IV compares the interconnect driversperformances for Cu and CNT interconnects. In section V,variability analysis of CMOS and CNFET basedinterconnects resource is carried out using sufficient MonteCarlo simulation run and Section VI draws the conclusionfrom this paper.

II BASIC STRUCTURE OF CNFET

CNFETs is one of the most promising devices amongemerging technologies. Most of the fundamental limitationsfor traditional MOSFETs are mitigated in CNFETs. Researchcommunity actively investigates CNFET as promising devicefor integrated circuit technology at the end or beyond theITRS roadmap [2]. The CNFET offers many potential

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Figure 1. Basic structure of CNFET

\ with (19, 0). CNFETs show 13×CV/I improvement over NMOS in superthreshold region at 32nmtechnology node due to near ballistic CNT transport [6].Theseadvantage leads us to investigate the CNFET performancein subthreshold region also.

The single wall carbon nanotubes (SWCNTs) is onedimensional conductor obtained by sheets of grapheme rolledin the forms of tubes, depending on the chirality’s, the singlewalled CNTs can be either metallic or semi conducting[10][11]. CNFET is obtained by replacing the channel of aconventional MOSFET by a number of carbon nanotubes,as shown in Fig. 1. As shown in Fig. 1 CNTs are placed onthe bulk substrate (k2), a high (k1) dielectric separates theCNTs from metal gate electrode by an insulator thicknessTox=4nm with dielectric constant of 16. The diameter ofCNT is given by the (1),

π

2nmn2maCNTD

(1)

Where (m, n) are chirality number of CNT, ‘a’ is Latticeconstant (a=2.49e-10). SWCNTs can be grouped as either

metallic nanotubes if m-n is an integer multiple of 3 orsemiconducting nanotubes if m-n is not an integer

multiple of 3Threshold voltage of CNFET given by (2) [12],

CNTTH D

aVV 33

(2)

Where q 3.03V is the carbon PI-PI bond energy..In this work, chirality numbers (m, n)= 13,0 is used for 1nmCNT diameter which gives Vth near to Vth of MOSFET at32nm technology node. Drive current in CNFET is functionnumber of CNTs per device (n), device transconductancegCNFET, VDD, Chirality vectors and hence CNT diameter andvoltage drop across the doped CNT source region (VSS).gCNFET, decreases with increasing the inter CNT pitch whereas Vth is constant for given diameter. Delay of CNFET givenby, [13].

n,CNFET

DDn CNFET, nCNFET,

Iα

VCT (3)

advantages with respect to MOSFET due to improvement inCV/I of intrinsic CNFET

The switching energy of CNFET is proportional tocapacitance of CNFET and given by, [13]

nCNFET,Energy nCNFET,C 2DDV (4)Where, nCNFET,C is capacitance of CNFET gate and isapproximately equal to its gate capacitance (CCNFET,n).

Gate capacitance of CNFET with n number of tubes isgiven by is given by,

CNT g,

parasitic-g

CNT g, g WCLCC n.

-CNT1n CNFET, (5)Where, Wg, CNT is width of CNFET and Lg, CNT is the length ofthe gate. Cg-CNT1 is almost constant for n. [13].

Total gate capacitance is proportion to number of CNTs inchannel, length of channel and pitch. It is necessary to useoptimum value of number of tubes and pitch to increase thedrive current as well as to keep the capacitance withinacceptable limit.

III.CMOS AND CNFET INVERTER ANALYSIS INSUBTHRESHOLD REGION

A. Subthreshold leakage CurrentFor very long wire, interconnect delay would be so

long that it can be dominate the gate delay. In ICs, a globalwire tends to be very long since they must be distributed allover the chip. These wires are associated with clocks, busses,and other major signals in the design. Since delay for longwire is quadratic with respect to interconnect length (L), thestandard solution is to insert repeaters or buffer periodicallyalong the wire. As drive current in subthreshold circuit isleakage current due to diffusion, therefore delay penalty isvery high which degrades the circuit performance insubthreshold regime. To overcome this problems driver withbetter delay response needed to be design.Unlike conventional CMOS in which the drain current IDS isdominated by transport of carrier due to drift, diffusioncurrent dominates in subthreshold operation. Transistors areoperated in subthreshold region by keeping VDD less thanthe Vth and leakage current flowing through the device isused as drive current for ultra low power applications.Subthreshold current is exponentially dependant on gate tosource voltage (VGS) because channel of transistor is notinverted. Subthreshold current is given by (5),

)e-(1eI=I T

DS

T

DSthGSV

-VnV

)V +V-(V

0D

(5)

Where I0 is the drain current when VGS=0V[14].

2Tox00 V)1n(

LWCI (6)

Where Vth is transistor threshold voltage, n is subthresholdslop factor (n=1+Cd/Cox), VT is the thermal voltage, η isDIBL coefficient.

B. CNFET optimisation for subthreshold regionSince subthreshold leakage current in Si-MOSFET isexponential function of supply voltage resistance of device

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also increases exponentially in subthreshold region. Insubthreshold domain this increase in resistance dominatesthe interconnect resistance as shown in Fig.2.Therefore it isnecessary to examine the scope of alternative device insubthreshold interconnect resources applications. In thissection we compared the performance of CNFET asinterconnect driver with Si-MOSFET in subthreshold regionfor global interconnect length from 200ìm to 1000ìm and forsemi-global interconnect length ranging from 100ìm to 500ìmwith Cu and MWCNT as interconnects.

Since device technology parameters designed forsuperthreshold region may not give the optimumperformance in subthreshold region. Hence it is necessaryto evaluate the performance of CNFET for different deviceparameters in subthreshold region to optimize these deviceparameters for better performance. Fig. 3 shows Ids asfunction of VDD at various gate oxide thicknesses. It is foundthat current increases exponentially up to 200mV and thensaturated, at TOX=2nm drive current shows 36% improvementover TOX=4nm due higher gate control over channel. Fig. 4shows I-V characteristics of CNFET at various inter CNTpitch and it is observe that varying pitch above 20nm doesnot show any significant advantage in Ids. Analysis fromFig. 3 is verified by measuring delay of FO4 at TOX=2nmand TOX=4nm, pitch=20nm as shown in Fig.5.

Figure 2. Driver resistance and interconnect resistance as function ofsupply voltage and interconnect length respectively

Figure 3. Drive current as function of supply voltage

Figure 4. Drive current as function of supply voltage for various CNTpitch

Figure 6. Drive current as a function of supply voltage

A delay improvement of 67.5% is seen for TOX=2. Sinceas TOX reduces the charge distribution become tighter andthe charge tends to accumulate just over the CNT channel,increasing drive current [15]. Conventional N-CNFET keyparameters are Tox=4nm, Kox=16, pitch=20nm, [12].

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Figure 8. PDP as function of supply voltage

To optimize CNFET (Opt-.CNFET) the selectedparameters are Tox=2nm from Fig. 3, pitch=20nm, numberof CNT tubes=10. Fig.6 shows I-V characteristicscomparison for NMOS, conventional NCNFET andOpt.CNFET. From simulated graph it is seen that Opt.NCNFET device is having better I-V characteristics overConventional NCNFET and NMOS device. For noise margincomparison between CNFET and CMOS device we havesimulate the device for voltage transfer characteristics. Fig.7 shows voltage transfer characteristics (VTC) of minimumsize Si-MOSFET and CNFET. For CNFET VTC curve issymmetric and switching threshold is at VDD/2 (200mv) and173mV for SI-MOSFET which degrades the SNM of Si-MOSFET in subthreshold. CNFET is having steeper curvesin transition region. This contributes to improvement in SNMover Si-MOSFET.

To evaluate the performance comparisons betweenCMOS, CNFET and Opt. CNFET devices at circuit level,FO4 is use as a test bench for design metric comparison.Fig. 8 shows the Power Delay Product (PDP) as function ofVDD. From Fig. 8 it is clear that Opt. CNFET showsimprovement in PDP over conventional CNFET and CMOSdue to improvement in delay.

IV.PERFORMANCE ANALYSIS OF INTERCONNECTDRIVERS FOR CU AND CNT

In any circuit or chip, the individual gates need tobe connected. While it is possible to use metals as inconventional circuits to make interconnects, the use ofmetallic carbon nanotubes would be much more desirabledue to better electrical properties. The ballistic transport ofthe metallic nanotubes provides significantly lower resistancein interconnect as compared to Cu. Fig. 9 show the test benchused for interconnect simulation with FO4 load .Theinterconnect considered for simulation is global and semi-global Cu and CNT. Fig. 10 and Fig.11 shows the delay andPDP performances of CMOS, CNFET and opt. CNFET baseddrivers for global Cu interconnect; similarly Fig. 12 and Fig.13 shows performances for MWCNT global interconnectlength from 200µm to 1000µm.

Figure 11. PDP as function of global Cu interconnect length

Figure 12. Delay as function of global MWCNT interconnects length.

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Figure 13. PDP as function of global MWCNT interconnect length

Figure 14. Delay and PDP as function of semi global Cu-interconnectlength

Figure 15. Delay and PDP as function of semi global MWCNTinterconnect length

It is observed from these figures that CNFET baseddriver shows the 42% and 46% improvement in delay andPDP over Si-MOSFET based drivers at 1000µm interconnectlength. Optimizing the CNFET parameters shows 52% and63% performance improvement in delay and PDP over theSI-MOSFET based interconnect resource.

It is also observed from Fig.10 to Fig. 15 that,replacing the Cu interconnect by MWCNT interconnect doesnot provide any significant advantage in delay as well asPDP due to higher driver resistance of Si-MOSFET insubthreshold region as shown in Fig.2.

Fig. 14 and Fig. 15 shows the delay and PDPperformances of semi-global interconnect of length 100 µmto 500 µm. CNFET and Opt.CNFET drivers shows significantimprovement in delay and PDP over Si-MOSFET basedinterconnect drivers.

V.VARIABILITY ANALYSIS

Random variation in process parameters, VDD andtemperature (PVT) are posing a major design challenges forsubthreshold circuit design. It is important to investigate theperformance variability for the optimal device. There are avariety of device parameter variations and imperfectioncaused by today’s CNT synthesis/fabrication technique,(1)CNT diameter and chirality control , (2)Doping levelcontrol,(3) The probability of a CNT to be metallic [12].

Test bench used for interconnect simulation isshown in Fig. 9 for the analysis of process and temperaturevariation on circuit performance. Table I shows the devicevariable parameters and process variation assumption for thevariability analysis. A 13% random variation is given to theCNT diameter so that it will reflect 10% random variation inVth. Si-MOSFET HSPICE model files are generated fromspecific tool called “Nano CMOS” 32nm technology forequal Vth for fair variability comparison with CNFET at(13,0) chirality vector.. Ratio of mean (µ) and standarddeviation (σ) for delay and PDP is calculated by Monte Carlosimulation for 50 runs per simulation. CNT diameter affectsnot only the CNT source and drain resistance, but also theconductivity of the channel [16].

TOX variation also affects the drive current of CNFET.Table 2 and Table 3 give variability coefficient (dispersion)(σ/ μ) for PDP and delay respectively. As shown in tablesbelow, it has been found that CNFET (TOX=4nm) havesuperior robustness against process and temperaturevariations.

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TABLE I. PROCESS ASSUMPTION

TABLE II. VARIABILITY COEFFICIENT OF PDP

TABLEII I. VARIABILITY COEFFICIENT OF DELAY

VI. CONCLUSION

Interconnect drivers are successfully analyzed usingCMOS and CNFET devices at deep submicron technologynode. We have explored optimized CNFET in subthresholdinterconnect applications. It is observed that CMOS devicesare more prone to variation than CNFET. CNFET driverdriving 1000µm cu-interconnect show 42% and 46% delayand PDP improvement at 1000µm over Si-MOSFET basedbuffers. Optimizing the CNFET parameters shows 52% and63% performance improvement in delay and PDP over theSi-MOSFET based interconnect resource.

The robustness of the drivers against process andtemperature variation has also investigated. From variabilitypoint of view, for Si-MOSFET there is tremendous impactof process variation for subthreshold operation due toexponential dependence of current on the threshold voltage,where as in CNFET threshold voltage is inverselyproportional to diameter of CNT. Optimized CNFET showsmore variation than conventional CNFET.

Reducing the variability problems in optimized CNFETdrivers will further allow to reduce the supply voltage forultra low energy applications

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