Performance Characterization and Architecture Exploration of PicoRadio Data Link Layer

Mei Xu and Rahul ShahEE249 Project

Fall 2001Mentor: Roberto Passerone

Project Description Complete the data link layer functional

description in VCC (initialization & maintenance blocks)

Develop target architecture platforms for implementation

Use VCC Architectural Services to estimate performance on different architectures

Identify an architecture that is suitable for the implementation of PicoNode III

Motivation Identify missed events Estimate system-level performance Provide data on the usage of

processors, buses, and other shared devices

Provide idea of potential target architectures and their characteristics

Data Link Layer – Major Blocks

Initialization & Maintenance Block Local Address Manager Neighbor Search Block Control Message Packetization Block Control Message Dispatcher Transmit Data Path Receive Data Path Transmit/Receive Controller Medium Access Control (MAC)

Control Data

Data Link Layer Behavior

LocalAddrMem

Netw

orkSearch

Netw

orkResult

Network Search Nb

NbLoc

NbStatus

NbLM

NbSize

NbAddr

FromMngr

ToMngr

FromRX

ToMsg

Local Info Processing

AddrSpace

Location

NumAvail

Assign

Local Addr Manager

Rand

RandNumAssigned

UniformPulses

StartT

TExpTimer

Timer_

Read

WriteRNG

clock

MyTimer

NW

_Search

From_N

W

From

_Phy

To_

NW

NW

_Res

ult

To_Phy

Node B

Assign

ToD

P

Fro

mP

roc

Init & Mnt Manager

StartTimer

TimerExp

StartInitMnt

AssignedToMsg

Fro

mD

PC

ntrl

Star

t

Init & Maint Timer

SetChl

ToT

XD

ataP

ath

FromRXTXCtrl

From

Init

MESSAGE

From

Mai

nten

ance

RX

From

Phys

ical

Lay

e

ToN

etwork

ToN

L

ToControlRX Data Path

TX

ToP

hyL

ayer

From

Net

wor

k

From

Mes

sage

TXReq

TXAck

TX Data Path

TXAskPermit

Permit

Ask

MA

C

Cha

nnel

Bac

koff

SetC

hann

el

Ask

ToT

X

Ask

ToR

X

TX

Don

e

RX

Don

e

RXGotMsg

FromM

anager

ToM

sg

TXRX Controller

CtrlT

imer

Tim

erExpired

ToM

anager

Cnt

rlT

ime

Exp

ired

Timer Controller

MyQT13_inst

MyQT11_inst

MyQT8_inst

MyQT3_inst

MyQT16_inst

MyQT7_inst

MyQT10_inst MyQT12_inst

MyQT14_inst

MyQT5_inst

MyQT2_inst

MyQT6_inst

MyQT1_inst

MyQT9_inst

MyQT4_inst TXTimer

MyQT15_inst

Basic Y-Chart

Behavior Architecture

Mapping

Flow to implementation

•Describe & verify behavior•Describe architectures•Explore HW/SW design tradeoffs•Integrated flow to implementation

The VCC Design Flow

Target Architectures

Architecture 0 – ASIC only Architecture 1 – CPU only Architecture 2 – ASIC and CPU

(hybrid)

Architecture 1:ARM CPU Only

Architecture

ARM7TDMI

TDMI_DataBus

TDMI_InterruptBus

eCos

SimpleMemoryMemor

y

ARM 7 CoreeCos RTOS – Round RobinTime Sliced BusSimple Memory

CPU Utilization vs. Clock Speed

Loss of events

CPU Latency vs. Clock Speed

CPU Utilization at 100khz

Architecture 2:ARM CPU + ASIC

Architecture

ARM7TDMI

TDMI_DataBus

TDMI_InterruptBus

ASIC eCos

SimpleMemoryMemor

y

ARM 7 CoreeCos RTOS – Round RobinASICTime Sliced BusSimple Memory

Mapping

Mapping of Major Blocks

Initialization & Maintenance Block Local Address Manager Neighbor Search Block Control Message Packetization Block Control Message Dispatcher Transmit Data Path Receive Data Path Transmit/Receive Controller Medium Access Control (MAC)

ASIC ARM

CPU Utilization vs. Clock Speed

Loss of events

CPU Latency vs. Clock Speed

CPU Utilization at 10kHz

RTOS Gantt Chart (5kHz)

Tx and Rx block take large time

Some Observations Very bursty system since nodes are

mostly sleeping High peak to average load Low resource utilization Power down of resources necessary

Control Path better suited to hardware

Data Path better suited to software

Conclusions Hybrid Architecture vs. only CPU:

Lower clock speed needed Will result in lower power

consumption Hybrid Architecture vs. only ASIC:

Higher latency More flexibility

Possible Improvements to VCC Native support for power

performance estimation Interface with network simulators

to simulate large networks Runtime linking Trace driven simulations

Better characterization of architectural resources

Future Work Do a power performance

estimation Simulate the whole node –

application, network & data link layer

Design power manager and estimate node performance