Rawad N. Al-Haddad, Carthik A. Sharma, Ronald F. DeMaraUniversity of Central Florida

Performance Evaluation of Two Performance Evaluation of Two Allocation Schemes for Combinatorial Allocation Schemes for Combinatorial

Group Testing Fault IsolationGroup Testing Fault Isolation

Agenda

• Overview of Group Testing AlgorithmsOverview of Group Testing Algorithms• Overview of Fault Handling TechniquesOverview of Fault Handling Techniques• Multi-stage Adaptive Group TestingMulti-stage Adaptive Group Testing• Equal Share Allocation SchemeEqual Share Allocation Scheme• Interleaved Allocation SchemeInterleaved Allocation Scheme• Performance Comparison of Allocation Performance Comparison of Allocation

StrategiesStrategies

Group Testing Algorithms

• Origin – World War II Blood testingOrigin – World War II Blood testing ProblemProblem: Test samples from millions of new : Test samples from millions of new

recruitsrecruits SolutionSolution: Test blocks of sample before testing : Test blocks of sample before testing

individual samplesindividual samples• Problem DefinitionProblem Definition

Identify subset Identify subset QQ of defectives from set of defectives from set PP Minimize numberMinimize number of tests of tests Test Test v-subsetsv-subsets of of PP Form suitable blocksForm suitable blocks

Device Failure

Duration:

Target:

Detection:

Isolation:

Diagnosis:

Recovery:

Transient: SEU Permanent: SEL, Oxide Breakdown, Electron Migration, LPD

Repetitive Readback

DeviceConfiguration

Approach: TMRBIST

Processing Datapath

DeviceConfiguration

Processing Datapath

Bitwise Comparison

Invert BitValue

IgnoreDiscrepancy

MajorityVote

STARS

SupplementaryTestbench

CartesianIntersection

Worst-caseClock Period

Dilation

Replicate inSpare Resource

Characteristics

MethodsCED

Duplex Output

Comparison

Fast Run-time Location

Select SpareResource

DuplexOutput

Comparison

unnecessary

Repetitive Intersections

EvolutionaryAlgorithm usingIntrinsic Fitness

Evaluation

Fault-Handling Techniques

Dueling

CGT-Based

Isolation Problem Outline

ObjectivesObjectives Locate faulty logic and/or interconnect resource: a single stuck-Locate faulty logic and/or interconnect resource: a single stuck-

at fault model is assumedat fault model is assumed Online Fault Isolation: device not entirely removed from serviceOnline Fault Isolation: device not entirely removed from service

Two Schemes:Two Schemes: Equal Share:Equal Share:

Suspect resources are divided into equal subsets, each Suspect resources are divided into equal subsets, each subset is assigned to one individual in the population, subset is assigned to one individual in the population,

Each suspect resource is guaranteed to be covered by at Each suspect resource is guaranteed to be covered by at least one individualleast one individual

Interleaved:Interleaved: Suspect subsets are shared among individuals, Suspect subsets are shared among individuals, Coverage Factor (CF)Coverage Factor (CF) determines the minimum number of determines the minimum number of

individuals (individuals ( 1) which utilize each resource in the suspect 1) which utilize each resource in the suspect poolpool

Equal Share Allocation

Allocation StrategyAllocation Strategy Suspect poolSuspect pool of of NN LUTs LUTs Population Population of of RR individuals individuals Each individual gets Each individual gets MM suspect resources, where suspect resources, where M = N/RM = N/R.. Maximal possible gain if the fault is articulated by the test Maximal possible gain if the fault is articulated by the test

vectors is a factor of vectors is a factor of RR (from (from NN suspect resources to suspect resources to MM)) Minimal possible testing phase gain: No gain at all if fault is not Minimal possible testing phase gain: No gain at all if fault is not

articulatedarticulated

Ind1

N LUTs

Ind2 Ind3 Ind4 Ind R

M LUTs M LUTs M LUTsM LUTs M LUTs

Experiments

• Experimental SetupExperimental Setup DES-56 encryption circuitDES-56 encryption circuit Xilinx ISE design tools to place and route the designXilinx ISE design tools to place and route the design Virtex II Pro FPGA deviceVirtex II Pro FPGA device Fault Injection and Analysis Toolkit (FIAT)Fault Injection and Analysis Toolkit (FIAT)

Application Programmer Interfaces (APIs)Application Programmer Interfaces (APIs) to interact with to interact with the Xilinx ISE tools to inject and evaluate faultsthe Xilinx ISE tools to inject and evaluate faults

Editing the design file rather than the configuration Editing the design file rather than the configuration bitstreamsbitstreams to introduce stuck-at-faultsto introduce stuck-at-faults

Editing Editing User Constraint Files (UCF) User Constraint Files (UCF) to control resource to control resource usageusage

Equal Share Results

0

2

4

6

8

10

12

14

16

3 4 5 6Groups

Num

ber o

f Run

s

15 individuals 20 individuals 25 individuals

Total number of runs for each group count

0500

100015002000250030003500400045005000

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Runs

Test

vec

tors

15 individuals 20 individuals 25 individuals

Number of test vectors required in each run

Results of three CGT experiments with different population size

PopulationIsolation results Number of groups

Required Test vectors DiscrepanciesSuccess Fail 3 4 5 6 Mean SD

15 17 3 0 13 6 1 4.35 0.587 247.4 3.7

20 17 3 14 6 0 0 3.3 0.470 311.9 2.55

25 17 3 14 6 0 0 3.3 0.470 525.3 2.6

Interleaved Allocation

Allocation SchemeAllocation Scheme Each LUT in the suspect pool is utilized by more Each LUT in the suspect pool is utilized by more

than one individual in the population than one individual in the population Implies “interleaving” of individuals over each LUT.Implies “interleaving” of individuals over each LUT. Interleaving degree decided by Coverage Factor.Interleaving degree decided by Coverage Factor. Coverage factor (CF): Number of individuals Coverage factor (CF): Number of individuals

utilizing each resource in the suspects pool utilizing each resource in the suspects pool Example: Example: CF = 2CF = 2 means that each suspected LUT means that each suspected LUT

is covered by two different individuals.is covered by two different individuals.

Interleaved Allocation Scheme

NN LUTs divided into LUTs divided into MM subgroups where subgroups where M = N/RM = N/R Each individual utilizes Each individual utilizes 22MM LUTs LUTs Discrepancy will reduce the number of suspects to Discrepancy will reduce the number of suspects to 2M2M rather rather

than than MM However, (100/However, (100/CF)% CF)% less chance of unarticulated faults.less chance of unarticulated faults.

N LUTs

Ind 1 Ind 2Ind 4 Ind 5Ind 3

Ind 3

S 1 S 2 S 3 S 4 S 5M LUTs M LUTs M LUTs M LUTs M LUTs

Interleaved Allocation scheme with CF = 2

Two-Pass Algorithm

• Pass one:Pass one: Reduce suspect list from Reduce suspect list from NN to to CFCFN/R,N/R, where where CFCF is the is the

coverage factor coverage factor Isolation granularity gain is reduced when Isolation granularity gain is reduced when CFCF is increased. is increased. Terminated once the first discrepant output is observed.Terminated once the first discrepant output is observed.

• Pass TwoPass Two Reduce suspect list from Reduce suspect list from CFCFN/R N/R to to N/RN/R (same gain as (same gain as

Equal Share)Equal Share) New data structure is introduced to expedite the process.New data structure is introduced to expedite the process. CalledCalled Interleaved Individuals Set Interleaved Individuals Set (IIS)(IIS)

Interleaved Individuals Set

• Purpose:Purpose: Keep track of the interleaved individuals in a specific Keep track of the interleaved individuals in a specific

CGT configuration CGT configuration

• Example:Example:

N LUTs

Ind 1 Ind 2Ind 4 Ind 5Ind 3

Ind 3

S 1 S 2 S 3 S 4 S 5M LUTs M LUTs M LUTs M LUTs M LUTs

Ind 1

Ind 2

Ind 3

Ind 4

Ind 5

Ind 3 Ind 4

Ind 5 Ind 1

Ind 4 Ind 5

Ind 1 Ind 2

Ind 2 Ind 3

In pass two, individuals interleaving with the one In pass two, individuals interleaving with the one which articulated the fault in pass one will be tested.which articulated the fault in pass one will be tested.

Conclusion

• Equal Share:Equal Share: Best Case: Suspect List reduced from N to N/RBest Case: Suspect List reduced from N to N/R Worst Case: Zero gain (unarticulated fault)Worst Case: Zero gain (unarticulated fault) One pass onlyOne pass only

• InterleavedInterleaved Best Case: Suspect List reduced from N to N/RBest Case: Suspect List reduced from N to N/R Performed in two passes (NPerformed in two passes (N CFCFN/RN/R N/R) N/R) IIS minimizes overhead in Pass twoIIS minimizes overhead in Pass two Worst Case: Zero gain also. Worst Case: Zero gain also. BUT, less chance to occur than Equal share scheme BUT, less chance to occur than Equal share scheme

(because of interleaving)(because of interleaving)

References

Sharma, C. A. and R. F. DeMara (2006), “A Combinatorial Group Testing Method for FPGA Fault Location,” in Proceedings of the International Conference on Advances in Computer Science and Technology (ACST 2006), Puerto Vallarta, Mexico, 2006

Du D and Hwang, F. K (2000), "Combinatorial Group Testing and its Applications," Series on Applied Mathematics volume 12, World Scientific.

Sharma, C. A. (2007), "FPGA Fault Injection and Analysis Toolkit (FIAT)."