performance of laser annealed junctions in advanced cmos ......nmos 1.4 a 1.5 a • 1.4-1.5Å ......

Applied Materials ConfidentialFRONT END PRODUCTS GROUP

Performance of Laser Annealed Junctions in Advanced CMOS

DevicesS.B. Felcha, B.J. Pawlakb, T. Hoffmannc, E.

Collarta, S. Severic, T. Nodac,d, V. Parihara, P. Eybenc, W. Vandervorstc, S. Thirupapuliyura,

and R. Schreutelkampa

aApplied Materials, Sunnyvale, CA USAbNXP Semiconductors, Research, Leuven, Belgium

cIMEC, Leuven, Belgium dMatsushita Electric Industrial Co., Ltd., Japan

Applied Materials Confidential

2

FRONT END PRODUCTS GROUP

Ultra-Shallow Junction Challenges

Reducing junction depthMaintaining target sheet resistanceMore abrupt junctionsOptimized gate/SDE overlap

Two candidate USJ technologies– Co-implantation of diffusion-

retarding species with spike anneal

– Ultra-fast anneal (sub-melt laser anneal)

ITRS 2005

AdvancedTransitionSpikeAnneal

Junctions are becoming shallower and more difficult to form;Novel solutions required for implant and activation anneal

<59Å<81Å<170Å<250ÅXj

1.4nm/dec

2.0nm/dec

2.8nm/dec

4.1nm/decAbruptness

<1380Ω/sq<1430Ω/sq<760Ω/sq<660Ω/sqPMOS Rs

32nm45nm65nm90nmTech.Node

Source DrainExtension

Gate Dielectric

Gate Poly

Sp

ace

r

EOTXj

RsChannel


3


Purpose

Sub-melt laser anneal (LA) with minimal diffusion enables further transistor scaling

Spike RTA plus LA improves Polysilicon Gate depletion– Delays introduction of complex metal gates

Spike RTA plus LA improves SDE dopant activation

Steep thermal gradients of LA induce mechanical stress at Si-SiON interface– Impact on transistor performance and reliability

Study of influence of process conditions on transistor characteristics– LA temperature– N content in gate dielectric– Co-implanted F– Sequence of spike anneal, LA, and absorber layer deposition


4


Experimental Approach

Conventional SiON/poly-Si CMOS baseline– Gate dielectric

1.5nm and 2.0nm thin oxides with 14% N1.5nm thin oxides with 5% and 10% N

– B co-implanted with F into PMOS source/drain extension and poly-Si gateHigh dose FLower dose FNo F

– 65nm wide spacer– HDD implants– Spike anneal followed by LA

Modulate peak LA temperature by changing laser power1200°C (MPL) and 1300°C (HPL)

– NiSi formation


5


Polysilicon Gate Depletion Improvement (Tinv) with Laser Anneal after Spike Anneal

1.6

1.8

2

2.2

2.4

10 100 1000

HPRTAMP

T inv (n

m) a

t Vg=

|1|V

Lgate (nm)

PMOS

NMOS

1.4 A

1.5 A

1.6

1.8

2

2.2

2.4

10 100 1000

HPRTAMP

T inv (n

m) a

t Vg=

|1|V

Lgate (nm)

PMOS

NMOS

1.4 A

1.5 A

• 1.4-1.5Å reduction in Tinv with LA after spike anneal for PMOS and NMOS due to improved dopant activation in Polysilicon Gates• Delays need to introduce Metal Gates


6


Polysilicon Gate Depletion Improvement (TINV) with LA after Spike Anneal

1.71.81.9

22.12.22.32.4

980 1000 1020 1040 1060

RTARTA+MPLRTA+HPL

T INV (n

m)

RTA temperature (oC)

PMOS

NMOS

1.71.81.9

22.12.22.32.4

980 1000 1020 1040 1060

RTARTA+MPLRTA+HPL

T INV (n

m)


PMOS

NMOS

• 1.5Å reduction in TINV with LA after spike anneal for PMOS and NMOS• Both high and medium power LA lead to equivalent gain


7


Spike + Laser Impact on Rs

Rs sensitivity to LA temperature increases dramatically as spike Tdecreases (i.e. ≤ 32nm devices)

Spike + Laser is optimal for low-T Spike (<1010°C)Spike + Laser impact is significant on Arsenic

F 10keV+B 0.5keV, 7E14/cm2 As 1 keV, 1E15/cm2

1,000 1,100 1,200 1,300 1,400

1,000

800

600

400

200

1,000 1,100 1,200 1,300 1,400

1,400

1,200

1,000

800

600 Spike 1050°C

990°C

1010°C

1030°C

950°C

Spike 1050°C

1030°C1010°C

990°C

Shee

t Res

ista

nce

(Ω/s

q.)

Shee

t Res

ista

nce

(Ω/s

q.)

0 400

Laser Temperature (°C) Laser Temperature (°C)


8


Improvement in Transistor Series Resistance (RSD) with Spike RTA + LA

02468

1012

980 1000 1020 1040

PMOSNMOS

RS

D g

ain

over

RTA

onl

y (%

)


RTA+ HPL

RTA + high power LA (HPL) produces additional gain in RSD, especially for lower RTA temperatures


9


Spike Plus LA for 32nm C Co-Implant Junctions

High-temperature LA produces ~20% dopant activation boost for 32nm PMOS junctions (Xj ~ 15nm)

0

200

400

600

800

1000

1200

900 950 1000 1050 1100

Spike Temperature (C)

Shee

t Res

ista

nce

(ohm

s/sq

.)

Spike + 1350C DSASpike + 1200C DSASpike Only

LA

LA


10


Further Extendibility of C Co-Implant with Spike Anneal

Continued decrease of spike temperature extends co-implant technology to ≤32 nm junctions

NMOSPMOS


11


Improved S/D Resistance with F or C Co-Implant with Spike + Laser Anneal (SiON + FUSI Gate)

300

350

400

450

500

550

600

0 20 40 60 80Lgate at Ioff=60nA/um

Rsd

(Ohm

um

)

Ref. BF21100C Laser

1300C Laser

• C co-implantation improves both short channel effects and series resistance• Higher laser anneal temperature provides further Rsd reduction (enhanced dopant activation)

Ref. BF2 + 1050°C Spike

F + 1030°C Spike + Laser

F + 1050°C Spike + Laser

C + 1030°C Spike + Laser

C + 1050°C Spike + Laser


12


Improved Device Performance and S/D Activation with LA PMOS B Co-Implant with Spike RTA + Laser Anneal (SiON + FUSI Gate)

10% Ion gain is obtained for same Cov due to enhanced dopant activation and reduced Rsd

Lateral dopant diffusion is suppressed with C co-implant, producing smaller Cov

S. Severi et al., IMEC/AMAT: MRS Symp. C, Spring 2006.

Laser anneal enhances Ion and maintains reduced Cov obtained with C co-implant

1030oC

370

380

390

400

410

420

2E-16 3E-16 4E-16 5E-16

Cov (F/um)

Ion

(uA

/um

)

BF2+RTA

Ge+F+B+RTA+Laser 1300°C

Ge+C+B+RTA+Laser 1300°C

1030oC 1050oC

1050oC

1050oC

Better deviceperformance


13


Improvement in Performance/Short Channel Effect Trade-Off due to C Co-Implant and Spike + Laser Anneal

300350400450500550600650700750800

20 30 40 50 60

Lgmin @ Ioff=60nA/um

Idsa

t @ Io

ff=60

nA/u

m (u

A/u

m)

Ge+C+P Spike + 1200C Laser

As Spike + 1200C Laser

Ge+C+B Spike

Ge+C+B Spike + 1200C Laser

Ge+C+B Spike + 1300C Laser

PMOS: Reduced SCE (Lgmin) and small Idsat improvement with Laser AnnealNMOS: High P activation leads to better performance than As

NMOS

PMOS


14


Spike Anneal + LA Enables Drive Current and Short Channel Effect (SCE) Improvements

• TINV and RSD gains lead to improvement in performance/short channel effect trade-off for NMOS and PMOS• Medium power LA leads to higher performance than high power LA

-15

-10

-5

0

5

10

15

-30 -25 -20 -15 -10 -5 0 5

RTA RTA+HPLRTA+MPL

Δ Ids

at@

targ

et I of

f(μ

A/μ

m)

ΔLgmin

@ target Ioff

(nm)

NMOS

1035oC

990oC

-

-15

-10

-5

0

5

10

15

-30 -25 -20 -15 -10 -5 0 5

RTA RTA+HPLRTA+MPL

Δ Ids

at@

targ

et I of

f(μ

A/μ

m)

ΔLgmin

@ target Ioff

(nm)

NMOS

1035oC

990oC

-

1005°C

1020°C

+8%

-20nm

As implant F + B co-implant

-25

-20

-15

-10

-5

0

5

-25 -20 -15 -10 -5 0 5

RTA RTA+HPLRTA+MPLΔ I

dsat

@ ta

rget

I off

(μA

/μm

)

ΔLgmin

@ target Ioff

(nm)

1035oC

990oC

PMOS-

-25

-20

-15

-10

-5

0

5

-25 -20 -15 -10 -5 0 5

RTA RTA+HPLRTA+MPLΔ I

dsat

@ ta

rget

I off

(μA

/μm

)

ΔLgmin

@ target Ioff

(nm)

1035oC

990oC

1020°C

1005°C

+2%-8nm

Scalability (SCE)

Perf

orm

ance


15


Model of Thermo-Mechanical Stress (TMS) at SiON Interface due to LA

Thermal and mechanical stresses during high-temperature LA induce additional interface traps (Nit) and fixed charges (Qf) in gate dielectric

Poly-Si

LA – 1GP compress

x xxx xx xx

SiON

(100) Si

Poly-Si

LA – 1GP compressLA – 1GP compress

x xxx xx xx xxx xx xSiON

(100) Si

Poly-Si



(100) Si

Poly-Si

LA – 1GP compressive stressLA –


(100) Si

Poly-Si



(100) Si

Poly-Si



(100) Si

Poly-Si



(100) Si

Poly-Si

LA – 1GP compressive stressLA –


(100) SiQf

Nit

Poly depletion


16


Increase in Interface State Density due to LA

0

2

4

1 2 3

Tox=1.5nmTox=2nm

0

2

4

1 2 3RTA RTA+MPL

RTA+HPL

NIT

(x10

11 c

m-2

cy-1

)0

2

4

1 2 3

Tox=1.5nmTox=2nm

0

2

4

1 2 3RTA RTA+MPL

RTA+HPL

NIT

(x10

11 c

m-2

cy-1

)

Higher LA temperature increases Si dangling bonds and interface traps at Si/SiON interface

NMOS

PMOS


17


Effect of Interface Traps and Fixed Charges in Gate Dielectrics on Peak Mobility

220230240250260

Tox=1.5nmpe

ak m

obili

ty (c

m2 /V

s)

RTA RTA+MPL

RTA+HPL

NMOS

5060708090

100

1011 1012

Tox=1.5nmTox=2nm

NIT

+QF (#/cm2)

PMOS

RTA

RTA+MPLRTA+HPL

NIT

Qf

220230240250260

Tox=1.5nmpe

ak m

obili

ty (c

m2 /V

s)

RTA RTA+MPL

RTA+HPL

NMOS

5060708090

100

1011 1012

Tox=1.5nmTox=2nm

NIT

+QF (#/cm2)

PMOS

RTA

RTA+MPLRTA+HPL

220230240250260

Tox=1.5nmpe

ak m

obili

ty (c

m2 /V

s)

RTA RTA+MPL

RTA+HPL

NMOS

5060708090

100

1011 1012

Tox=1.5nmTox=2nm

NIT

+QF (#/cm2)

PMOS

RTA

RTA+MPLRTA+HPL

220230240250260

Tox=1.5nmpe

ak m

obili

ty (c

m2 /V

s)

RTA RTA+MPL

RTA+HPL

NMOS

5060708090

100

1011 1012

Tox=1.5nmTox=2nm

NIT

+QF (#/cm2)

PMOS

RTA

RTA+MPLRTA+HPL

NIT

Qf

Medium power LA minimizes stress, Nit and Qf, and mobility and device performance degradation


18


Effect of Co-Implant on Long Channel Transistor Threshold Voltage (Vt) Difference between RTA and RTA+LA

1

10

100

1000 1100 1200 1300 1400

No Flow dose FHigh dose F

ΔV

t shi

ft (m

V)

Laser peak temperature (oC)

Lg=1μm

• ΔVt shift is reduced by decreasing or eliminating (use C) co-implanted F• Indicates smaller amount of added interface states at Si-SiON interface due to stresses from LA thermal gradients


19


Performance Improvement with C Co-Implant and Spike + High-Temperature Laser Anneal

• High-dose F co-implant results in no Ion-Ioff improvement with additional 1300°C LA • C co-implant (no F) produces increasing Ion-Ioff improvement with LA temperature, reflecting lower generation of interface states


20


Effect of Gate Dielectric N Content on Long Channel Transistor Vt Difference between RTA and RTA+LA

1

10

100

1000 1100 1200 1300 1400

N 14%

N 10%

N 5%

ΔV

t shi

ft (m

V)

Laser peak temperature (oC)

Decreasing N content in dielectric reduces Nit and ΔVt shift and improves possibility to use higher LA power


21


Transistor Lifetime (NBTI) for RTA alone, RTA+MPL and RTA+HPL

1

100

104

106

108

0 2 4 6 8 10

RTARTA+MPLRTA+HPL

Tim

e (a

.u.)

(VG-V

T)/T

INV (MV/cm)

EOT=1.5nmT=105oC

1

100

104

106

108

0 2 4 6 8 10

RTARTA+MPLRTA+HPL

Tim

e (a

.u.)

(VG-V

T)/T

INV (MV/cm)

EOT=1.5nmT=105oC

Transistor lifetime with medium power LA is same as for spike RTA alone, even with high F dose and high N content in dielectric


22


Effect of Absorber Layer (AL) and Thermal (Spike + LA) Process Sequence

9% PMOS performance improvement over spike reference with AL/LA/spike, while maintaining 7% NMOS gain

SDE

Spacer

HDD

NiSi

AL

LaserLaser

Spike RTA

ALSpike RTA

AL

Laser

Spike RTA

A B C

AL removal

PMOS NMOS


23


Device Mobility and Reliability with AL/LA/Spike Sequence

AL/LA/spike results in same NBTI lifetime and mobility with 1350°C LA as spike reference

Mobility NBTI Lifetime

10

100

1000

104

105

106

107

108

109

0.7 1

D7 1350C LAD8 1350C LAD10 1350C LASpike anneal Li

fetim

e@30

mV

V th s

hift

[s]

(VG-V

th)[V]

10years

0

20

40

60

80

100

0.2 0.5 0.8

D7 1350C LAD8 1350C LAD10 1350C LAD7 spike D8 spike D10 spike

μ[cm

2 /Vs]

Eeff

[cm/MV]

CBA

SDE

Spacer

HDD

NiSi

AL

LaserLaser

Spike RTA

ALSpike RTA

AL

Laser

Spike RTA

A B C

AL removal

CBA

CBA


24


SSRM Image of C Co-Implant with Spike Anneal

C co-implant reduces vertical junction depth and lateral diffusion, consistent with SIMS profiles and reduced Cov


25


SSRM Image of Device with LA-only

40nm4nm

60nm

100nm

20-24 11RTA Sub. ms.

LA only reduces vertical junction depth and lateral diffusion, consistent with SIMS profiles and reduced Cov


26


LA Micro-Uniformity Measured by Capres

Sample:– 1200C Laser-annealed sample (As - 5keV) (no absorbing layer film)

Excellent uniformity with min-max range ~ 2%

~2%

Rs [ohm/sq]

Rs [ohm/sq]2D-contours

(Courtesy: W. VanDerVorst, IMEC)

Rs range 2%


27


Summary

Spike RTA plus medium power LA is compatible with POR CMOS processes

– Maintains poly depletion improvement– Maximizes device performance– Preserves dielectric quality and transistor lifetime

Lowering F dose and gate dielectric N content are beneficial– Reduce additional charges generated by LA– Should enable optimized device performance and lifetime, even with high power LA

Altering thermal process sequence to have spike RTA after LA produces best results

– Large PMOS performance improvement with high power LA– No mobility or lifetime degradation– Spike RTA “heals” dielectric damage and charges induced by LA


28


Thank You.

performance of laser annealed junctions in advanced cmos ......nmos 1.4 a 1.5 a • 1.4-1.5Å ......

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