A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery

Tae-Young Oh, Seung-Hyun Yi, Sung-Hyun Yang, Byong-Chan Lim, and Kuk-Tae Hong

LG Electronics, Republic of Korea GS Gangnam Tower, 679 Yeoksam-dong, Gangnam-gu

Seoul, Republic of Korea Tel : +82-2-2005-9817, Fax : +82-2-2005-9701, Email : otyoung@lge.com

Abstract- This paper presents a digital PLL for low long-term

jitter clock recovery. A jitter reduction scheme for digitally controlled oscillator is proposed and 39% jitter reduction is observed. A 5-phase digital phase frequency detector (PFD) has 265 ps resolution and controls output clock phase by 132 ps step. The long-term jitter is measured as 460 ps pk-pk. This digital PLL is implemented in 0.18 µm CMOS process using 0.417 mm2

and consumes 61.0 mW power.

I. INTRODUCTION

A clock recovery PLL with very low long-term jitter is essential in high definition video and audio systems, because the reference signal is up to tens of thousand times slower than recovered clock in some cases. The output clock jitter accumulates between each reference signal to create large long-term jitter which results in pixel fluctuation of displayed image for video pixel clock recovery, and video and audio data mismatch for audio clock recovery. Digital PLLs offer many advantages over conventional analog PLLs for these applications, which include superior noise immunity, guaranteed performance, compact size, scalability on process. In recent years, there have been works for digital PLL to utilize those advantages, however, the output clock jitter was large[1],[4], or oscillators were delay type which are not suitable for clock recovery purpose due to jitter accumulation between reference clocks[2]-[4]. This paper presents a clock recovery digital PLL in 0.18µm CMOS technology, which incorporates a digital loop pass filter (LPF) and a flying adder type digitally controlled oscillator (DCO)[1], and introduces several new approaches: DCO jitter reduction scheme, high resolution 5-phase digital PFD with output clock phase control and PFD controlled bandwidth digital LPF.

II. PLL Design

Fig. 1 is the block diagram of this digital PLL. The digital PFD detects the phase difference between reference signal and feedback signal with 265ps step. This detected phase difference is handed to a digital LPF by 12 bits digital word. The loop pass filter is a first order digital filter and controls the DCO with 28 bits digital word. A flying adder type DCO synthesize a frequency according to this 28 bits digital word from the 756MHz 5-phase clock of an analog PLL. A phase interpolator and clock realigner are used to reduce the deterministic jitter in DCO output clock.

Simplified circuits of flying adder type DCO is illustrated in Fig. 2 a). This DCO is a flying adder type based on the work of L. Xiu [1] which has phase drift free advantage over delay type DCO [2]-[4]. The 756 MHz 5-phase clock is divided to 356MHz 10-phase clock prior to DCO, because the adders in DCO cannot operate at 756 MHz. Then, a duty cycle corrector changes the duty cycle of that 10-phase 356 MHz from 5:5 (high:low) to 3:7. The bottom side MUX and 28-bit adder create the rising edge of DCO output clock and top side MUX and 4-bit adder create falling edge. The deterministic jitter of this DCO is 1/10/378MHz = 265 ps, since all edges of output clocks are generated by the rising edge of 378 MHz 10-phase clock. The output frequency of this DCO is

24

_10 2378

FREQ_IN<27:0>DCO OUTF MHz ×= × .

Fig. 2 b) is the timing diagram of DCO when FREQ_IN<27:0>=E000000 (Hexadecimal). Each pulse in MUX_RISE signal is generated from CLK_IN<0>, CLK_IN<4> and CLK_IN<8>, respectively. The MUX_FALL signal is slower than MUX_RISE by 7∆t, and generates a clock for 28-bit adder and 4-bit register. At t1 and t2, the bottom side MUX changes its input from CLK_IN<0> to CLK_IN<4> and from CLK_IN<4> to CLK_IN<8>, respectively. If the duty cycle of CLK_IN is 5:5, the values of CLK_IN<4> at t1 and CLK_IN<8> at t2 are still high and

756MHz 5 Phase

Analog PLL

27MHz Clock from Crystal Oscillator

265ps ResolutionDigital PFD

DigitalLPF

Feedback Divider

ReferenceFlying

Adder Type DCO

28 Clock Realigner

½ Divider

378MHz, 10 Phase

OutputDivider

9 bit Delay Control

Clock Out

PhaseInterpolator

756MHz, 10 Phase

Digital PLL

12

Feedback

16 bit Dividing Value Control

Fig. 1 Block diagram of the system.

IEEE 2006 Custom Intergrated Circuits Conference (CICC)

1-4244-0076-7/06/$20.00 ©2006 IEEE 74525-1-1

glitches occur in MUX_RISE. Therefore, the duty cycle correction has a critical role in stable operation of this DCO. If all components in DCO are ideal without any delay, the minimum frequency this DCO can generate is

_10378 27014

DCO OUTF MHz MHz= × = .

In actual design, the minimum supporting frequency is even lower, because MUX changes its input after the delay in buffers and flip-flops. As a result, this DCO still works when FREQ_IN=FFFFFFF, with 236 MHz minimum supporting frequency. On the other hand, the maximum supporting frequency is limited by the speed of adders in DCO, which is 540 MHz in this design.

The 756 MHz 5-phase clock required for this DCO are generated by a conventional analog PLL with 27 MHz reference clock from an external crystal oscillator. 27 MHz is greatly higher than the reference signal which is up to a hundred kilohertz, therefore the DCO output clock phase drift between each reference signal is virtually reduced to zero.

This 27 MHz crystal oscillator also provides a clock to other digital circuits on the application IC, not an additional requirement from this digital PLL.

Fig. 3 a) shows blocks and circuits around DCO for jitter reduction. The phase interpolator in Fig 3 a) generates 756 MHz 10-phase clock and passes to a clock realigner. This clock realigner has two purposes. One is eliminating the random jitter produced in frequency synthesizing process of DCO. A rising edge of the 756MHz 5-phase reference clock needs to pass 13 gate stages to arrive at the output of DCO. The layout path length for each multi-phase clock cannot be identical. Consequently, those effects accumulate to a large amount of DCO output jitter. The clock realigning to the original input clock solves this problem. The other purpose is reducing the deterministic jitter to 132 ps by realigning the output clock to 756 MHz 10-phase clock edges. The deterministic jitter also can be reduced to 132ps by frequency synthesis from 756 MHz 10-phase reference clocks edges,

10 to

1 M

UX

10 to

1 M

UX

D QQ

D QQ

4bit Adder+Regab out

CLK_IN<9:0>

28bit Adder+Regba

out<27:24> out<23:0>

4bit Regin<3:0>

out<3:0>

FREQ_IN<27:0>

FREQ_IN<27:25>

DCO_OUT( 378MHz, 10 Phase Clock3:7 Duty Cycle )

MUX_RISE

MUX_FALL

Duty Cycle Corrector

DIV_OUT<9:0>

CLK_IN<0>

CLK_IN<4>

MUX_RISE

MUX_FALL

CLK_IN<8>

DCO_OUT

1 1 26510 378

t psMHz

∆ = × =

14 t∆ 14 t∆ 14 t∆7 t∆ 7 t∆ 7 t∆ 7 t∆

1t 2t

Fig. 2 a) Simplified circuits of flying adder type DCO. b) Timing diagram of DCO.

a)

b)

Fig. 4 Simplified circuits and block diagram for 5-phase PFD and phase selector

• PHASE_A<k> = Clk( t - 2(k-1)Φ)• PHASE_B<k> = Clk( t – (2k-1)Φ)

10Φ= 1/756MHz = 1.32ns

OUTPUT_CLOCK

Phase Interpolator

VCO_OUT<4:0> 756MHz, 5 Phase

½ Divider

378MHz, 10 Phase

Clock Realigner

Delay

PHA

SE_A

<4:0

>

PHA

SE_B

<4:0

>

10 to 5MUX

PHASE_OUT<4:0>

D Q

Clk_Realigner<0>

SEL

CLKD OUT

Clk_Realigner<1>SELCLKD OUT

Clk_Realigner<2>SELCLKD OUT

Clk_Realigner<3>SELCLKD OUT

Clk_Realigner<4>SELCLKD OUT

PHASE_OUT<0>

PHASE_OUT<1>

PHASE_OUT<2>

PHASE_OUT<3>

PHASE_OUT<4>

SELECT<0>

SELECT<1>

SELECT<2>

SELECT<3>

SELECT<4>

DCO_OUT

Clock Realigner

OUTPUT_CLOCK

Flying Adder Type

DCO

DCO_OUT

DELAY_EN

SELECT<4:0>

Clock Realign Controller

Fig. 3 a) Block diagram for jitter reduction scheme. b) Simplified circuits of clock realigner.

a) b)

PFD 1stSEL CLK_B CLK_A Feedback Reference

SIGNDIFF[7:0]

D Q

REFERENCE

FEEDBACK

Lead-Lag Comparator

CounterENB

MUX

SIGN

DIFF[7:0]

CLK_ACLK_B

SEL

D Q

D Q

D Q

ADDERSIGN_1 IN_1[7:0]SIGN_2 IN_2[7:0]SIGN_3 IN_3[7:0] SIGN_4 IN_4[7:0]SIGN_5 IN_5[7:0]

OUT[11:0]

PHASE SHIFT

ADDER

PFD_OUT[11:0]

FINE_DELAY_EN

SHIFT[8:0]

LPF_IN[11:0]

LPF_IN[11:0]

SHIFT[8:0]

PHASE_B[0]PHASE_A[0]FEEDBACKREFERENCE

PHASE_B[1]PHASE_A[1]

PHASE_B[4]PHASE_A[4]

5 PHASE PFD

PFD 2ndSEL CLK_B CLK_A Feedback Reference

SIGNDIFF[7:0]

PFD 5thSEL CLK_B CLK_A Feedback Reference

SIGNDIFF[7:0]

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however using phase interpolator and clock realigner greatly saves DCO complexity and area.

The clock realigning process occurs as following. The phase interpolated clock, PHASE_B<4:0> in Fig 3 a), is slower than PHASE_A<4:0> by 132 ps. A 10-to-5 MUX passes PHASE_A<4:0> or PHASE_B<4:0> to PHASE_OUT<4:0> depending on the value of DELAY_EN signal. SELECT<4:0> chooses the clock to which DCO_OUT needs to be realigned. When out<23> value of the 28-bit adder in DCO is high, 132 ps additional delay is necessary. Therefore, the clock realigner controller sends DELAY_EN to 10-to-5 MUX, and PHASE_B is chosen to realign DCO_OUT.

To achieve high resolution of digital PFD, the 756 MHz 5-phase reference clock to DCO is used for time interleaving sampling as shown in Fig 4. High resolution PFD is essential in clock recovery applications, because the reference clock may have large jitter or spread spectrum and recovered clock needs to follow this property for accurate data acquisition. In other words, the recovered clock needs to become faster or slower following the reference clock frequency fluctuation. Therefore, the phase fluctuation of reference signal is required to be measured with high resolution. Fig. 4 shows the block diagram and simplified circuits of this 5-phase digital PFD. Each PFD samples reference and feedback signal with different clock phases, making the resolution of this digital PFD to 265 ps.

The phase shift function is implemented by adding an adder to the output of digital PFD. This adder creates an offset to the digital PFD output, resulting in a corresponding phase shift to the output clock. The phase shift control step is 265 ps which is same as the resolution of digital PFD, however, the step can be further reduced by changing the sampling time of reference and feedback signal. In this digital PLL, the sampling clock of feedback signal can be chosen as 0 delayed (PHASE_A<4:0>) or 132 ps delayed (PHASE_B<4:0>). These sampling clocks are generated by the phase interpolator for DCO. If the PHASE_B is chosen, the feedback signal will also have additional 132 ps delay after PLL is locked, because the output of digital PFD will be the same as PHASE_A sampling case only if feedback signal also has 132 ps delay.

Fig. 5 is the digital LPF of this digital PLL and simulated performance. A first order digital filter is used, making the whole system second order [1], [2]. This type of digital filter is

widely used in digital PLL and stability was verified. G1 and G2 are variables that decide loop bandwidth and stability. All multiplication functions are implemented by shift registers for small area and fast evaluation, therefore G1 and G2 values only can be 2n where n is an integer. The deadzone of PFD is removed by adding one if LPF_IN is zero or greater than zero. The values of G1 and G1 are controlled by the output value of

265ps (DCO Deterministic Jitter)

440ps (DCO Tota l Jitter)

a)

132ps (DCO Determ inistic J itter)

270ps (DCO Total J itter)

b)

Fig. 6 DCO jitter measurement result. a) clock realigner off b) clock realigner on

Recovered Pixel Clock (202.5MHz)

Reference Signal (93.8kHz) (Used as Trigger Signal)

460ps (@ 1000 samples )

Jitter Histogram

Fig. 7 Locking image and long-term jitter measurement result.

H(Z) = G1 + 1 - Z-1

G2Transfer Function :

LPF_OUT<27:0>

G1

G2

Z-1

LPF_IN<11:0>LPF Bandwidth

Control

PLL Lock Detector

PFD Dead-zone

Removal

LOCK_DETECT

LOCK_DETECT

×

×

++

0 20 40 60 80 100 120 140 160 180 200156M

157M

158M

159M

160M

161M

162M

163M

01

LPF_

OUT

<27:

0>

# of Reference Signal Pulses Passed

Fig. 5 Block diagram of digital LPF and simulated property.

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digital PFD. If the output value of PFD keeps being smaller than a certain value, LOCK_DETECT signal changes to high and G1 and G2 value changes to make the loop bandwidth wider or narrower depending on application.

III. Experimental Results

The jitter measurement results of DCO are drawn in Fig. 6. The DCO control digital value was fixed to a constant to verify the performance of DCO only. For Fig. 6 a), the DCO output clock was set to bypass the clock realigner to disable jitter reduction scheme. Therefore, the DCO deterministic jitter of 265 ps can be obviously noticed by two peaks in the jitter histogram. The total jitter is 440 ps, including 175 ps random jitter. In Fig. 6 b), the jitter reduction scheme is enabled and those two peaks in Fig. 6 a) are merged to one. The random jitter is also reduced to 138ps, since the random jitter generated in frequency synthesis process of DCO is removed by clock realigning. As a result, the total jitter is reduced to 270ps, which means about 39% reduction of DCO jitter. Fig. 7 is the locking image and long-term jitter measurement result. The measurement was performed by measuring the jitter in recovered clock triggered by reference signal. This 93.8 kHz reference signal is generated by a PC graphic card as horizontal sync signal (HSYNC) with 300 ps pk-pk jitter in this test. The frequency multiplication factor is 2160 and output clock is 202.5 MHz. The short-term and long-term jitter are measured as 290 ps (pk-pk) and 460 ps (pk-pk), respectively.

The output clock phase with PHASE_SHIFT<8:0> control increment was measured and shown in Fig. 8. A monotonous shift of output clock phase can be verified. The shift step is 132ps, which corresponds to 1/28 of output clock period when PLL is set to generate maximum frequency, 270 MHz.

Fig. 9 is the chip micrograph of this digital PLL. Except 756MHz 5-phase reference clock generation PLL and phase interpolator, all layout was implemented by CMOS standard cells. Also, divider, adder and digital LPF were created by automated PNR software, which facilitates the process

migration of this PLL to finer technology. The layout size is 632.2 µm×660.3 µm under 0.18 µm CMOS process. This PLL consumes 30.1 mW with 3.3 V power supply and 30.9 mW with 1.8 V power supply. Table I summarizes the performance of this PLL.

IV. Conclusion

A digital PLL has been developed for low long-term jitter clock recovery. A new DCO jitter reduction scheme reduces DCO jitter to 270 ps (pk-pk). The 5 phase high resolution PFD with output clock phase control function controls output clock phase with 132 ps step. The long-term jitter of recovered clock is 460 ps (pk-pk). This PLL is suitable for clock recovery applications where the long-term output clock jitter performance and fine clock phase control are crucial.

REFERENCES

[1] L. Xiu, W. Li and J. Meiners, “A Novel All-Digital PLL With Software Adaptive Filter,” IEEE JSSC, VOL. 39, No. 3, pp. 476-483, Mar. 2004.

[2] A.M. Fahim, “A compact, low-power low-jitter digital PLL,” ESSCIRC, pp. 101-104, Sep. 2003.

[3] T. Olosson and P. Nilsson “A Digitally Controlled PLL for SOC Applications,” IEEE JSSC, VOL. 39, No. 5, pp. 751-760, May 2004.

[4] T. Watanabe and S. Yamauchi “An All-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time”, IEEE JSSC, VOL. 38, No. 2, pp. 198-204, Feb 200

Technology 0.18 µm 1P5M CMOS Process

Power Dissipation Total : 61.0 mW

( 3.3V : 30.1 mW, 1.8V : 30.9 mW ) Die Size 632.2 µm×660.3 µm = 0.417 mm2 Digital PFD Resolution 265 ps DCO Output Frequency Range 236 MHz ~ 540 MHz Output Frequency Range up to 270MHz DCO Jitter 270 ps (pk-pk), 52 ps (rms) Long-term Jitter 460 ps (pk-pk), 85 ps (rms)

Output Phase Control 132ps Step

Fig. 8 Phase shift function measurement result

TABLE I PLL Summary

756MHz 5 Phase

Reference Clock

Generation PLL

Digital LPF

Flying Adder Type

DCO

5 Phase PFD

Output DividerPhase Interpolator

632.2µm

660.

3µm

Fig. 9 Chip micrograph

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