Phase Comparison SystemPhase Comparison System

Digital - Analog Hybrid Digital - Analog Hybrid

Phase Comparison System

smplng = 64, phslts/cy = 16, wndw = 16 phslets, vrble wndw = yes

FDL = 7.0 ph, 7.0 ps, 1.0 ng, 2.0 mx, K = 0.2, uncertW = 0.0

FDH = 8.0 ph, 8.0 ps, 1.1 ng, 2.2 mx, COUNT = 8, 72 in samples

time error = 0.0 radiuns, gain error % = 0.0, residual error = 1.00 Amps

dual slope, slp1 = 0.00, slp2 = 0.00, knee = 10.00 Amperes

Keying on Raw Samples

Synchronization of Phasors

•Synchronization of sampling clocks or phasors is not needed

•Arbitrary time reference rotates phasor by an angle:

•Projecting a phasor back to a real value cancels the rotation:

Keying on Phasors

Mixed Excitation

•Mixed excitation is needed for single channel systems

•Used Ia, Ib, Ic, I1, I2, I2+K*I1, I2-K*I1 phasors in simulations

•I2+K*I1, I2-K*I1 worked best

•Suitable for digital implementation

Offset Keying

•For improved security, phase comparison schemes often use

offset keying:

|ilocal(t)| > FDH (Fault Detector High)

|iremote(t)| > FDL (Fault Detector Low)

Phase Comparison Operating Principle