Vout

ƒo = ƒn + ∆ƒ

Vd(t)

VCO output

External signal

Vi sin(2πƒit + θi)

Timing capacitor, Ct

Phase-locked loop

Timing resistor, Rt

PHASE-LOCKED LOOPS

The phase-locked loop (PLL) is used extensively in electronic communications for performing modulation, demodulation, frequency generation, and frequency synthesis. PLLs are used in both transmitters and receivers with both analog and digital modulation and with the transmission of digital pulses. Phase-locked loops were first used in 1932 for synchronous detection of radio signals, instrumentation circuits, and space telemetry systems. However, for many years the use of PLLs was avoided because of their large size, necessary complexity, narrow bandwidth, and expense. With the advent of large-scale integration, PLLs now take up little space, are easy to use, and are more reliable. Therefore, PLLs have changed from a specialized design technique to a general-purpose, universal building block with numerous applications. Today, over a dozen different integrated-circuit PLL produces are available from several IC manufacturers. Some of these are designated as general-purpose circuits suitable for a multitude of uses, while others are intended or optimized for special applications such as tone detection, stereo decoding, and frequency synthesis.

Essentially, a PLL is a closed-loop feedback control system in which the frequency of the feedback signal voltage is the parameter of interest rather than simply a voltage. The PLL provides frequency selective tuning and filtering without the need for coils or inductors. The basic phase-locked-loop circuit is shown in Figure 2-21 and consists of four primary blocks: a phase comparator (mixer), a low-pass filter, a low-gain amplifier (op-amp), and a voltage-controlled oscillator (VCO). With no external input signal, the output voltage, Vout, is equal to zero. The VCO operates at a set frequency called its natural or free-running frequency (ƒn), which is set by external (Rt) and capacitor (Ct). If an input signal is applied to the system, the phase comparator compares the phase and frequency of the input signal with the VCO natural frequency and generates an error voltage,

FIGURE 2-21 Block diagram for phase-lock loop

Phase comparatorKd (V/rad)

-π/2 +V rad

+π/2

-V 0° rad

Low-passfilter

Kƒ(V/V)

Low-gainamplifier Ka (V/V)

Voltage-controlled oscillator(ƒn)

Ko (Hz/V)

Hold-in range(ƒi)

Lock range = 2ƒi

Hold-in range(ƒi)

Upper locklimit, ƒiu

Lower locklimit, ƒii

ƒn

Pull-in range(ƒc)

Capture range = 2ƒc

Pull-in range(ƒc)

Upper capturelimit, ƒcu

Lower capturelimit, ƒcl

ƒn

FIGURE 2-22 PLL lock range FIGURE 2-23 PLL capture range

Vd(t), that is related to the phase and frequency difference between the two signals. This error voltage is then filtered, amplified, and applied to the input internal of the VCO. If the input frequency, ƒ i, is sufficiently close to the VCO naturally frequency, ƒn’ the feedback nature of the PLL causes the VCO to synchronize, or lock, to the incoming signal. Once in lock, the VCO frequency is identical to the input signal, except for a finite phase difference that is equal to the phase of incoming signal minus the phase of the VCO output signal.

Lock and Capture Range

Two key parameters of PLLs that indicate their useful frequency range are lock and capture range.

Lock range. Lock range is defined as the range of frequencies in the vicinity of the VCO’s natural frequency (ƒn) over which the PLL can maintain lock with an input signal. This presumes that the PLL was initially locked onto the input signal. Lock range is also known as tracking range. It is the range of frequencies over which the PLL will accurately track or follow the input frequency. Lock range increases as the overall loop gain of the PLL is increased (loop gain is discussed in a later section of this chapter). Hold-in range is equal to half the lock range (that is, lock range = 2 x hold-in range). The relationship between lock and hold-in range is shown in frequency diagram form in Figure 2-22. The lowest frequency that the PLL will track is called the lower lock limit (ƒu), and the highest frequency that the PLL will track is called the upper lock limit (ƒtu). The lock range depends on the transfer functions (gains) of the phase comparator, low-gain amplifier, and VCO.

Capture range. Capture range is defined as the band of frequencies in the vicinity of ƒn where the PLL can establish or acquire lock with an input signal. The capture range is generally between 1.1 and 1.7 times the natural frequency of the VCO. Capture range is also known as acquisition range. Capture range is related to the bandwidth of the low-pass filter. The capture range of a PLL decreases as the bandwidth of the filter is reduced. Pull-in range is the peak capture range (that is, capture range = 2 x pull-in range). Capture and pull-in ranges are shown in frequency diagram form in Figure 2-23. The lowest frequency the PLL can lock onto is called the lower capture limit (ƒcl), and the highest frequency the PLL can lock onto is called the upper capture limit (ƒcu).

The capture range is never greater than, and is almost less than, the lock range. The relationship among capture, lock, hold-in, and pull-in range is shown in frequency diagram form in Figure 2-24. Note that lock range > capture range and hold-in range > pull-in range.

∆ƒ∆V

Hold-in range(ƒi)

Lock range = 2ƒi

Hold-in range(ƒi)

ƒll

Capture range = 2ƒc

Pull-in range(ƒc)

Pull-in range(ƒc)

ƒnƒcl ƒcu ƒlu

VC

O o

utpu

t fre

que

ncy,

ƒo (

kHz)

180

100

80

50

Bias (volts)

-2 -1 0 +1 +2

ƒn

Voltage-Controlled Oscillator

A voltage-controlled oscillator (VCO) is an oscillator (more specifically, a free-running multivibrator) with a stable frequency of oscillation that depends on an external bias voltage. The output from a VCO is a frequency, and its input is a bias or control signal that may be a dc or ac

FIGURE 2-24 PLL capture and lock ranges FIGURE 2-25 Voltage-controlled oscillator input bias voltage-versus-output frequency characteristics

voltage. When a dc or slowly changing ac voltage is applied to the VCO input, the output frequency changes or deviates proportionally. Figure 2-25 shows a transfer curve (output frequency-versus-input bias voltage characteristics) for a typical VCO. The output frequency (ƒo) with 0-V input bias is the VCO’s natural frequency (ƒn), which is determined by an external RC network, and the change in the output frequency caused by a change in the input voltage is called frequency deviation (∆ƒ). Consequently, ƒo = ƒn + ∆ƒ, where ƒo = VCO output frequency. For a symmetrical ∆ƒ, the natural frequency of the VCO should be centered within the linear portion of the input-versus-output curve. The transfer function for a VCO is

Ko = (2-10)

where Ko = input-versus-output transfer function (hertz-pen-volt)∆V = change in the input control voltage (volts)∆ƒ = change in the output frequency (hertz)

Phase Comparator

A phase comparator, sometimes called a phase detector, is a nonlinear device with two input signals: an externally generated frequency (ƒi) and the VCO output frequency (ƒo). The output from a phase comparator is the product of the two signals of frequencies ƒ i and ƒo and, therefore, contains their sum and difference frequencies (ƒi + ƒo). The topic of mixing is analyzed in more detail later in this chapter. Figure 2-26a shows the schematic diagram for a simple phase comparator. νo is applied simultaneously to the two halves of input transformer T1. D1, R1, and C1 make up a half-wave rectifier, as do D2, R2, and C2 (note that C1 = C2 and R1 = R2). During the positive alternation of νo, D1

and D2 are forward biased and on, charging C1 and C2 to equal values but with opposite polarities. Therefore, C1 and C2 discharge equally through R1 and R2, respectively, keeping the output voltage

External Input signal

Vi (t) = Vi sin (2πƒit)

+C1

C2 R2

R1

Vout

D1

VCO input signal Vo sin (2πƒot)

D2

C2R2

R1

Vout = + VC1 – VC2 = 0 V

D2

+

-C1

+

--

+

Vo + -

-

“on”+ -

Vi +

-

+

+ -“on”

D1

C2R2

R1

D2

+

-C1

+

--

+

Vo -

“off”

Vi

“off”

D1

+

Ti

-

+

-

+

Vout = + VC1 – VC2 = 0 V

equal to 0 V. This is shown in Figure 2-26c. The two half-wave rectifiers produce equal-magnitude, opposite-polarity output voltages. Therefore, the output voltage due to νo is constant and equal to 0 V. The corresponding input and output waveforms for a square-wave VCO signal are shown in Figure 2-26d.

Circuit operation. When an external input signal [νin = Vi sin(2πƒit] is applied to the phase comparator, its voltage adds to νo, causing C1 and C2 to charge and discharge, producing a proportional change in the output voltage. Figure 2-27a shows the unfiltered output waveform shaded

(a)

(b)

(c)

-V

Diodes D1 and D2 “on”

C1 discharging

C2 discharging C2 charging

C1 charging +V

input voltage Vo

Output voltage Vout VC1

0 V

VC2

+V

-V

T

(d)

FIGURE 2-26 Phase comparator: [a] schematic diagram; [b] output voltage due to positive halfcycle of Voi [c] output voltage due to negative half-cycle of Voi; [d] input and output voltage waveforms

when ƒo = ƒi and νo leads νi by 90°. For the phase comparator to operate properly, νo must be much larger than νi. Therefore, D1 and D2 are switched on only during the positive alternation of νo and are off during the negative alternation. During the first half of the on time, the voltage applied to D1 = νo

– νi, and the voltage applied to D2 = Vo + νi. Therefore, C1 is discharging while C2 is charging. During the second half of the on time, the voltage applied to D1 = νo + νi, the voltage applied to D2 = νo – νi, and C1 is charging while C2 is discharging. During the off time, C1 are neither charging nor discharging. For each complete cycle of νo, C1 and C2 charge and discharge equally and the average output voltage remains at 0 V. Thus, the average value of Vout is 0 V when the input and VCO output signals are equal in frequency and 90° out of phase.

Figure 2-27b shows the unfiltered output voltage waveform shaded when νo leads νi by 45°. νi is positive for 75% of the on time and negative for a the remaining 25%. As a result, the average output voltage for one cycle of νo is positive and approximately equal to 0.3 V, where V is the peak input voltage. Figure 2-27c shows the unfiltered output waveform when νo and νi are in phase. During the entire on time, νi is positive. Consequently, the output voltage is positive and approximately equal to 0.636 V. Figure 2-27d and e show the unfiltered output waveform when νo leads νi by 135° and 180°, respectively. It can be seen that the output voltage goes negative when ν o leads νi by more than 90° and reaches its maximum value when νo leads νi by 180°. In essence, a phase comparator rectifies νi

and integrates it to produce an output that is proportional to the difference in phase between νo and νi.

Diodes D1 and D2 “off”

-V

D1 and D2

“on”

+V

Vi

T/2

Vd = V average = 0 V

+V

-V

T/2

Vo

-V

D1 and D2

“on”

+V

Vi

3T/4

Vd = V average = 0.3V

+V

-V

T/2

Vo

T

-V

D1 and D2

“on”

+V

Vi Vd = V average = 0.636 V

+V

-V

T

Vo

T

-V

D1 and D2

“on”+VVi

+V

Vo

T

(a)

(b)

(c)

D1 and D2

“off”

D1 and D2

“off”

D1 and D2

“off”

D1 and D2

“off”

-V

3T/4

Vd = V average = -0.3 V

T/4

-V

D1 and D2

“on”

+V

Vi

+V

-V

T

Vo

T

Vd = V average = -0.636 V

Vout

+V

180°0 V

0° 90°π rad

-V

0 rad π/2 rad

+V

180°0 V

0° 90°π rad

-V

0 rad π/2 rad

Vout

45°

135°

(d)

(e)

FIGURE 2-27 Phase comparator output voltage waveforms: [a] Vo leads Vi by 90°; [b] Vo leads Vi by 45°; [c] Vo and Vi in phase; [d] Vo leads Vi by 135°; [e] Vo leads Vi by 180°.

(a) (b)

D1 and D2

“off”

Vout

θe

2Vπ

Vout+V

+190°0 V

-90° 0°+π /2rad

-V

0 rad-π/2 rad

+V

(c)

FIGURE 2-28 Phase comparator output voltage [Vd] versus phase difference [θe] characteristics: [a] square-wave inputs; [b] sinusoidal inputs; [c] square-wave inputs, phase bias reference

Figure 2-28 shows the output voltage-versus-input phase difference characteristic for the phase comparator shown in Figure 2-26a. Figure 2-28a shows the curve for a square-wave phase comparator. The curve has a triangular shape with a negative slope from 0° to 180°. Vout is maximum positive when νo and νi are in phase, 0 V when νo leads νi by 90° and maximum negative when νo leads νi by 180∆. If νo advances more than 180°, the output voltage become less negative, and if νo lags behind νν the output voltage become less positive. Therefore, the maximum phase difference that the comparator can track is 90° + 90° or from 0° to 180°. The phase comparator produces an output voltage that is proportional to the difference in phase between νo and νi. This phase difference is called the phase error. The phase error is expressed mathematically as

θe = θi – θo (2-11)

where θe = phase error (radians)θo = phase of the VCO output signal voltage (radians)θi = phase of the external input signal voltage (radians)

The output from the phase comparator is linear for phase errors between 0° and 180° (0 to π radians). Therefore, the transfer function for a square-wave phase comparator for phase errors between 0° and 180° is given as

Kd = = (2-12)

where Kd = transfer function or gain (volts per radian)Vout = phase comparator output voltage (volts) θe = phase error (θi – θo) (radians) π = 3.14 radians νi = peak input signal voltage (volts)

Vout

θe

-V

D1 and D2

“on”

+V

Vi

-V

Vo

T

Vout = V average = 0 V

T/2 T/2

Vout +V

+90°-90° 0°

+π /2rad

-V

0 rad-π/2 rad

(b)

(a)

FIGURE 2-29 Phase comparator output voltage: [a] unfiltered output voltage waveform when Vi

leads Vo by 90°; [b] output voltage-versus-phase difference characteristics

Figure 2-28b shows the output voltage-versus-input phase difference curve for an analog phase comparator with sinusoidal characteristics. The phase error versus output is nearly linear only from 45° to 135°. Therefore, the transfer function is given as

Kd = volts per radian (2-13)

where Kd = transfer function or gain (volts per radian)θe = phase error (θi – θo) (radians)

Vout = phase comparator output voltage (volts)

From Figure 2-28a and b, it can be seen that the phase comparator output voltage Vout-0 V when ƒo = ƒi and νo and νi are 90° out of phase. Therefore, if the input frequency (ƒ i) is initially equal to the VCO’s natural frequency (ƒn), a 90° phase difference is required to keep the phase comparator output voltage at 0 V and the VCO output frequency equal to its natural frequency (ƒo = ƒn). This 90° phase difference is equivalent to a bias or offset phase. Generally, the phase bias is considered as the reference phase, which can be deviated + π/2 radians (+ 90°). Therefore, Vout goes from its maximum positive value at –π/2 radians (-90°) and to its maximum negative value at +π/2 radians (+90°). Figure 2-28c shows the phase comparator output voltage-versus-phase error characteristics for square-wave inputs with the 90° phase bias as the reference.

Figure 2-29a shows the unfiltered output voltage waveform when νi leads νo by 90°. Note that the average value is 0 V (the same as when νo led νi by 90°). When frequency lock occurs, it is uncertain whether the VCO will lock onto the input frequency with a + or – 90° phase difference. Therefore, there is a 180° phase ambiguity in the phase of VCO output frequency. Figure 2-29b shows the output voltage-versus-phase difference characteristics for square-wave inputs when the VCO output frequency equals its natural frequency and it has locked onto the input signal with a -90° phase difference. Note that the opposite voltages occur for the opposite direction phase error, and the slope is positive rather than negative from –π/2 radians to +π/2 radians. When frequency lock occurs, the PLL produces a coherent frequency (ƒo = ƒi), but the phase of the incoming signal is uncertain (either ƒo leads ƒi by 90° + θ e, or vice versa.

D1 and D2

“off”

Vout

Beat frequency(ƒi – ƒo)

ƒi, ƒo, ƒi = ƒo, and fi – fo

VCO output signal

ƒo = ƒn + ∆ƒsquare wave Phase-locked loop

Θo

Phase θe = θi – θo

error

Vi sin(2π f1t + θi)

External input signal

Vd (t )

ƒ d(H

z)

t

+

0

-

Loop Operation

For the following explanation, refer to Figure 2-30.

(a)

(b)

FIGURE 2-30 PLL operation: [a] block diagram; [b] beat frequency

Loop acquisition. An external input signal [(Vi sin(2πƒit + θ i)] enters the phase comparator and mixes with the VCO output signal (a square wave with fundamental frequency ƒo). Initially, the two frequencies are not equal (ƒo ≠ ƒi) and the loop is unlocked. Because the phase comparator is a nonlinear device, the input and VCO signals mix and generate cross-product frequencies (that is, sum and difference frequencies). Therefore, the primary output frequencies from the phase comparator are the external input frequency (ƒi), the VCO output frequency (ƒo), and their sum (ƒi + ƒo) and difference (ƒi – ƒo) frequencies.

The low-pass filter (LPF) blocks the two original input frequencies and the sum frequency; thus, the input to the amplifier is simply the difference frequency (ƒ i – ƒo), sometimes called the beat frequency). The beat frequency is amplified and then applied to the input of the voltage-controlled oscillator, where it deviates the VCO by an amount proportional to its polarity and amplitude. As the VCO output frequency changes, the amplitude and frequency of the beat frequency changes proportionately. Figure 2-30b shows the beat frequency produced when the VCO is swept by the difference frequency (ƒd). After several cycles around the loop, the VCO output frequency equals the external input frequency and the loop is said to be locked. Once lock has occurred, the beat frequency at the output of the LPF is 0 Hz (a dc voltage), which is necessary to bias the VCO and keep it locked to the external input frequency. In essence, the phase comparator is a frequency comparator until frequency acquisition (zero beat) is achieved, then it becomes a phase comparator. Once the loop is locked, the difference in phase between the external input and VCO output frequencies is converted to

Phase comparatorKd(V/rad)

Low-passloop filter

(LPF)Kƒ(V/V)

Amplifier Ka(V/V)

Voltage-controlled Oscillator, fn

Kn(Hz/V)

V2

V2

V2

V2

(volt)(volt)(volt)(hertz)(rad)(volt)(volt)(volts)

hertz

radcycles/s

radcyclesrad-s

hertzrad

a bias voltage (Vd) in the phase comparator, amplified, and then fed back to the VCO to hold lock. Therefore, it is necessary that a phase error be maintained between the external input signal and the VCO output signal. The change in the VCO frequency required to achieve lock and the time required to achieve lock (acquisition or pull-in time) for a PLL with no loop filter (loop filters are explained later in this chapter) is approximately equal to 5/Kv seconds, where Kv is the open-loop gain of the PLL. Once the loop is locked, any change in he input frequency is seen as a phase error, and the comparator produces a corresponding change in its output voltage, Vd. The change in voltage is amplified and fed back to the VCO to reestablished lock. Thus, the loop dynamically adjusts itself to follow input frequency changes.

Mathematically, the output from the phase comparator is (considering only the fundamental frequency for Vo and excluding the 90° phase bias)

Vd = [V sin(2πƒot + θ o) x V sin(2πƒit + θ i)]

= cos(2πƒot + θ o – 2πƒot – θi) - cos(2πƒot + θo + 2πƒi t – θi)

where Vd = the phase detector output voltage (volts)V = VoVi (peak volts)

When ƒo = ƒi, Vd = cos(θi + θo) (2-14)

= cos θe

where θi + θo = θe (phase error). θe is the phase error required to change the VCO output frequency from ƒn to ƒi (a change = ∆ƒ) and is often called the static phase error.

Loop gain. The loop gain for a PLL is simply the product of the individual gains or transfer functions around the loop. In Figure 2-30, the open-loop gain is the product of the phase comparator gain, the low-pass filter gain, the amplifier gain, and the VCO gain. Mathematically, open-loop gain is

Kv = KdKƒKaKo (2-15)

where Kv = PLL open-loop gain (hartz per radian or s-1)Kd = phase comparator gain (volts per radian)Kƒ = low-pass filter gain (volts per volt)Ka = amplifier gain (volts per volt)Ko = VCO gain (hertz per volt)

and Kv = =

or = = x = 2π s-1

Expressed in decibels, this gives us

Kv(dB) = 20 log Kv (2-16)

From Equations 2-10, 2-13, and 2-16, the following relationships are derived:

Vd = (θe)(Kd) volts (2-17)

π2

π2

π2

Open-loop frequency response

ωv = Kv = 125.6krad/s

Closed-loop frequency response

1 rad/s

0

Gai

n (d

B)

20 log Kv102

-3 dB-6 dB/octave-20 dB/decadeω (rad/s)

Vout = (Vd)(Kƒ)(Ka) volts (2-18)

∆ƒ = (Vout)(Ko) hertz (2-19)

As previously stated, the hold-in range for a PLL is the range of input frequencies over which the PLL will remain locked. This presumes that the PLL was initially locked. The hold-in range is limited by the peak-to-peak swing in the phase comparator output voltage (∆Vd) and depends on the phase comparator, amplifier, and VCO transfer functions. From Figure 2-28c it can be seen that the phase comparator output voltage (Vd) is corrective for +π/2 radians (+90°). Beyond these limits, the polarity of Vd reverses and actually chases the VCO frequency away from the external input frequency. Therefore, the maximum phase error (θe) that is allowed is +π/2 radians and the maximum phase comparator output voltage is

+ Vd(max) = [θe(max)](Kd) (2-20a)

= + rad (Kd) (2-20b)

where + Vd(max) = maximum peak change at the phase comparator output voltage Kd = phase comparator transfer function

Consequently, the maximum change in the VCO output frequency is

+∆ƒmax = + rad (Kd)(Kƒ)(Ka)(Ko) (2-21)

where +∆ƒmax is the hold-in range (maximum peak change in VCO output frequency). Substituting Kv for KdKƒKaKo yields

+∆ƒmax = + rad (Kv) (2-22)

FIGURE 2-31 Frequency response for an uncompensated phase-locked loop

2√ (∆ƒmax)RC

Lock range is the range of frequencies over which the loop will stay locked onto the external input signal once lock has been established. Lock range is expressed in rad/s and is related to the open-loop Kv as

lock range = 2∆ƒmax = πKv

where Kv = (Kd)(Kƒ)(Ko) for a simple loop with a LPF, phase comparator, and VCO or Kv = (Kd)(Kƒ)(Ka)(Ko) for a loop with an amplifier.

The lock range in radians per second is π times the dc loop voltage gain and is independent of the LPF response. The capture range depends on the lock range and on the LPF response, so it changes

capture range =

with the type of filter used and with the filter cutoff frequency. For a simple singe-pole RC LPF, it is given by

Closed-loop frequency response. The closed-loop frequency response for an uncompensated

(unfiltered) PLL is shown in Figure 2-31. The open-loop gain of a PLL for a frequency of 1 rad/sec = Kv. The frequency response shown in Figure 2-31 is for the circuit and PLL parameters given in Example 2-2. It can be seen that the open-loop gain (Kv) at 1 rad/sec = 102 dB, and the open-loop gain equal 0 dB at the loop cutoff frequency (ωv). Also, the closed-loop gain is unity up to ωv, where it drops to -3 dB and continues to roll off at 6dB/octave (20 dB/octave). Also, ω v = Kv = 125.6 krad/s, which is the single-sided bandwidth of the uncompensated closed loop.

From Figure 2-31 it can be seen that the frequency response for an uncompensated PLL is identical to that of a single-pole (first-order) low-pass filter with a break frequency of ω c = 1 rad/s. In essence, a PLL is a low-pass tracking filter that follows input frequency changes that fall within a bandwidth equal to +Kv.

If additional bandlimiting is required, a low-pass filter can be added between the phase comparator and amplifier as shown in Figure 2-30. This filter can be either a single- or multiple-pole filter. Figure 2-32 shows the loop frequency response for a simple single-pole RC filter with a cutoff frequency of ωc = 100 rad/s. The frequency response follows that of Figure 2-31 up to the loop filter break frequency; then the response rolls off at 12 dB/octave (40 dB/decade). As a result, the compensated unity-gain frequency (ωc) is reduced to approximately +3.5 krad/s.