PHASE LOCKED LOOP PHASE LOCKED LOOP SIMULATIONSSIMULATIONS

By, By, R.Vikram R.Vikram

Reddy(0104445)Reddy(0104445)

Talk OutlineTalk Outline•HistoryHistory

•IntroductionIntroduction

•PLL BasicsPLL Basics

•PLL TypesPLL Types

•Loop ComponentsLoop Components

-Phase Detectors-Phase Detectors

-Voltage controlled Oscillators-Voltage controlled Oscillators

-Loop Filters-Loop Filters

•ApplicationsApplications

History:History:• Coincides with invention of “coherent

communication” (DeBellescize, 1932).• The earliest widespread use of PLLs was to

the horizontal and vertical sweeps used in television, where a continuous clocking signal had to be synchronized with a periodic synch pulse.

• PLLs were critical to development of color television

• The first PLL IC arrived around 1965. This created an explosion in the use of PLLs.

PLLs TodayPLLs Today

– PLLs in every cell phone, television, radio, pager, computer, all telephony, ...

– The most prolific feedback system built by engineers.

– At low end: all software PLLs implement entire PLL functionality on sampled data.

– At high end: optical PLLs used in clock recovery for 160 Gbps data (OFC 2002).

PLL BasicsPLL Basics

• Definition:Definition:

A phase-locked loop (PLL) is an A phase-locked loop (PLL) is an electronic circuit with a voltage- or electronic circuit with a voltage- or current-driven oscillator that is current-driven oscillator that is constantly adjusted to match in constantly adjusted to match in phase (and thus lock on) the phase (and thus lock on) the frequency of an input signal. frequency of an input signal.

Basic idea of a Phase Basic idea of a Phase Locked LoopLocked Loop

Components Of PLLComponents Of PLL

• Phase Detector (PD):Phase Detector (PD):A nonlinear A nonlinear device whose output contains the device whose output contains the phase difference between the two phase difference between the two oscillating input signals.oscillating input signals.

• Voltage controlled oscillator Voltage controlled oscillator (VCO):(VCO): Another nonlinear device Another nonlinear device which produces oscillations whose which produces oscillations whose frequency is controlled by a lower frequency is controlled by a lower frequency input voltage.frequency input voltage.

• Loop filterLoop filter

•General sinusoid at reference input can be written as:

Vin=Einsin(ωt)…….(1)

•Assume VCO output signal is Vosc=Eoscsin(ωt- Ød+90)

=Eosccos(ωot - Ød)……(2)

•Phase Detector output: Vpd=KmVinVosc

where Km is the multiplication constant

• VVpdpd=K=KmmEEininEEoscoscsin(sin(ωωt)cos(t)cos(ωωt-Øt-Ødd))

• Using the familiar trigonometric identity in Using the familiar trigonometric identity in terms of the PLL:terms of the PLL:

VVpdpd=0.5K=0.5KmmEEininEEoscosc[sin(Ø[sin(Ødd) + sin(2) + sin(2ωωt-Øt-Ødd)])]

• The output of the low pass filter :The output of the low pass filter :

VVcntlcntl=0.5K=0.5KlplpKKmmEEininEEoscoscsin(Øsin(Ødd))

For small ØFor small Ødd

VVcntlcntl=0.5K=0.5KlplpKKmmEEininEEoscoscØØdd

How A PLL Works:How A PLL Works:

Capture Range:Capture Range:

• The maximum difference between The maximum difference between the input signals frequency and the input signals frequency and oscillators free running frequency oscillators free running frequency where lock can eventually be where lock can eventually be attained is defined as the capture attained is defined as the capture range.range.

• The Phenomenon of The Phenomenon of “Beating”.“Beating”.

Lock Range:Lock Range:• The maximum frequency excursions over which the The maximum frequency excursions over which the

output remains locked with the input is called the output remains locked with the input is called the lock range.lock range.

• The maximum output of the low pass filter is given The maximum output of the low pass filter is given byby

VVcntl-maxcntl-max=0.5 K=0.5 KlplpKKmmEEininEEoscosc

when Øwhen Ødd=90.=90. Therefore lock range is given byTherefore lock range is given by

ωωlck=lck=KKoscoscVVcntl-max.cntl-max.

Types Of PLLsTypes Of PLLs

• Analog or Linear PLL (LPLL)Analog or Linear PLL (LPLL)

• • Digital PLL (DPLL)Digital PLL (DPLL)

• • All digital PLL (ADPLL)All digital PLL (ADPLL)

LPLLLPLL

• The LPLL (Best) or analog PLL is the The LPLL (Best) or analog PLL is the classical form of PLL. All components classical form of PLL. All components in the LPLL operate in the in the LPLL operate in the continuous-time domain. continuous-time domain.

LPLLLPLL

• The phase detector is typically some The phase detector is typically some form of analog multiplier.form of analog multiplier.

• The phase error function is of the formThe phase error function is of the form

φ(t) = KmK1Asin [θ(t) − θ^(t)]φ(t) = KmK1Asin [θ(t) − θ^(t)]

≈ ≈ KD[θ(t) − θ^(t)]KD[θ(t) − θ^(t)]

• The loop filter may be active or The loop filter may be active or passive, but it typically results in the passive, but it typically results in the loop being either first-order or second-loop being either first-order or second-order.order.

• The design/analysis of the loop filter The design/analysis of the loop filter makes use of the Laplace transform.makes use of the Laplace transform.

DPLLDPLL

The digital PLL is just an analog PLL The digital PLL is just an analog PLL with a digital phase detector.with a digital phase detector.

• The DPLL is a hybrid systemThe DPLL is a hybrid system

• The DPLL is very popular in The DPLL is very popular in synthesizer synthesizer

applicationsapplications

In the below figure the optional digital In the below figure the optional digital divider, and variations on it, are used divider, and variations on it, are used in frequency synthesis applications.in frequency synthesis applications.

• Popular types of digital phase detectors Popular types of digital phase detectors include:include:

– – Exclusive or gate (EXOR)Exclusive or gate (EXOR)

– – Edge-triggered JK-flip flopEdge-triggered JK-flip flop

– – Phase frequency detector (PFD)Phase frequency detector (PFD)

ADPLLADPLL

• The all-digital PLL (classical all-digital) is The all-digital PLL (classical all-digital) is distinctly different from the other two distinctly different from the other two PLLsPLLs

• The ADPLL is a digital loop in two senses:The ADPLL is a digital loop in two senses:

– – All digital componentsAll digital components

– – All digital (discrete-time) signalsAll digital (discrete-time) signals

• There are many ADPLL building blocks, There are many ADPLL building blocks, and many variations on putting them and many variations on putting them together.together.

ADPLLADPLL

• The VCO is replaced by a Digitally The VCO is replaced by a Digitally Controlled Oscillator (DCO) or also Controlled Oscillator (DCO) or also called a Numerically Controlled called a Numerically Controlled Oscillator (NCO)Oscillator (NCO)

LOOP COMPONENTSLOOP COMPONENTS

Phase DetectorPhase Detector

− A phase detector is a circuit that A phase detector is a circuit that normally has an output voltage with an normally has an output voltage with an average value proportional to the phase average value proportional to the phase difference between the input signal and difference between the input signal and output of VCO.output of VCO.

Vpd=Kp∆Vpd=Kp∆ФФ

− Phase detectors can be a simple EX-OR Phase detectors can be a simple EX-OR gate, a sample and hold, an analog gate, a sample and hold, an analog multiplier or a combination of D-flip flops.multiplier or a combination of D-flip flops.

XORXOR−The simplest phase detector is xor The simplest phase detector is xor

−An exclusive OR gate gives a high output An exclusive OR gate gives a high output when the signals are of opposite sign and a when the signals are of opposite sign and a low output when they are of the same sign.low output when they are of the same sign.

Phase Frequency DetectorPhase Frequency Detector

−It is a combination of tri state phase It is a combination of tri state phase frequency detector and a charge frequency detector and a charge pump.pump.

Sample and Hold Phase Sample and Hold Phase DetectorDetector

−A sample and hold circuit samples an A sample and hold circuit samples an input signal and holds on to its last input signal and holds on to its last sampled value until the input is sampled sampled value until the input is sampled again.again.

AnalysisAnalysis

Design Circuit:XOR (TTL Logic) gate:

EXCLUSIVE OR GATEVCC 4 0 5VVINA 1 0 PULSE(0V 5V 0US 0.1US 0.1US 2US 5US)VINB 9 0 PULSE(0V 5V 0US 0.1US 0.1US 3US 5US)

RBA 4 3 4KRBB 4 8 4K RCSA 4 5 1.9KRCSB 4 11 1.9KRSDA 7 0 1.2KRSDB 12 0 1.2KRCX 4 14 3KRC 4 15 1.6KRCP 4 16 120RX 18 0 1K

DCA 0 1 DIODEDCB 0 9 DIODEDSA 5 6 DIODEDSB 11 13 DIODEDX 17 19 DIODE

Q1A 2 3 1 QMQ1B 10 8 9 QMQS2A 5 2 7 QMQS2B 11 10 12 QMQSDA 6 7 0 QMQSDB 13 12 0 QMQX1 14 13 6 QMQX2 14 6 13 QMQS 15 14 18 QMQP 16 15 17 QMQO 19 18 0 QM

.MODEL DIODE D (RS=40 TT=0.1NS)

.MODEL QM NPN (IS=1E-14 BF=50 BR=1 RB=70 RC=4 TF=0.1NS TR=1NS)

.TRAN 0.1US 15US

.PLOT V(1) V(9) V(19)

.END

Voltage Controlled Oscillators Voltage Controlled Oscillators (VCOs)(VCOs)

− The function of a VCO is to generate a stable The function of a VCO is to generate a stable and periodic waveform whose frequency can and periodic waveform whose frequency can be varied with the applied control voltage.be varied with the applied control voltage.

− The actual clock from PLL is the VCO The actual clock from PLL is the VCO output.output.

− VCO’s frequency is modulated by the input VCO’s frequency is modulated by the input voltagevoltage

Classification of VCOClassification of VCO

Depending on the type of output Depending on the type of output waveform, VCOs are classified aswaveform, VCOs are classified as

− Harmonic OscillatorsHarmonic Oscillators

−Relaxation OscillatorsRelaxation Oscillators

Some of the commonly used VCOsSome of the commonly used VCOs

--Ring Oscillators:Ring Oscillators:Common in monolithic topologies and it uses odd Common in monolithic topologies and it uses odd number of inverters connected in feedback loop.number of inverters connected in feedback loop.

-Other forms of VCOs, such as crytal oscillators and -Other forms of VCOs, such as crytal oscillators and resonant oscillators essentially run on the same resonant oscillators essentially run on the same principleprinciple

VCO Circuit Design:VCO Circuit Design:−A simple design of VCO consists of a collector A simple design of VCO consists of a collector

coupled astable multivibrator using n-p-n transistor coupled astable multivibrator using n-p-n transistor with a control voltage. with a control voltage.

Step 1Step 1

Step 2

f=1/2RCln (1+Vcc/V)

Step 3:

*Voltage controlled Oscillator*Voltage controlled OscillatorVCC 6 0 DC 5VVCC 6 0 DC 5VVI 7 0 PULSE(0 5 0US 30US 30US 30US 40US)VI 7 0 PULSE(0 5 0US 30US 30US 30US 40US)RC1 6 1 1KRC1 6 1 1KRC2 6 2 1KRC2 6 2 1KRE1 7 10 1KRE1 7 10 1KRE2 7 11 1KRE2 7 11 1KR3 7 8 2KR3 7 8 2KR4 7 9 2KR4 7 9 2KR5 8 0 4.7KR5 8 0 4.7KR6 9 0 4.7KR6 9 0 4.7KC1 1 4 150PFC1 1 4 150PFC2 2 3 150PFC2 2 3 150PFQ1 1 3 0 QMQ1 1 3 0 QMQ2 2 4 0 QMQ2 2 4 0 QM.MODEL QM NPN (IS=2E-16 BF=50 BR=1 RB=5 RC=1 RE=0 TF=0.2NS TR=5NS).MODEL QM NPN (IS=2E-16 BF=50 BR=1 RB=5 RC=1 RE=0 TF=0.2NS TR=5NS)Q3 3 8 10 QM1Q3 3 8 10 QM1Q4 4 9 11 QM1Q4 4 9 11 QM1.MODEL QM1 PNP (IS=2E-16 BF=100 BR=1 RB=5 RC=1 RE=0 TF=0.2NS TR=5NS).MODEL QM1 PNP (IS=2E-16 BF=100 BR=1 RB=5 RC=1 RE=0 TF=0.2NS TR=5NS).IC V(1)=0 V(3)=0.IC V(1)=0 V(3)=0.TRAN 0.1US 90US.TRAN 0.1US 90US.PLOT TRAN V(2) V(7).PLOT TRAN V(2) V(7).END.END

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0

Time (us)

0 .0

0 .5

1 .0

1 .5

2 .0

2 .5

3 .0

3 .5

4 .0

4 .5

5 .0 Vo

ltage

(V)

v (7 )

astblmul22

0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0

Time (us)

0 .0

0 .5

1 .0

1 .5

2 .0

2 .5

3 .0

3 .5

4 .0

4 .5

5 .0

Volta

ge (V

)

v (2 )

astblmul22

Loop filter:Loop filter:− The loop filter may be active or passive, but it

typically results.− In the loop being either first-order or second-

order.− A 1st order filter having a low frequency pole and

high frequency zero is recommended.−Loop filter system functions, F(s), include:

Filter Type Filter F(s)

perfect integrator 1+sτ2/sτ1 imperfect integrator 1+sτ2/1+sτ1 lag or low pass 1/1+sτ

Filter DesignFilter Design

−Design circuit is a simple RC low-pass filter Design circuit is a simple RC low-pass filter which can extract the average value from which can extract the average value from the output of the phase detector.the output of the phase detector.

−This average value is used to drive the VCOThis average value is used to drive the VCO

C1

R1

R2

Hlp(s)=1+sR2C1/1+s(R1+R2)C1

in out

low pass filterR1 1 2 86KC1 2 3 5PFR2 3 0 2KVIN 1 0 PULSE(0V 9V 0US 0US 0US 2US 5US).TRAN 0.01US 15US.PLOT TRAN V(2) V(1) .END

0 5 1 0 1 5 2 0 2 5

Time (us)

0 .0

0 .5

1 .0

1 .5

2 .0

2 .5

3 .0

3 .5

4 .0

4 .5

5 .0

Vol

tage

(V

)

v (1 )

T-Spice1

0 5 1 0 1 5 2 0 2 5

Time (us)

0 .0

0 .5

1 .0

1 .5

2 .0

2 .5

3 .0

3 .5

Vol

tage

(V

)

v (2 )

T-Spice1

PLL APPLICATIONSPLL APPLICATIONS

• The earliest widespread use of PLLs was for the horizontal and vertical sweeps used in televisions.• PLLs were critical to development of color televisions also. PLLs today:–Cell phones, televisions, radios, pagers, computers, all telephony,

– At low end: all software PLLs implement entire PLL functionality on sampled data.

– At high end: optical PLLs used in clock recovery for 160 Gbps data

Phase-locked loops are widely used for synchronization purposes

• Space communications for coherent carrier tracking and threshold extension

• Bit and symbol synchronization

They are also used for:

• Demodulation of frequency modulated signals

•To synthesize new frequencies which are multiples of a reference frequency, with the same stability as the reference frequency.

1. Deskewing • the clock must be received and amplified

• finite delay dependent on process,temperature and voltage between detected clock edge and the received data

• delay limits the frequency at which data can be sent

• deskew PLL on the receiver side phase-matches the clock at each data flip-flop to the received clock.

2. Clock generation

• multiplies lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor that operate at Gigahertz

3. Spread spectrum

• All electronic systems emit some unwanted radio frequency energy • limits on this emitted energy and any interference caused • spreading the energy over a larger portion of the spectrum

4. Jitter and noise reduction

•reference and feedback clock edges can be brought into very close alignment •phase and frequency of generated clock is unaffected by rapid changes in voltages of the power supply lines and of the substrate on which the PLL circuits are fabricated

1. Carrier Recovery

• General block diagram of frequency recovery from a modulated signal.• When carrier has strong component in signal spectrum, PLL can lock.• When carrier is missing from signal spectrum, PLL must be preceded by a nonlinear element.

2. Costas Loop

• A Costas loop can both recover the carrier and demodulate the data from a signal.• If there were no modulation, the upper arm is simply a PLL lock to a carrier. • The effect of the lower arm of the loop is to lock to the modulation and cancel it out of the upper arm of the loop.• Does the same thing as squaring loop, but down converts signal to baseband & does filtering there.

3. Clock distribution

4. Frequency Synthesis

In wireless applications, frequency synthesizers provide local oscillators ability for up and down conversion of modulated signals

A basic PLL synthesizer

5. Disk Drive Control

Amplitude encoded position error signal (PES) in a hard disk.

PLLs are used to time the acquisitionof the readback signal.