physical design for nanometer ics -...
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EEE5026; 943/U0280
Physical Design for Nanometer ICs
Yao-Wen Chang
[email protected]://cc.ee.ntu.edu.tw/~ywchang
Graduate Institute of Electronics EngineeringDepartment of Electrical Engineering
National Taiwan UniversitySpring 2018
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Y.-W. ChangUnit 1 2
Administrative MattersTime/Location: Thursdays 2:20 pm--5:30 pm; BL-114 Instructor: Yao-Wen ChangE-mail: [email protected]: http://cc.ee.ntu.edu.tw/~ywchangOffice: BL-428. (Tel) 3366-3556; (Fax) 2364-1972Office Hours: Wednesdays 4-5pm; other times by appointmentTeaching Assistant: Yu-Sheng Lu ([email protected]); office
hours: 12:30-1:30pm, WednesdaysPrerequisites: data structures, algorithms, and logic designRequired Text: Either of the following two books:
Wang, Chang, and Cheng (Ed.), Electronic Design Automation: Synthesis, Verification, and Test, Morgan Kaufmann, 2009
Sait and Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific Publishing Co., 1999
References: Selected reading materials from recent publications
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Y.-W. ChangUnit 1 3
Teaching AssistantYu-Sheng Lu Email: [email protected]: BL-406; Tel: 3366-3700 # 6406Office Hours: 12:30-1:30pm, Wednesdays.2nd-year Ph.D. student
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Y.-W. ChangUnit 1 4
Course ObjectivesStudy techniques/algorithms for physical design
(converting a circuit description into a geometric description) and their comparisons
Study nanometer process/electrical effects and their impacts on the development of physical design tools
Study problem-solving (-finding) techniques!!!
S1S2S3S4S5
P1 P2 P3 P4 P5 P6 problem
solution
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Y.-W. ChangUnit 1 5
Course ContentsVLSI design flow/styles and technology roadmapPhysical design processes
Partitioning Floorplanning Placement Routing (global, detailed, clock, and power/ground routing) Post-layout optimization
Timing: timing modeling, performance-driven designSignal/power integrity: crosstalk, IR dropDesign for manufacturability
Process variation, optical proximity correction (OPC), chemical mechanical polishing (CMP), multiple pattering, e-beam, extreme ultraviolet (EUV), directed self-assembly (DSA), nanowire, etc.
Design for reliability: antenna effect, redundant via, electromigration, thermal, etc.
Machine learning based layout optimization
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Y.-W. ChangUnit 1 6
Grading PolicyGrading:
Homework assignments + quizzes: 25% Programming assignments + lab: 25% One in-class open-book, open-note exam: 30% (June 28) Final project + presentation + demo: 20% (due June 21)
A 1-page project proposal is due in-class on May 24 Could be research work, implementation, and/or literature
survey Default project: Problem B, C, or E of the 2018 IC/CAD Contest at
http://iccad-contest.org/tw/ (E for domestic undergraduate students) Teamwork is permitted (1--3 persons; preferably 2 persons)
Bonus for class participationHomework: 30% per day penalty for late submission WWW: http://cc.ee.ntu.edu.tw/~ywchang/Courses/PD/pd.htmlAcademic Honesty: Avoiding cheating at all cost
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Y.-W. ChangUnit 1 7
2018 CAD Contest @ ICCADDefault project: Problem B, C, or E of the 2018 IC/CAD
Contest at http://iccad-contest.org/tw/Teamwork is permitted (1--3 persons; preferably 2
persons)
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Y.-W. ChangUnit 1 8
Unit 1: Introduction Course contents:
Introduction to VLSI design flow/styles Introduction to physical design automation Semiconductor technology roadmap
Readings W&C&C: Chapter 1 S&Y: Chapter 1
fabricationphysicaldesign
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Y.-W. ChangUnit 1 9
IC Design & Manufacturing Process
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Y.-W. ChangUnit 1 10
IC Design & Manufacturing Process (contd)
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Y.-W. ChangUnit 1 11
From Wafer to Chip
8-inch vs. 1-inch ignot
Wafer dicing
Wirebonding
chips
Apple A11 die (iPhone 8)TSMC 10nm FinFET;
4.3B transistors; 87.66 mm2
12-inch wafer
18-inch wafer
2, 4, 6, 8-inch wafers
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Y.-W. Chang
Die, Package, and BoardApple A9 die for iPhone 6s (1.85GHz; 5B+ transistors)
TSMC16nm FinFET
104.5 mm2
Samsung14nm FinFET
96 mm2packages
boardspackages
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Y.-W. ChangUnit 1 13
IC Design Considerations
Several conflicting considerations: Complexity: large number of devices/transistors Power: low-power consumption Performance: high-speed requirements Cost: die area, packaging, testing, etc. Time-to-market: about a 15% gain for early birds Others: manufacturability, reliability, testability, etc.
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Y.-W. ChangUnit 1 14
4004 80386 PentiumPro8086 Pentium 4
Intel uP
Logic capacity doubles per IC at a regular interval (say, 18 months). G. Moore: Logic capacity doubles per IC every two years (1975). D. House: Computer performance doubles every 18 months (1975)
Moores Law: Driving Technology Advances
4Gb
Itanium 2
Itanium 2
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Y.-W. ChangUnit 1 15
Design Productivity Crisis
Human factors may limit design more than technology.Keys to solve the productivity crisis: CAD (tool &
methodology), hierarchical design, abstraction, IP reuse, platform-based design, etc.
1980 1985 1990 2000 20101995 2005
0.01M
0.1M
1M
10M
100M
1,000M
10,000M
Logic transistors per chip 0.1K1K
10K
100K
1,000K
10,000K
100,000KProductivity in transistors
per staff-month21%/yr compound
productivity growth rate
58%/yr compound complexity growth rate Complexity limiter
2015
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Y.-W. ChangUnit 1 16
Old (1997) Technology Roadmap for Semiconductors
Source: International Technology Roadmap for Semiconductors (easier to see the past & trend with the older version; for more recent update, see http://www.itrs2.net/).
Deep submicron technology: node (feature size) < 0.25 m. Nanometer Technology: node < 100 nm. 14/16 nm technology was in production in 2015; 10 nm in 2016/2017
(5nm in 2020 by EUV?)
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Y.-W. ChangUnit 1 17
Nanometer Design ChallengesApple A11 (iPhone 8): technology node: 10 nm FinFET,
P frequency 2.39 GHz, die size 87.66 mm2,transistor count per chip 4.3B, wiring level 10+ layers, supply voltage < 1.0 V, power consumption < 16 W (?) Feature size : sub-wavelength lithography (impacts of
process variation)? reliability? noise? wire coupling? Frequency , dimension : interconnect delay?
electromagnetic field effects? timing closure? Chip complexity : large-scale system design
methodology? Supply voltage : signal integrity (noise, IR drop, etc)? Wiring level : manufacturability? yield? 3D layout? Power consumption/density : power & thermal issues?
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Y.-W. ChangUnit 1 18
Design Complexity Increases Dramatically!!Mixed-size Placement
Routing & interconnect
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Y.-W. ChangUnit 1 19
High IC Complexity
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Y.-W. Chang
Wat
ts/c
m2
1
10
100
1000
i386i486
Pentium Pentium Pro
Pentium IIPentium IIIHot plate
RocketNozzleRocketNozzleNuclear ReactorNuclear Reactor
Fred Pollack, New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies, 1999 Micro32 Conference keynote. Courtesy Avi Mendelson, Intel.
Pentium 4
Power Is a Key Limiting Factor for IC Design!
Power doubles every 4 years5-year projection: 200W total, 125 W/cm2 !
Power density increases exponentially!
Power & Performance trade-off!!
Itanium 2Itanium 2-DC
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Y.-W. ChangUnit 1 21
Interconnect Dominates Circuit Performance!!
10
20
30
40
50
60
70
650 500 350 250 180 150 100 70 (nm)
Worst-caseinterconnectdelay dueto crosstalk
Interconnectdelay
Technology Node
Del
ay (p
s)
Gate delay
CWCSIn 0.18m wire-to-wire capacitance dominates (CW>>CS)
Source: Synopsys
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Y.-W. Chang
Manufacturing with Optical LithographyPatterns on a mask are transferred onto a wafer
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Light source
Lens
Lens
Mask
Wafer
Illumination
Projection
Immersion(water)
R = k1 / NAR: resolution; k1: resolution constant (>= 0.25); : wavelength
NA: numerical aperture = f(lens, refractive index)
0.25 * 193 nm / 1.35 = 36 nm
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Y.-W. Chang
Sub-Wavelength Lithography GapSub-wavelength lithography: use light of larger
wavelength (193nm) to print features of smaller sizes
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[S. Borkar, MICRO04]
EUVE-beam
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Y.-W. Chang
Technology Roadmap [Aitken, 2014]
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1975 1985 1995 2005 2015 2025
Log
(com
plex
ity) Interconnect
Patterning
Transistors
PMOS NMOSPlanar CMOS
StrainHKMG
FinFET
HNW
III-V
VNW
eNVM NEMS CNT
LE, ~LE,