pic design across platforms - 7 pennies · design across platforms footprint spectra platform 2 mm...
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PIC design across PIC design across platformsplatforms
Ronald BroekeRonald BroekeBright PhotonicsBright Photonics
OUTLINEOUTLINE
Introduction PIC applications & designs MPW Materials & platforms Design modules PICs in Phoxtrot
multi-wavelength Rxmulti-wavelength Txfiber optical sensing
radio over fibermux/demuxmodulators
switches(C)WDM
QAMAWGFTTH
BOTDRO-CDMA
amplifiersring-lasers
90-deg hybrids FM-IM conversion
MZI interferometerswavelength conversion
power splitters/combiners
Design House for Photonics ICs
Ap
plic
atio
n d
riv e
n d
esig
n
Custom PIC design Design libraries MPW & custom fab Prototyping
InP Silicon (SOI) SiN/Triplex Silica/PLC Polymer
PIC design across PIC design across platformsplatforms
Ronald BroekeRonald Broeke
Session: COMPONENTS & SYSTEMS FOR DATA CENTERS
PhoxTroT 3rd Symposium on Optical Interconnect in Data Centers
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PICs, a plethora of applications
PIC:Photonic Integrated CircuitHorizontal business model provides commercial access to ASPIC technology:
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Design for productsDesign for products
Sensor PICs for spectrometers, scanners, airplanes, ...
World record: atto-meter sensing Design for package Flexible prototyping
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Hybrid packagingHybrid packaging
BRIGHT photonics, LioniX, SMART photonics, PhoeniX Software, VLC photonics , XiO Photonics
InPTriplex (SiN)
Hybrid packaging: Best of 2 worlds
carrier substrate
InP chip
TriPleX chip
fiber array
fiber feed through
wire bonds
electrical connections
TEC
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Application example: 100 channel InP Rx (5 Application example: 100 channel InP Rx (5 THz)THz)
InP wafer (HHI)
GDS + photo
Measured response
Single AWG, sim vs meas.
Dark current PD
99% < 3 nA
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100 channel receiver: design100 channel receiver: design
Cascading principle: spectra Simulated cascade 1x10x10
Options for a 1x100 demux across 100 nm
Simulated 1x100
drawn to scale
1x
1x 10x
12 mmA
B
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Application example: SOI beam Application example: SOI beam formerformer
Re-circulating AWG loop
Integrated step-wise true time delay for beam formers in-home.
lambda design measured
nm ps ps
1552.93 0 0
1549.72 2.9 2.9
1546.12 5.7 5.7
1538.58 11.4 10.7
1534.25 14.3 13.4
1529.16 17.1 16.5
GDS + photo Performance
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Manufacturing PICsManufacturing PICs
InP
Silicon
SiN
InP ~10 MPW/ySilicon ~10 MPW/ySiN ~2 MPW/y ~2 MPW runs per month!
MPW = multi project waferIn a MPW a foundry fabricates PICs
Custom foundryCustom foundry MPW services in EuropeMPW services in Europe
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MPW prototyping timelineMPW prototyping timeline
Fabrication in FoundryDesign
Sub
missio
n
Time
Testing+Packaging
3-6 months1-2 months
➔ Timing depends on foundry and MPW schedule➔ Align with packaging during design➔ Custom fabrication faster but costly
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Material platformsMaterial platforms… a waveguide comparison… a waveguide comparison
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Chip design based on functional Chip design based on functional BBsBBs
AWG-demux
couplers
ring filters
phase modulator
amplitude modulator
WDM add-drop
picosecond pulse laser
multiwavelength lasers
tunable DBR lasers
tunable ring filters
true-time delay
gain or non-linear mixing
Application Functional BB Technological BB MaterialA. Passives B. Phase control C. Amplification
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Comparison of platformsComparison of platforms
RF: Tx, Rx All-in-one
Data centers4x25 GbitHigh volume
High quality passivesDemux. splitters
ModulatorsCheap hybrid
True-time delayMicrowave photonics
Telecom Txlow voltage RF modulators
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Supported MPW Foundries (design + modules)Supported MPW Foundries (design + modules)
+ many custom foundries
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Design time lineDesign time line
Physical level design Interconnect BBs
layout time
A. Design BBs from physics up without IP-blocks
B. Re-use BBs + IP-blocks
BBs
layout timeBBs
PDK
PDKPDK
design module
Time gained
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MPW prototyping timelineMPW prototyping timeline
Fabrication in FoundryDesign
Sub
missio
n
Time
Testing+Packaging
3-6 months1-2 months
➔ Timing depends on foundry and MPW schedule➔ Align with packaging during design➔ Custom fabrication faster but costly
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Multi-platform design modulesMulti-platform design modules
AWG MMI Interconnects Tapers Etc.
Foundry
Logic
Interface
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Design modulesDesign modulesDesign new BB, extend PDK Available for external usersRe-use default BBsAdd design functionality & design speed
AW
G
MM
I
Tap
er
Bu
s
Lase
r
Dio
des
Material
Slab
Control
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BB material libraryBB material library
“Material” underpins BB modules Multiple processes / Foundry Multiple Index models / process
M
EIM
Material library
Foundry-1
2D
Mea
sure
d2 N. . .
Layers (CS)Indices
process-1 2 . . .
mat
AWGMMI
TaperBus
LaserDiodes
Material
BrightModules
Slab
M
EIM
Foundry-1
2D
2 N. . .
Layers (CS)Indices
process-1 2 . . .
mat
overview
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AWG design (Mux - deMux)AWG design (Mux - deMux)
BrightAWG (GUI PhoeniX OptoDesigner)
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Design for manufacturingDesign for manufacturing
Logic to GDS DRC Underetch correction Multiple GDS layers Grid adaptation
Logic GDS
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Design across platformsDesign across platforms
Footprint
Spectra
Platform
2 mm 2 mm1.4 mm
BB-module
lambda central = 1.55 umchannel spacing = 0.8 nmFSR = 3.2 nm#in x #out = 1 x 4
HHI, InPLioniX, SiN IMEC, SOI
User application specs (AWG example)
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MMI design (power splitters)MMI design (power splitters)
BrightMMI (GUI PhoeniX OptoDesigner)
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MMI librariesMMI libraries
100 um
2x3
1x5
2x3 asym.
2x4, 90deg-hybrid
1x4
2x2, 72/28
2x4, 85/15
2x2
1x2
1x3
3x3
PDK extension for MMIs: Initialized scripted MMIs Predefined MMIs (GDS) Templates with MMI rules
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Bright-BB circuit simulation in AspicBright-BB circuit simulation in Aspic
BrightAWG in
GUI Aspic Circuit simulator
Via S-matrix
Symbolic AWG
parameter block
Spectra in Aspic GUI
BBs
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Bright-BB circuit simulation in VIP-photonicsBright-BB circuit simulation in VIP-photonics
Spectra in GUI100 channels cw
Spectra in GUI4 channels modulated at 5 GHz
Circuit in VPI:1+10 AWGs + 100 PDs
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PICs and optical routing in PhoxtrotPICs and optical routing in PhoxtrotMaterials: InP, SOI, Polymer, glass
PICs (SOI, InP): Linecard OAC,
Optical interconnects(polymer, glass): Linecard | SM OBP | SM, MM
Functions: Mux, deMux Power plittting Routing Tx (VCSEL), Rx (PD)EU-FP7-Phoxtrot
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SOI, Monolithic Photonic-Electronic SOI, Monolithic Photonic-Electronic integrationintegrationChallenges● Tooling interfaces
3D CAD tools Electronics design tools Photonics design tools
● Routing and element placement● DRC
Photonics level integration: Use electronics GDS as ref. in photonics design (vias, metal) Integrate routing electrical elements BB in library Add DRC on electronic GDS layers
Optical and electronic BB libraryOpto-electonic SOI chip
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Thank You
Ronald.Broeke @ BrightPhotonics.euInfo @ BrightPhotonics.euwww.brightphotonics.eu