pic12c508 and adf4113

A December 11th, 2002

PIC12C508A

& THE ADF4110 FAMILY OF PLL SYNTHESIZERS

Author : Pauline LEMORE.

Index 1. Introduction p.1 2. The ADF 4110 Family of PLL synthesizer p.2 3. The PIC12C508A p.9 4. The software code p.10 4.1. The bit banging protocol p.10 4.2. Code Architecture p.11 4.2.1. Configuration bits p.11 4.2.2. Constants and variables definition p.12 4.2.2.1. Outputs p.12 4.2.2.2. Data registers to transmit p.12 4.2.2.3 Variables p.13 4.2.3. Processor initialization p.13 4.2.4. Data transmission p.15 4.2.5. Sub-routines p.15 5. Timings p.17 6. Schematic p.19 7. How to use this software code p.23

7.1. Programming environment p.23 7.2. How to get the wanted fixed frequency p.23

8. Software code p.25

PIC12C508A & the ADF4110 Family of PLL synthesizers a

December 11th

, 2002 1

1 Introduction:

Presently, it is possible to program any frequency from the 411X evalboard, using the evalboard software. Data is sent through a serial port from the PC to the board. The objective of this project is to use a micro-controller, instead of the software and serial port, to configure the PLL synthesizer. The objective is to have one fixed frequency, the value of which is programmed into the micro-controller. So, when the board is powered up, the micro-controller sends all configuration data to the synthesizer, which will lock the PLL at the desired frequency. Although the 411X evalboard could be issued with a pre-programmed micro-controller, the serial connection will be still usable. Thus, the customer could choose to get any frequency by the software evalboard and the serial port, or use the micro-controller, and have a fixed frequency. The advantages of using the board with the PIC are mainly the possibility to choose the fixed frequency by changing its value into the software code and the simplicity of its use, just turn on the board and the PLL is locked.


December 11th

, 2002 2

2 The ADF4110 Family of PLL synthesizers:

This family of PLL synthesizers can deliver maximum output frequencies between 550 MHz and 4 GHz. To get a stable frequency, it is necessary to lock the PLL by programming it. To do that, 4 latches have to be configured. They are:

- the Reference counter latch, which selects the REFin frequency - the N counter latch, where the A and B counters are - the Function latch and the Initialization latch, both similar, and where the prescaler,

the current and the muxout can be set.

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

ControlBits14-Bit Reference CounterTest

Mode Bits

Lo

ck Detect

Precisio

n

Reserved

DB21DB22DB23

DLY SYNC

AntiBacklash

Width

DL

Y

SY

NC


C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

ControlBits6-Bit A Counter13-Bit B Counter

DB21

Reserved

DB22DB23

CP

Gain

G1


C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2

ControlBits

Co

un

terR

eset

Po

wer

Do

wn

1

MUXOUTControl

PH

AS

ED

ET

EC

TO

RP

OL

AR

ITY

CP

3-State

Po

wer

Do

wn

2

CurrentSetting

1Prescaler

ValueTimer Counter

Control

CPI3CPI4

DB21

CurrentSetting

2

TC3 TC2 TC1

DB22DB23

Fastlo

ckE

nab

le

FastL

ock

Mo

de

F4F5



ControlBits

Co

un

terR

eset

Po

wer

Do

wn

1

MUXOUTControl

CP

3-State

Po

wer

Do

wn

2

CurrentSetting

1Prescaler

ValueTimer Counter

Control

CPI3CPI4

DB21

CurrentSetting

2

TC3 TC2 TC1

DB22DB23

Fastlo

ckE

nab

le

FastL

ock

Mo

de

F4F5

Reference Counter Latch

N Counter Latch

Function Latch

Initialisation Latch

PH

AS

ED

ET

EC

TO

RP

OL

AR

ITY


December 11th

, 2002 3

They are all 24 bits and are programmed via the SPI port on the ADF411X chip. The programming order is the Initialization latch, then the Function latch, the N counter latch and the Reference counter latch. To help, below is the functional block diagram of the ADF4110 Family:

REFIN14-BIT

R COUNTER

CLK

DATALE

PRESCALERP/P+1

24-BITINPUT REGISTER

FUNCTIONLATCH

CHARGEPUMP

MUX

MUXOUT

ADF4110/1/2/3

RFINA

CP

AVDD DVDD VP

CE AGND DGND

CPGND

RFINB

+

-

RSET

R COUNTERLATCH

A, B COUNTERLATCH

13-BITB COUNTER

6-BITA COUNTER

22

14

REFERENCE

LOCK DETECT CURRENTSETTING 1

CPI3 CPI2 CPI1

M3 M2 M1

LOAD

LOAD

19

13

6

CURRENTSETTING 2

CPI6 CPI5 CPI4

SDOUT

SDOUT

AVDD

High Z

N = BP + A

FROMFUNCTIO

NLATCH

PHASEFREQUENCYDETECTOR

The A ( 6-bit ) and B (13-bit ) counters, in conjunction with the dual modulus prescaler ( P/P+1 ), implement an N divider ( N = BP + A ). In addition, the 14-bit reference counter ( R counter ), allows selectable REFIN frequencies at the PFD ( Phase Frequency Detector ) input. The description of the bits of each register ( Initialization, Function, AB and Reference latches ) to configure is presented in these four following pages.


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, 2002 4



ControlBits

Co

un

terR

eset

Po

wer

Do

wn

1

MUXOUTControl

Ph

aseD

etector

Po

larity

CP

3-State

Po

wer

Do

wn

2

CurrentSetting

1Prescaler

ValueTimer Counter

Control

CPI3CPI4

DB21

CurrentSetting

2

TC3 TC2 TC1

DB22DB23

Fastlo

ckE

nab

le

FastL

ock

Mo

de

F4F5

P2 P1 Prescaler Value0 0 8/90 1 16/171 0 32/331 1 64/65

CE Pin PD2 PD1 Mode0 X X Asynchronous Power-Down1 X 0 Normal Operation1 0 1 Asynchronous Power-Down1 1 1 Synchronous Power-Down

CPI6 CPI5 CP14 ICP (mA)

CPI3 CPI2 CPI1 2.7kΩ 4.7kΩ 10kΩ0 0 0 1.088 0.625 0.2940 0 1 2.176 1.25 0.5880 1 0 3.264 1.875 0.8820 1 1 4.352 2.5 1.1761 0 0 5.44 3.125 1.471 0 1 6.528 3.75 1.7641 1 0 7.616 4.375 2.0581 1 1 8.704 5.0 2.352

TC4 TC3 TC2 TC1 Timeout(PFD Cycles)

0 0 0 0 30 0 0 1 70 0 1 0 110 0 1 1 150 1 0 0 190 1 0 1 230 1 1 0 270 1 1 1 311 0 0 0 351 0 0 1 391 0 1 0 431 0 1 1 471 1 0 0 511 1 0 1 551 1 1 0 591 1 1 1 63

F4 F5 Fastlock Mode0 X F a s t l o c kDisabled1 0 Fastlock Mode 11 1 Fastlock Mode 2

M3 M2 M1 Output0 0 0 3-State Output0 0 1 Digital Lock Detect0 1 0 N Divider Output0 1 1 AVDD

1 0 0 R Divider Output1 0 1 N-Channel Open-Drain

Lock Detect1 1 0 Serial Data Output1 1 1 DGND

F3 Charge PumpOutput

0 Normal1 3-State

F3 Phase DetectorPolarity

0 Negative1 Positive

F1 CounterOperation

0 Normal1 R, A, B Counters Held in Reset

Initialization Latch


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, 2002 5


C2 (1) C1 (0)F1PD1M1M2M3F3XX CPI1CPI2CPI5CPI6 TC4PD2 F2

ControlBits

Co

un

terR

eset

Po

wer

Do

wn

1

MUXOUTControl

PH

AS

ED

ET

EC

TO

RP

OL

AR

ITY

CP

3-State

Po

wer

Do

wn

2

CurrentSetting

1

Timer CounterControl

CPI3CPI4

DB21

CurrentSetting

2

TC3 TC2 TC1

DB22DB23

Fastlo

ckE

nab

le

FastL

ock

Mo

de

F4F5

CE Pin PD2 PD1 Mode0 X X Asynchronous Power-Down1 X 0 Normal Operation1 0 1 Asynchronous Power-Down1 1 1 Synchronous Power-Down

CPI6 CPI5 CP14 ICP (mA)

CPI3 CPI2 CPI1 2.7kΩ 4.7kΩ 10kΩ0 0 0 1.088 0.625 0.2940 0 1 2.176 1.25 0.5880 1 0 3.264 1.875 0.8820 1 1 4.352 2.5 1.1761 0 0 5.44 3.125 1.471 0 1 6.528 3.75 1.7641 1 0 7.616 4.375 2.0581 1 1 8.704 5.0 2.352

TC4 TC3 TC2 TC1 Timeout(PFD Cycles)

0 0 0 0 30 0 0 1 70 0 1 0 110 0 1 1 150 1 0 0 190 1 0 1 230 1 1 0 270 1 1 1 311 0 0 0 351 0 0 1 391 0 1 0 431 0 1 1 471 1 0 0 511 1 0 1 551 1 1 0 591 1 1 1 63

F4 F5 Fastlock Mode0 X Fastlock Disabled1 0 Fastlock Mode 11 1 Fastlock Mode 2

M3 M2 M1 Output0 0 0 3-State Output0 0 1 Digital Lock Detect0 1 0 N Divider Output0 1 1 AVDD

1 0 0 R Divider Output1 0 1 N-Channel Open-Drain

Lock Detect1 1 0 Serial Data Output1 1 1 DGND

F3 Charge PumpOutput

0 Normal1 3-State

F1 CounterOperation

0 Normal1 R, A, B Counters Held in Reset

F3 Phase DetectorPolarity

0 Negative1 Positive

Function Latch


December 11th

, 2002 6


C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

ControlBits6-Bit A Counter13-Bit B Counter

DB21

Reserved

DB22DB23

CP

Gain

G1

N Counter Latch

These bits are notusedby the device and areDon't Care Bits.

F4 (Function Latch) CP Gain OperationFastlock Enable0 0 Charge Pump CurrentSetting 1 is permanently used0 1 Charge Pump CurrentSetting 2 is permanently used1 0 Charge Pump CurrentSetting 1 is used1 1 Charge Pump Current is

switched to Setting 2. Thetime spent in Setting 2 is

dependent onwhich Fastlock Mode is used.See Function LatchDescription

B13 B12 B11 B3 B2 B1 B Counter Divide Ratio0 0 0 .......... 0 0 1 10 0 0 .......... 0 1 0 20 0 0 .......... 0 1 1 30 0 0 .......... 1 0 0 4. . . .......... . . . .. . . .......... . . . .. . . .......... . . . .1 1 1 .......... 1 0 0 8188

1 1 1 .......... 1 0 1 8189

1 1 1 .......... 1 1 0 8190

1 1 1 .......... 1 1 1 8191

A6 A5 .......... A2 A1 A CounterDivide Ratio

0 0 .......... 0 1 10 0 .......... 1 0 20 0 .......... 1 1 30 0 .......... 0 0 4. . .......... . . .. . .......... . . .. . .......... . . .1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

N = BP + A, P is prescaler value set in the Function LatchB must be greater than or equal to AFor contiguous values of N, NMIN is (P2 - P)


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, 2002 7


C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

ControlBits14-Bit Reference CounterTest

Mode Bits

Lo

ck Detect

Precisio

n

Reserved

DB21DB22DB23

DLY SYNC

AntiBacklash

Width

DL

Y

SY

NC

DLY SYNC Operation0 0 Normal Operation0 1 Output of Prescaler is Resynchronized

with non-delayed version of RF Input.1 0 Normal Operation1 1 Output of Prescaler is Resynchronized

with delayed version of RF Input.

LDP Operation0 3 consecutive cycles of phase delay less than

15ns must occur before lock detect is set.1 5 consecutive cycles of phase delay less than

15ns must occur before lock detect is set.

Test Mode Bits shouldbe set to 00 for NormalOperation

ABP2 ABP1 Anti-Backlash Pulse Width0 0 2.9ns0 1 1.3ns1 0 6.0ns1 1 2.9ns

R14 R13 R12 .......... R3 R2 R1 Divide Ratio0 0 0 .......... 0 0 1 10 0 0 .......... 0 1 0 20 0 0 .......... 0 1 1 30 0 0 .......... 1 0 0 4. . . .......... . . . .. . . .......... . . . .. . . .......... . . . .1 1 1 .......... 1 0 0 16380

1 1 1 .......... 1 0 1 16381

1 1 1 .......... 1 1 0 16382

1 1 1 .......... 1 1 1 16383

Reference Counter Latch


December 11th

, 2002 8

As was shown, using the SPI port on the PLL synthesizer configures all the registers. From the PIC, data is sent to the SPI, via three wires for the clock, data and the latch enable. Once the SPI buffer is filled, a pulse is sent on the latch enable input. Thus, the value in the buffer goes to the appropriate latch. This is determined with the last two bits, or the two LSB. So, it is necessary to send the 24 bits starting with the MSB and finishing with the LSB. Using SPI, SDATA is sampled on each rising edge of SCLOCK. This diagram shows the timings, which are minimum for a good working of the synthesizer.

t6

t7

CLOCK

DB23(MSB)

DB22 DB2 DB1(CONTROL BIT C2)DATA

LE

LE

DB0 (LSB)(CONTROL BIT C1)

t2 t3

t4 t5

t1

With: t1 = 10 ns mini, LE Setup Time

t2 = 10 ns mini, DATA to CLOCK Setup Time t3 = 10 ns mini, DATA to CLOCK Hold Time t4 = 25 ns mini, CLOCK High Duration t5 = 25 ns mini, CLOCK Low Duration t6 = 10 ns mini, CLOCK to LE Setup Time t7 = 20 ns mini, LE Pulsewidth


December 11th

, 2002 9

3 The PIC12C508A:

For this simple application, it was decided to work with one of the Microchip micro-controllers. The PIC12C5XX family has an internal oscillator at 4 MHz, 8-bit wide data and 8 pins. Moreover, they are in-circuit programmable. This is a special feature that could be used in the future, because for the present, the PIC is programmed with the PICSTART Plus development programmer. These micro-controllers are not SPI compatible. A transmission protocol, called bit-banging, will be used to transfer data from the PIC to the PLL synthesizer. This protocol is compatible with the SPI, as it is based on it.

The PIC12C508A is one of the simplest and cheapest micro controllers from Microchip.

Here it was decided to use an one-time programmable ( OTP ) chip, because of the wanted fixed frequency. So with the software code inside this report, only one frequency is pre-programmed into the PIC. VDD VSS GP4/OSC2 GP1 GP3/ /MCLR / VPP GP2/TOCK1

Figure 1: Pin diagram VDD and VSS are the power supply and the ground. The pin /MCLR needs to be set at a high level. It is the master clear, which allows a reset for all the chip. Only three pins on the PIC are used, to implement the SPI protocol:

GP0 CLK GP1 DATA GP2 LE

Only GP4 and GP5 are left not used, but as they are input/output pins, they will not be connected. Finally, minimum timings for a good transmission were given in the previous section. The PIC will be synchronized with its internal oscillator at 4 MHz. Thus, its each Clock cycle will be 250 ns, large enough to ensure a good transmission of the data.

1 8 2 7 3 6 4 5

PIC12C

508A

GP0 GP5/OSC1/CLKIN


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, 2002 10

4 The software code: 4.1 The bit banging protocol:

As mentioned above, the PIC12C508A doesn’t have a SPI support. That’s why was developed a bit banging protocol, to emulate an SPI interface. Three pins are used for data, clock and latch enable. Before the transmission, data can’t be stocked in a 8-bit register, opposite to the SPI where it’s a 24-bit register.

So, the data will be transmitted bit per bit. To know the data value, a left rotation through the carry is done. After testing the carry value, the pin DATA is set or cleared. The rotation needs to be left, because it is necessary to transmit the MSB first. Once the DATA is positioned, the CLK pin is set and cleared, creating a cycle. Then, the PLL synthesizer samples the DATA, on its pin, and loads it into its input latch. To be sure that sampling is correct, it is better to wait before clearing the pin CLK, doing the next left rotation through the carry, preparing the new data value to transmit. In the way of 8 repetitions, 8 bit-data can be sent bit per bit, and stocked in the 8-bit SPI latch of the synthesizer.

Figure 2:Functional diagram

First left rotation

Test of the carry

=0 ? =1 ?

DATA = 0 DATA = 1

CLK = 1

Left rotation

CLK = 0

x 8


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, 2002 11

4.2 Code Architecture: 4.2.1 CONFIGURATION BITS: The 12 configuration bits allow the user to select several device configurations. Only five of them are writable, the others being unimplemented. Two are for the selection of oscillator type, one to enable the watchdog timer bit, one for the code protection and the last one to enable the /MCLR bit.

Figure 3: Configuration word for the PIC12C5XX

During device operations, this register can’t be addressable. So to configure it, specific instructions are used, as explained below. Underlined are the instructions that were chosen.

FOSC0 FOSC1 INSTRUCTIONS SELECTION

1 1 _ExtRC_OSC External RC Oscillator

1 0 _IntRC_OSC Internal 4 MHz RC Oscillator

0 1 _XT_OSC Crystal/Resonator Oscillator

0 0 _LP_OSC Lower Power Crystal Oscillator

WDTE SELECTION

_WDT_ON Enabled

_WDT_OFF Disabled

CP SELECTION

_CP_ON Code protection on

_CP_OFF Code protection off

MCLRE SELECTION

_MCLRE_ON /MCLRE pin enabled

_MCLRE_OFF /MCLRE tied to Vdd ( internally )

MCLRE CP WDTE FOSC1 FOSC0

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Not implemented


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, 2002 12

As the watch dog timer and the code protection are not used, the CP and WDT bits are off. The bit /MCLR is on to hardwire the RESET low. And the internal oscillator for our application will be used. 4.2.2 CONSTANTS & VARIABLES DEFINITION: 4.2.2.1 Outputs Three I/O pins on the micro controller are connected to the 3-wire serial interface of the PLL synthesizer, allowing the PIC to transmit configuration data to frequency synthesizer. They are: The pins GP0, GP1 and GP2 will be configured as outputs later in the code, by configuring the Tris register. Here we are simply labelling the pins of the PICis only a labelling for the pins of the PIC. 4.2.2.2 Data registers to transmit The following data need to be entered by the user to program the PLL synthesizer’s output frequency Four 24-bit words have to be transmitted to the PLL synthesizer. As only data bytes are available in the PIC memory, each 24-bit word will be split into 3 bytes: one most significant, one middle and one least significant. So we have: For the Reference Latch, REF_LATCH_H REF_LATCH_M REF_LATCH_L For the AB Latch, AB_LATCH_H AB_LATCH_M AB_LATCH_L For the Function Latch, FCT_LATCH_H FCT_LATCH_M FCT_LATCH_L For the Initialization Latch, INIT_LATCH_H INIT_LATCH_M

GPIO of the PIC Pin labels

GP0 CLK

GP1 DATA

GP2 LE


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INIT_LATCH_L In this definition, memory space is allocated and its value in hexadecimal code is entered. See in the section 7, how to program them. 4.2.2.3 Variables Temp is used in the SEND_BYTE sub-routine. It contains the value of one the register bytes to transmit. After each left rotation to get the new bit to send, the result is put in the Temp variable. Count, used in the same sub-routine as the Temp variable, is initialised to 8 and decremented at each rotation. It’s a counter to send 8 bits, not more, not less. When it equals zero, the SEND_BYTE sub-routine is stopped. 4.2.3 PROCESSOR INITIALIZATION: To initialise the processor, the following registers need to be configured: The OSCCAL where six of its eight bits allow the internal 4 MHz oscillator to be calibrated. Increasing the cal value, increases the frequency. The OPTION_REGISTER contains the controls bit to configure timer0, timer0/watchdog prescaler, wake-up on change and weak pull-ups.

/GPWU

SELECTION

0 Wake-up on pin change ( GP0, GP1, GP3 ) enabled

1 Wake-up on pin change disabled

/GPPU

SELECTION

0 Weak pull-ups ( GP0,GP1,GP3 ) enabled

1 Weak pull-ups disabled

Cal 0 Cal 1 Cal 2 Cal 3 Cal 4 Cal 5

Bit 7 Bit 0

/GPWU /GPPU TOCS TOSE PSA PS2 PS1 PS0

Bit 0 Bit 7


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TOCS

( timer clock source select bit )

SELECTION

0 Transition on internal instruction cycle clock Fosc/4

1 Transition on TOCK1 pin

TOSE

( timer0 source edge select bit )

SELECTION

0 Incrementing on low to high transition on the TOCK1 pin

1 Incrementing on high to low transition on the TOCK1 pin

PSA ( Prescaler assignment bit )

SELECTION

0 Prescaler assigned to timer0

1 Prescaler assigned to the WDT

PS2 PS1 PS0

Timer0 rate

WDT rate

000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1:16 1:8 100 1:32 1:16 101 1:64 1:32 110 1:128 1:64 111 1:256 1:128

The GPIO is an 8-bit I/O register. Only the lowest significant bits are used, the others are unimplemented. GP3 in only an input. The TRIS register allows to configure each pins as an input or output of the GPIO. It is the output driver control register. A “1” from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A “0” puts the contents of the output data latch on the selected pins, enabling the output buffer.


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4.2.4 DATA TRANSMISSION: Four 24-bit words are sent each split into three bytes. There are four sub-routines, each specific for one of the four 24-bit words: SEND_INIT_WORD SEND_FCT_WORD SEND_AB_WORD SEND_REF_WORD First, the initialisation word is sent to the PLL synthesizer. It is needed for the first programming of the chip. Then, the function word, the N counter or AB counter word and, finally the Reference word, will be transmitted. Once all are sent, the micro-controller stays in an infinite loop doing nothing. 4.2.5 SUB-ROUTINES: SEND_BYTE is the sub-routine for the bit banging protocol, based on the SPI serial interface. Its function is to clock out a byte of data via the data and clock outputs. See section bit banging protocol Variables: Temp, contains the data byte to send to the PLL synthesizer. Count, which is a counter initialised to 8. Send a byte is done as follows ( see figure 2: Functional diagram ): - Initialization of the variables Temp and Count, with the data byte to transmit from the W register and the hexadecimal value 8. - First left rotation through the carry, where the MSB is ready to be transmitted. - Carry test. If carry bit equals 1, call the “ONE” sub-routine to set the DATA pin. If carry bit equals 0, call the “ZERO” sub-routine to clear the DATA pin. - Clock pin is toggled and a new left rotation is done, allowing time for the PLL synthesizer to sample data. - Decrementing of the counter and back to the carry test, which has got the next bit to transmit with the rotation during the clock banging. A test is done on the Count value, while being decremented. When Count equals 0, eight bit-transmission is finished, and so, all the three bytes have been sent to the synthesizer. We return from this sub-routine to the sub-routine, which called it. It could be SEND_INIT_WORD, SEND_FCT_WORD, SEND_AB_WORD or SEND_REF_WORD. SEND_INIT_WORD is a sub-routine to send the configuration word for the initialization latch of the PLL synthesizer. First, the most significant byte is sent using the SEND_BYTE routine. Then, the middle byte is sent, followed by the least significant byte. The value of those bytes is loaded from the memory to the W register, and then use in the SEND_BYTE routine with the local variable Temp.


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SEND_FCT_WORD, SEND_AB_WORD and SEND_REF_WORD are built in the same way as SEND_INIT_WORD, but their respective purpose is to transmit the configuration word for the function, N counter and Reference latches. LATCH_ENABLE is the last sub-routine of the software code. It simply generates a pulse on the PIC pin linked to the PLL synthesizer LE. After the falling edge of a 24-bit register write operation, the “clock to LE setup time”(10 ns ) must be observed, so the minimum LE pulsewidth ( 20 ns ) before clearing the LE bit. Toggling the LE bit takes the 24 bit data, which has just been clocked into the synthesizer’s input shift register, and loads it into one of the corresponding data latch.


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, 2002 17

5 Timings Below are the timings for programming a 411X PLL synthesizer with a PIC12C508A programmed for the fixed frequency of 900 MHz, and a PFD of 200 kHz. Data to configure the PLL at these working conditions, is: INITIALIZATION LATCH : 9F 80 93h FUNCTION LATCH : 9F 80 92h AB LATCH : 00 8C 51h

REFERENCE LATCH : 00 00 C8h There are four LE pulses, each one positioned after three packs of eight clock events ( or three bytes ). So, these 24 clock cycles correspond to the transmission of 24 bits, that is to say one configuration word to the PLL synthesizer. The first one is the configuration word for the initialisation latch, the second one for the function latch, the third one for the AB latch and the last one for the Reference latch. DATA CLK LE

Initialization Function AB Reference


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Below are represented, the average timings measured by scope, while sending data from the PIC12C508A to the PLL synthesizer. DATA 81.20 us CLK 9.2 us 6us LE 1.4 us To transmit one byte: 81.20 us To transmit one word: 250 us Time between two clock raising edge: 9.2 us Clock and LE Pulsewidth: 1.4 us Comparing with the timings of the SPI transmission in the section 2, they are large enough to allow a good transmission of the data, between the micro controller and the PLL synthesizer.


December 11th

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6 Schematic The simplest connection schematic between the PLL synthesizer and the PIC, is the following: On the following pages, are given the whole schematic of the board built for this application, with all the components, like decoupling capacitors, resistors, etc…, for the good working of each chip on the board; and the silkscreen of this same board.

CLK

DATA

LE

ADF4110/1/2/3

PIC12C508A

VDD

VDD GP0

GP1

GP2

SCK

SDATA

LE


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7 How to use this software code This use guide of the software is based on the example of a PLL that we want it to work in the following conditions: Chip : ADF4113 Power : 5V Icpmax : 5 mA REFin : 10MHz Output Frequency : 900MHz PFD : 200kHz Muxout : Digital lock detect Rset : 4,7kOhm Prescaler : 32 PD Polarity : positive Current settings (1&2 ) : 7 7.1 Programming environment The evalboard has been developed to use the PIC12C508A, SOIC package or DIP socket. The power supply could be 3V or 5V for both the PIC and the synthesizer. The output levels coming from the PIC depend of the power supply. To program the PIC, the user needs the PICSTART Plus development programmer, a PC with a serial port, the Microchip software MPLAB, version 5.20. The software code is written in the MPASM language, specific to the Microchip micro controllers. 7.2 How to get the wanted fixed frequency While it is soldered on the board, the PLL synthesizer is programmed by the PIC. If the user does want to use the serial connection, the PIC would have been removed, which keeps the priority between both kinds of PLL synthesizer’s programming. The software given to the user is optimised to program an output frequency of 900 MHz for the ADF4113. To change the value of this output frequency, the new value to enter into each register of the synthesizer needs to be calculated. For that, it is possible to use the interactive tool on the ADI website: http://www.analog.com/techSupport/designTools/interactiveTools Then, by clicking on the link called ADF 4110/1/2/3 in the Phase-Locked Loop section, the tool to calculate the hexadecimal value of each register of the chosen device is launched. The only things to enter are the working conditions of the synthesizer on the top of the page.


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Next to the registers, you can find their hexadecimal value to write into the software code following the same order that they are presented by the tool. If one of the hexadecimal values starts with a letter ( A, B, C, D, E or F ), a zero should be put before it. For example: To write the hex value C8h, it will be written 0C8h. However, a zero mustn’t be put for a value with a letter in it, but starting with a number, as 9F. Remember that a register is split into three bytes. For example, the Reference latch value to enter is 0000C8h, you will fill the bytes in the code as shown below: REF_LATCH_H : 00h REF_LATCH_M : 00h REF_LATCH_L : 0C8h In the software code, a summary of these indications is done, above the variables to update.


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8 Software code: ;***************************************************************************** ; * ; Filename : pic12c.asm * ; Date : 21/11/02 * ; * ; Author : Pauline LEMORE * ; Company : Analog Devices * ; * ;***************************************************************************** ; * ; Notes : The PIC12C508A is used with the EVAL-ADF411XEB1 * ; This PIC doesn't have an SPI. To transmit data * ; to PLL, the bit banging protocol is used. * ; * ;***************************************************************************** list p=12c508a ;definition of the processor used #include <p12c508a.inc> ;include processor specific variable definitions __CONFIG _CP_OFF & _WDT_OFF & _MCLRE_ON & _IntRC_OSC ;***************************************************************************** ; CONSTANTS DEFINITION * ;***************************************************************************** #define CLK GPIO,0 #define DATA GPIO,1 #define LE GPIO,2 ;===================================================================== ;= = ;= Following, data to configure the PLL synthesizer. = ;= = ;= They can be calculated using the following link : = ;= ---------------------------------------------------------------- = ;= http://www.analog.com/techSupport/designTools/interactiveTools + ADF411x = ;= ---------------------------------------------------------------- = ;= = ;= Notes : = ;= = ;= All configuration words are 24 bits, so for programming they are split = ;= into 3 bytes. It is important to start with the most significant byte. = ;= A useful link to help in programming the PIC is given just above. = ;= The registers have to be filled in the same order as presented by the design tool. = ;= = ;= Note, for programming the PIC, if the hex values starts with a letter, = ;= a zero should have been put before. For example : =


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;= = ;= To write the hex value C8h, it will be written 0C8h. = ;= But, to write the hex value 9F, a zero mustn't be put. = ;= = ;= --------------------------------------------------------------- = ;= = ;= Example of programming: = ;= = ;= To get these working features for the EVAL-ADF4113EB1 : = ;= = ;= --------------------------------------------------------------- = ;= chip : ADF4113 power : 5 V Icpmax : 5mA = ;= REFin : 10 MHz VCO : 900 MHz PFD : 200 kHz = ;= P : 32 Rset : 4,7 kohms = ;= Muxout : digital lock detect PD Polarity : ticked = ;= Current settings ( 1 & 2 ) : 7 = ;= ---------------------------------------------------------------- = ;= = ;= the values to put in the registers are : = ;= = ;= REFERENCE LATCH : 00 00 C8h = ;= AB LATCH : 00 8C 51h = ;= FUNCTION LATCH : 9F 80 92h = ;= INITIALIZATION LATCH : 9F 80 93h = ;= = ;= As the REFERENCE latch is divided into 3 bytes, they will be filled as = ;= shown below : = ;= = ;= REF_LATCH_H : 00h the most significant byte = ;= REF_LATCH_M : 00h = ;= REF_LATCH_L : 0C8h the less significant byte = ;= = ;===================================================================== #define REF_LATCH_H 00h ; High Reference Latch Byte #define REF_LATCH_M 00h ; Middle Reference Latch Byte #define REF_LATCH_L 0C8h ; Low Reference Latch Byte #define AB_LATCH_H 00h ; High AB Latch Byte #define AB_LATCH_M 8Ch ; Middle AB Latch Byte #define AB_LATCH_L 51h ; Low AB Latch Byte #define FCT_LATCH_H 9Fh ; High Function Latch Byte #define FCT_LATCH_M 80h ; Middle Function Latch Byte #define FCT_LATCH_L 92h ; Low Function Latch Byte #define INIT_LATCH_H 9Fh ; High Initialization Latch Byte #define INIT_LATCH_M 80h ; Middle Initialization Latch Byte #define INIT_LATCH_L 93h ; Low Initialization Latch Byte


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; ------------------------------------------------------- ; end of data to update ; ------------------------------------------------------- ;***************************************************************************** ; VARIABLES DEFINITION * ;***************************************************************************** temp EQU 08h count EQU 09h ;***************************************************************************** ; CODE CORE * ;***************************************************************************** ORG 00h ; processor reset vector goto main main ; ------------------------------------------------------- ; processor initialization ; ------------------------------------------------------- INIT clrf OSCCAL clrf GPIO movlw 0CFh OPTION movlw 0FFh movwf OSCCAL movlw 00h TRIS 6 ; ------------------------------------------------------- ; to send data to the PLL synthesizer ; ------------------------------------------------------- SENDING call SEND_INIT_WORD call SEND_FCT_WORD call SEND_AB_WORD call SEND_REF_WORD nop B $-1


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;===================================================================== ;= to send configuration words for the pll = ;= --------------------------------------- = ;= As the configuration words are 24 bits and the register for the serial = ;= transmission has 8 bits, the data need to be transferred in 3 goes or 3 bytes. = ;===================================================================== SEND_BYTE movwf temp ;data to transmit in the temp variable movlw 08h movwf count ;initialization of the counter for the 8-bit-transmission bcf STATUS,C ;clear the carry rlf temp,1 ;MSB put into the carry, through a left rotation LOOP btfsc STATUS,C ;test of the carry. If equals to 1, set SPIDATA. goto ONE goto ZERO ;If equals to 0, clear SPIDATA SEND_BIT bsf CLK ;banging of the clock rlf temp,1 ;rotation to put the new bit to be transmitted into the carry bcf CLK decfsz count,1 ;when count equals to 0, all 8 bits have been transmitted goto LOOP retlw 0 ONE bsf DATA goto SEND_BIT ZERO bcf DATA goto SEND_BIT ; ------------------------------------------------- ; send the configuration word for the ; Initialization latch ; ------------------------------------------------- SEND_INIT_WORD movlw INIT_LATCH_H ;loading of the highest byte of data to transmit call SEND_BYTE ;transmission of the highest byte of data movlw INIT_LATCH_M ;for the middle byte of data call SEND_BYTE movlw INIT_LATCH_L ;for the low byte of data call SEND_BYTE call LATCH_ENABLE retlw 0


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; ------------------------------------------------- ; send the configuration word for the ; Function latch ; ------------------------------------------------- SEND_FCT_WORD movlw FCT_LATCH_H call SEND_BYTE movlw FCT_LATCH_M call SEND_BYTE movlw FCT_LATCH_L call SEND_BYTE call LATCH_ENABLE retlw 0 ; ------------------------------------------------- ; send the configuration word for the ; AB latch ; ------------------------------------------------- SEND_AB_WORD movlw AB_LATCH_H call SEND_BYTE movlw AB_LATCH_M call SEND_BYTE movlw AB_LATCH_L call SEND_BYTE call LATCH_ENABLE retlw 0 ; ------------------------------------------------- ; send the configuration word for the ; Reference latch ; ------------------------------------------------- SEND_REF_WORD movlw REF_LATCH_H call SEND_BYTE movlw REF_LATCH_M call SEND_BYTE movlw REF_LATCH_L call SEND_BYTE call LATCH_ENABLE retlw 0


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; ------------------------------------------------- ; to send the LE signal ; ------------------------------------------------- LATCH_ENABLE nop bsf LE nop bcf LE retlw 0 ; ------------------------------------------------- ; End of the program ; ------------------------------------------------- END

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