picnode board specs - ipfn · 2010. 2. 23. · picnode board specs horácio fernandes joão...
TRANSCRIPT
PICNODE board specs
Horácio FernandesJoão FortunatoLeonardo PedroTiago Pereira
Micro processor- dsPIC30F4013- Fcristal = 7,3728MHZ- max clock: Fcristal * 16 / 4 = 29.4912 MIPS
InterfacesSome interfaces are pin multiplexed- Optical serial interface (Rx and Tx)- CAN- RS485 (Half Duplex)- RS232 (true RS232 from MAX232 or equivalent)- I2C- SPI- RJ11 (for ICD2, a microchip programmer)
IOSome IO features are pin multiplexed- up to 8 power pull-down outputs (0.5A per output)- up to 6 analog inputs- up to 31 general purpose digital IO- up to 3 external interrupt sources
Board- one push button for reset (SW2)- one push button connected to general I/O pin (SW1)- two monitoring led connected to I/O pins
Clock- 7,3728MHZ cristal for uP clock (0% error in baud rates generation)- 32,768KHz cristal (example applications: 1s real time clock (unix time format) or 1s period timer)
Communication speed- optical: up to 1,8Mbaud (limited by pic clock)- RS232 port: min 120kbps for HIN232CPZ (depends on RS232 converter)- RS232 standard baud rates: 9600, 19200, 38400, 115200, 460800, 921600 (with appropriate
RS232 converter)
Programming- 1st option: . use microchip ICD2 connected to RJ connector . work with MPLAB IDE . programming jumpers must be in position 1 . programming switch must connect pins 1 and 2 - 2nd option: . use serial straight through cable from PC serial port to picnode board D9 connector . compile your code in MPLAB IDE . use "WinPic - A PIC Programmer for Windows" to program the pic . programming jumpers must be in position 3 . programming switch must connect pins 2 and 3 when programming . programming switch must connect pins 1 and 2 when using the rs232 port
DIN 96 pins outputs- Avcc: 5v used as reference for pic ADC. Maximum current out of these pins: 100mA- Vcc_unreg: vcc voltage not regulated. Maximum current: 0.9A- Vcc_5: 5v voltage supply to the pic. Maximum current: 0.8A- 5V_pwr: regulated 5v output (7805). Maximum current: 1A
- Agnd: ground (0V) used as reference to the pic ADC- GND: general ground
- an0, an1, ...: inputs to the several ADC channels- PwrDrv0 to PwrDrv7: power pulldown outputs- canrx and cantx: can output and input directly from the pic- can_h and can_l: differential can line from the can transceiver- rx2 and tx2: uart output and input directly from the pic- sdo: pic output to be used in rs485- rs485_a and rs485_b: differential rs485 line from the rs485 transceiver- int0, int1 and int2: pic external interrupt pins- rc13 and rc14: pic general purpose IO
Schematic - Core section
55
44
33
22
11
DD
CC
BB
AA
<D
oc>
1
dsp
icn
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oa
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Title
Siz
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ocu
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nt N
um
be
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ev
Da
te:
Sh
ee
to
f
U2
MC
P2
55
1
TX
D1
RX
D4
CA
NH
7
CA
NL
6V
SS
2
VD
D3
VR
EF
5
RS
8
R4
1K
R3
40
R
R3
9
0R
R1
0
0R
X1
7.3
72
8M
HZ
U4
UL
N2
80
3
CO
M1
0G
ND
9
IN1
1
IN2
2
IN3
3
IN4
4
IN5
5
IN6
6
IN7
7
IN8
8
OU
T1
18
OU
T2
17
OU
T3
16
OU
T4
15
OU
T5
14
OU
T6
13
OU
T7
12
OU
T8
11
R3
3
0R
R1
80
R
R2
0
10
K
R3
2
0R
R4
4
12
0R
U9
MA
X2
32
A
C1
+1
C1
-3
C2
+4
C2
-5
VC
C1
6
GN
D1
5V
+2
V-
6
%%
oR
1O
UT
%%
o1
2
%%
oR
2O
UT
%%
o9
T1
IN1
1
T2
IN1
0
R1
IN1
3
R2
IN8
%%
oT
1O
UT
%%
o1
4
%%
oT
2O
UT
%%
o7
C3
10
0 n
F
U1
-MC
LR
-1
AN
0/V
RE
F+
/CN
2/R
B0
2
AN
1/V
RE
F-/C
N3
/RB
13
AN
2/S
S1
/LV
DIN
/CN
4/R
B2
4
AN
3/C
N5
/RB
35
AN
4/C
N6
/RB
46
AN
5/C
N7
/RB
57
PG
C/E
MU
C/A
N6
/OC
FA
/RB
68
PG
D/E
MU
D/A
N7
/RB
79
AN
8/R
B8
10
VD
D1
1
VS
S1
2
OS
C1
/CL
KI
13
OS
C2
/CL
KO
/RC
15
14
EM
UD
1/S
OS
CI/T
2C
K/U
1A
TX
/CN
1/R
C1
31
5
EM
UC
1/S
OS
CO
/T1
CK
/U1
AR
X/C
N0
/RC
14
16
INT
0/R
A1
11
7
IC2
/IN
T2
/RD
91
8
RD
31
9
VS
S2
0V
DD
21
RD
22
2
IC1
/IN
T1
/RD
82
3
EM
UC
3/S
CK
1/R
F6
24
EM
UD
3/U
1T
X/S
DO
1/S
CL
/RF
32
5
U1
RX
/SD
I1/S
DA
/RF
22
6
U2
TX
/CN
18
/RF
52
7
U2
RX
/CN
17
/RF
42
8
C1
TX
/RF
12
9
C1
RX
/RF
03
0
VS
S3
1
VD
D3
2
EM
UD
2/O
C2
/RD
13
3
UM
UC
2/O
C1
/RD
03
4
AN
12
/RB
12
35
AN
11
/RB
11
36
AN
10
/RB
10
37
AN
9/R
B9
38
AV
SS
39
AV
DD
40
R3
1
0R
D4
LE
D
C2
8
10
0n
F
C2
2
10
0 n
F
C2
5
10
0 N
F
C2
10
0 n
F
C5
18
pF
R3
80
R
R7
1K
R1
5
10
0K
D3
LE
D
R3
7
0R
R2
12
0
R8
1K
R6
1K
C1
10
0 n
F
C6
10
0 n
F
R2
4
10
K
R3
6
0R
X2
32
,76
8 K
HZ
R3
5
0R
R2
90
R
R1
1
0R
U1
0
LT
C4
85
RO
1D
I4
GN
D5
VC
C8
DE
3
%%
oR
E%
%o
2A
6
B7
C8
10
0 n
F
R2
20
R
C1
3
18
pF
C1
2
10
0 n
F
R1
3
10
K
R2
5
4K
7
SW
1
R3
00
R
R9
0R
C1
4
18
pF
SW
2
C2
9
10
0 n
F
R2
80
R
C7
10
0 n
F
C2
7
10
0 n
F
R4
20
R
C1
1
10
0 n
F
R4
1
0R
R1
40
R
R2
3
4K
7
R4
0
0R
C4
10
0 n
F
PG
D
PG
C
CA
N_
L
CA
NT
X
CA
NR
X
RX
2
TX
2
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
8
AN
10
AN
9
AN
11
AN
12
RD
1
RD
0
RX
_P
C
MC
LR
*
AN
8
AN
9
AN
10
AN
11
Pw
rD
rv0
Pw
rD
rv1
Pw
rD
rv2
Pw
rD
rv3
Pw
rD
rv4
Pw
rD
rv5
Pw
rD
rv6
Pw
rDrv7
SD
O
RD
3
TX
1/S
CL
RX
1/S
DA
INT
1
RD
2
MC
LR
*
TX
2
RX
2
RD
0
RD
1
RD
2
RD
3
AN
4
AN
5
RX
1/S
DA
TX
1/S
CL
SD
OR
S4
85
_A
RS
48
5_
B
CA
NR
X
AN
8
AN
9
RD
0
RD
1
RD
2
RD
3
AN
10
AN
11
Pw
rD
rv3
Pw
rD
rv4
Pw
rD
rv5
Pw
rD
rv6
Pw
rDrv7
Pw
rD
rv1
Pw
rD
rv2
Pw
rD
rv0
INT
2
INT
0
RC
13
CA
NT
X
CA
N_
H
RX
_M
AX
VC
C_
5
VC
C_
5
VC
C_
5
VC
C_
5
VC
C_
UN
RE
G
VC
C_
5
VC
C_
5
VC
C_
5
VC
C_
5
VC
C_
5
VC
C_
5
VC
C_
5
Pw
rD
rv2
Pw
rD
rv3
Pw
rD
rv4
Pw
rD
rv5
Pw
rD
rv6
Pw
rD
rv7
Pw
rDrv0
Pw
rD
rv1
MC
LR
an
0
an
1
an
2
an
3
an
4
an
5
pg
c
pg
d
an
12
rx2
tx2
sd
oin
t0
int2
int1
rx1
/sd
a
tx1
/scl
ca
nrx
ca
ntx
ca
n_
l
rc1
3
rc1
4
ca
n_
h
rs4
85
_b
rs3
85
_a
avcc
Op
tio
na
l
Op
tio
na
l
Schematic - Input/output section
55
44
33
22
11
DD
CC
BB
AA
<D
oc>
1
dsp
icn
od
e b
oa
rd -
inp
ut/o
utp
ut
B
23
Mo
nd
ay,
Ma
rch
03
, 20
08
Titl
e
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
TP
8
AG
ND
TP
9
MC
LR
R4
73
30
R
12
R1
95
60
R
12
J26
C
DIN
96
_A
BC
-RC1
C2
C3
C4
C5
C6
C7
C8
C9
C1
0
C1
1
C1
2
C1
3
C1
4
C1
5
C1
6
C1
7
C1
8
C1
9
C2
0
C2
1
C2
2
C2
3
C2
4
C2
5
C2
6
C2
7
C2
8
C2
9
C3
0
C3
1
C3
2
J3
0
HE
AD
ER
3
1
2
3
TP
10
GN
D
TP
1
AV
CC
R2
15
60
R
12
TP
6
VC
C
R4
3
18
0
12
P1
CO
NN
EC
TO
R D
B9
594837261
U1
1
BS
17
0/T
O
C2
3
22
0p
F
TP
4
PG
D
R4
93
30
R
12
R4
50
R
12
R5
0
4K
7
12
R4
83
30
R
12
J26
A
DIN
96
_A
BC
-RA1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
A1
7
A1
8
A1
9
A2
0
A2
1
A2
2
A2
3
A2
4
A2
5
A2
6
A2
7
A2
8
A2
9
A3
0
A3
1
A3
2
TP
2
5V
_P
WR
C2
1
10
0 n
F
C6
2
10
0 n
F
R4
63
30
R
12
J3
1
HE
AD
ER
3
1
2
3
TP
7
V_
Un
reg
U8
HF
BR
-24
12
OU
T6
GN
D3
VC
C2
NC
4N
C5
NC
1
GN
D7
NC
8
J26
B
DIN
96
_A
BC
-RB1
B2
B3
B4
B5
B6
B7
B8
B9
B1
0
B1
1
B1
2
B1
3
B1
4
B1
5
B1
6
B1
7
B1
8
B1
9
B2
0
B2
1
B2
2
B2
3
B2
4
B2
5
B2
6
B2
7
B2
8
B2
9
B3
0
B3
1
B3
2
TP
5
GN
D
C2
6
10
0 n
F
U7
HF
BR
-14
12
AN
OD
E6
CA
TH
OD
E3
AN
OD
E2
NC
4
NC
5
NC
1
AN
OD
E7
NC
8
R5
1
4K
7
12
J2
9
HE
AD
ER
3
1 2 3
J28 H
EA
DE
R 6
1 2 3 4 5 6
TP
3
PG
C
U1
2
BS
17
0/T
O
C2
4
22
0p
F
PG
D_
ser
ial
TX
_P
C
TX
1/S
CL
MC
LR
*
PG
C_
seri
al
RX
_P
C
AN
5
RX
1/S
DA
AN
3
AN
1
AN
4
AN
0
AN
2
AN
12
RX
_M
AX
TX
_P
C
MC
LR
*
PG
D
PG
C
PG
DP
GC
PG
D_
seri
al
PG
C_
seri
al
VC
C_
5
VC
C_
5
VC
C_
5
VC
C_
UN
RE
G
AV
CC
5V
_P
WR
VC
C_
5
VC
C_
5
AV
CC
MC
LR
an
0
an
1
Pw
rD
rv1
Pw
rDrv
6
Pw
rDrv
4
Pw
rDr
v3
Pw
rDrv
0
Pw
rDrv
2
Pw
rD
rv5
an
5
an
3
an
4
an
12
an
2
Pw
rD
rv7
ca
ntx
can
rx
can
_h
can
_l
tx2
rx2
sd
o
rx1
/sd
a
tx1
/scl
rs4
85
_b
rs3
85
_a
int1
rc1
4int2
int0
rc1
3
Use
on
ly w
ith I2
C p
ro
toc
ol
Schematic - Power section
55
44
33
22
11
DD
CC
BB
AA
<D
oc>
1
dsp
icn
od
e b
oa
rd
- p
ow
er
B
33
Mo
nd
ay,
Ma
rch
03
, 2
00
8
Tit
le
Siz
eD
ocu
me
nt
Nu
mb
er
Re
v
Da
te:
Sh
ee
to
f
C2
0
22
00
UF
+
VR
4
LM
78
L0
5C
/TO
92
IN3
OU
T1
GND2
J27
RC
A J
AC
K
12
D1
D1
N4
00
1
C1
9
10
0 N
F
C9
10
0 U
F
+
C1
8
10
UF
+
C1
0
10
0 N
F
R1
7
10
RR
16
1R
L2
CH
OK
ED
2
LE
D
R5
1K
C1
7
10
0 N
F
C1
6
47
0U
F
+
VR
2
LM
78
05
C/T
O2
20
IN1
OU
T3
GND2
VR
1
LM
78
05
C/T
O2
20
IN1
OU
T3
GND2
VC
C_
UN
RE
GV
CC
_5
VC
C_
UN
RE
G
VC
C_
UN
RE
G
AV
CC
VC
C_
UN
RE
G
5V
_P
WR
AG
ND
vcc_
un
re
g
avc
c5
v_p
wr
vcc_
5
PCB layout - Top layer
0.098 CARD GUIDES
S W 2 S W 1
VR 4
VR 2
Q1
D1
6
1
J28
J29
R51
R50
R47
R46
R30
R29
R28
R25R
24
R22
R20
R18
R7
R6
R5
R4
R2
R48
C25
MCLR
C28
C12
C10
C8
C 4
C2
U1
U9 D4 D3 D2
C16
C20
C9
C18
L2
X 2
PGC
0.109
0.218 3.500
3.937
J26
6.299
B 32
A 1
B 1
C1
A 32
C32
X1
V R 1
96
51
U2
+V GND
RX TX
U10
U4
Outubro 2007
EU
RA
TO
M/IS
T
dsPicN
ode v1.2C
FN
-IST
5V _PWR
J27
1
A VCC
122
R16
V_UNREG
VCCGND
PGD
31
J31
31
J30 S
D
121
GND_PWR
A GND
Q2
DS
R17
PCB layout - Bottom layer
C23
R49
R4
5
R4
3
R 23
R 19
R15
R1
3
R8
R41
R4
0
R3
9
R3
8
R37
R3
6
R3
5
R3
4
R3
3
R3
2
R31
R1
4
R11
R10
R9
C62
C 24C
21
C19
C17
C14
C13
C1
1
C7
C6
C5
C 3
C1
R42
0.2183.500
3.937
6.050
C2
6
C22
C27