pipeline control hazards and instruction variations
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Pipeline Control Hazards and Instruction Variations. Hakim Weatherspoon CS 3410, Spring 2011 Computer Science Cornell University. See P&H Appendix 4.8 & 2.16 and 2.17. Announcements. PA1 available: mini-MIPS processor PA1 due next Friday Work in pairs Use your resources - PowerPoint PPT PresentationTRANSCRIPT
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Pipeline Control Hazardsand Instruction Variations
Hakim WeatherspoonCS 3410, Spring 2011
Computer ScienceCornell University
See P&H Appendix 4.8 & 2.16 and 2.17
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AnnouncementsPA1 available: mini-MIPS processorPA1 due next Friday Work in pairsUse your resources• FAQ, class notes, book, Sections, office hours, newsgroup,
CSUGLab
Prelims: • Thursday, March 10th in class• Thursday, April 28th Evening
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Goals for TodayRecap: Data HazardsControl Hazards• What is the next instruction to execute if a branch is
taken? Not taken?• How to resolve control hazards• Optimizations
Instruction Variations• ARM• x86
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Data Hazard RecapDelay Slot(s)• Modify ISA to match implementation
Stall• Pause current and all subsequent instructions
Forward/Bypass• Try to steal correct value from elsewhere in pipeline• Otherwise, fall back to stalling or require a delay slot
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More Hazards
beq r1, r2, L
add r3, r0, r3
sub r5, r4, r6
L: or r3, r2, r4
datamem
instmem D
B
A
PC
+4
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More Hazards
beq r1, r2, L
add r3, r0, r3
sub r5, r4, r6
L: or r3, r2, r4
datamem
instmem D
B
A
PC
+4
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Control HazardsControl Hazards• instructions are fetched in stage 1 (IF)• branch and jump decisions occur in stage 3 (EX) • i.e. next PC is not known until 2 cycles after branch/jump
Delay Slot• ISA says N instructions after branch/jump always executed
– MIPS has 1 branch delay slot
Stall (+ Zap)• prevent PC update• clear IF/ID pipeline register
– instruction just fetched might be wrong one, so convert to nop• allow branch to continue into EX stage
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Delay Slot
beq r1, r2, L
ori r2, r0, 1
L: or r3, r1, r4
datamem
instmem D
B
A
PC
+4
branchcalc
decidebranch
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Control Hazards: Speculative ExecutionControl Hazards• instructions are fetched in stage 1 (IF)• branch and jump decisions occur in stage 3 (EX) • i.e. next PC not known until 2 cycles after branch/jump
StallDelay SlotSpeculative Execution• “Guess” direction of the branch
– Allow instructions to move through pipeline– Zap them later if wrong guess
• Useful for long pipelines
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Loops
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Branch Prediction
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Branch Prediction
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Pipelining: What Could Possibly Go Wrong?
Data hazards• register file reads occur in stage 2 (IF) • register file writes occur in stage 5 (WB)• next instructions may read values soon to be written
Control hazards• branch instruction may change the PC in stage 3 (EX)• next instructions have already started executing
Structural hazards• resource contention• so far: impossible because of ISA and pipeline design
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Goals for TodayRecap: Data HazardsControl Hazards• What is the next instruction to execute if a branch is
taken? Not taken?• How to resolve control hazards• Optimizations
Instruction Variations• ARM• x86
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VariationsMore shifts
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VariationsCondition flags
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VariationsCondition flags
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VariationsCondition flags
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VariationsConditional instructionstop: CMP r3, r4
SUBGT r3, r3, r4SUBLT r4, r4, r3BNE top
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VariationsStack operations & multiple destinations
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VariationsString instructionsMOV AX, FFhMOV DI, 5000hMOV CX, 2000hREP STOSB
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VariationsVector instructionsvaddubs v3, v1, v2
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Next timeInstruction Variations• ARM/MIPS (RISC)• Versus x86 (CISC)