pipeline synchronization continued
DESCRIPTION
Pipeline Synchronization Continued. This second part is based on the recent article Bridging Clock Domains by Synchronizing the Mice in the Mousetrap (PATMOS, Sep. 2003) by Joep Kessels and Ad Peeters Philips Research Laboratories, The Netherlands together with - PowerPoint PPT PresentationTRANSCRIPT
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Avshalom Elyada, Ran Ginosar Pipeline Synchronization 1
Pipeline SynchronizationPipeline SynchronizationContinuedContinued
This second part is based on the recent articleThis second part is based on the recent article
Bridging Clock Domains by Bridging Clock Domains by Synchronizing the Mice in the Synchronizing the Mice in the Mousetrap Mousetrap (PATMOS, Sep. 2003)(PATMOS, Sep. 2003)
byby
Joep Kessels and Ad PeetersJoep Kessels and Ad PeetersPhilips Research Laboratories, The NetherlandsPhilips Research Laboratories, The Netherlands
together withtogether with
Suk-Jin KimSuk-Jin Kim atat KJIST, South KoreaKJIST, South Korea
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Avshalom Elyada, Ran Ginosar Pipeline Synchronization 2
Recall Seizovicâs Recall Seizovicâs Synchronization PipelineSynchronization Pipeline
Seizovic, âPipeline Synchronization,â Async 1994Kessels, Peeters, Kim, "Bridging Clock Domains by synchronizing the mice in the mousetrap", PATMOS, 2003
B clk
⢠Ripple Buffer between two clock domainsâ High throughputâ Embedded synchronizationâ spanning a long distance 2-phase
half cycledistance
A clk
ME
ME
A clk
REQ
ME
B clk
ME
ME
ACK
ME
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Which buffer to use?Which buffer to use?⢠Ripple Buffer
â Stream data (isochronous)â˘Throughput important, latency notâ˘Steady rate maintained on both
sidesâ Short distance (2-3 stages)
â˘Pipe to improve throughputâ or Long distance (many stages)
â˘Improve throughput and bridge distance
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Which buffer to use?Which buffer to use?
⢠Pointer Bufferâ Block data
â˘Chunk available at-onceâ˘Rate not importantâ˘No sense to ripple every word in all
pipe stagesâ˘Write few long bursts to SRAM and
read on other side, with pointers
â But if long distance, need Ripple
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An ME as a SynchronizerAn ME as a Synchronizer⢠Outputs mutually exclusive :⢠Connect ~clk and signal âRâ to inputs⢠âAâ synced output, other output unused⢠Today we refer to ME with ~clk as WAIT4 component
S
clk
XR1
R0
A1
A0
clk
ME
R A
A +
R -
A -
R
Clk +Clk -
Clk=1
Clk=0
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WAIT4WAIT4
â˘A is synced to clk
â˘Used in 4-phase, doesnât sync A
â˘used as building block for 2-phase sync
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One StageOne Stage
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ââMousetrap Mousetrap CellâCellâ
as FIFO as FIFO ElementElement
⢠2-phase single-rail⢠Any hi/lo signal toggle
indicates change⢠reqÇack, sender cell is full⢠req=ack, data accepted by rcver, snder
empty⢠âEqualâ gate implements âemptyâ when
req=ack⢠Cell empty all 4 ctrl signals equal
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MT BehaviorMT Behavior
⢠Ignoring âemptyâ signal,MT similar to Muller Pipeline:
([Rreq=Rack * WreqÇRreq]; Rreq := Wreq)*
Rack
WreqRreqc
Wack
(rcving cell empty)*(sending cell full); capture data, send(rcving cell empty)*(sending cell full); capture data, send
merely prevents idle operationsmerely prevents idle operations
([WreqÇRack * WreqÇRreq]; Rreq := Wreq)*
([WreqÇRack]; Rreq := Wreq)*
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MousetraMousetrap p vs. vs.
MullerMuller⢠Muller
â Need to match delay of req to comb. logicâ For 2-phase, need special Capture-Pass
Latchâ When full, every other cell contains data
⢠Mousetrapâ âemptyâ no need for CP Latchâ âemptyâ does automatic delay-matchingâ When full, all cells contain dataâ No async elements (good for business)
creq
ack
req
ack
c req
ack
Latch
LatchLatch
Latch Latch
Comb.logic
del
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⢠Rcver Ack to Snder does NOT indicate latch locked
⢠Latch locked T(EQ+HoldLatch) after Ack
⢠Timing restraint to ensure data not overrun
1) Snder Full
4) Rcver gets Rack from
outside
5) Rcver empties
EQ
3) Rcver stores data
EQ+HoldLatch
Latch
2)Rcver Ack
back & Rreq
forward
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Delay Delay AsymmetriAsymmetri
es es ⢠Delay of full/empty
tokenâ Full: T(Latch),
Empty: T(Latch+EQ)â Phase-shift in
handshake signalsâ FIFO at full speed is
less than ½ full
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Delay Asymmetries IIDelay Asymmetries II⢠Different inputs of a cell have
different delay-to-outâ Connect slow EQ input to Ack to
help timing, orâ âŚto Req to improve performance
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Delay Asymmetries IIIDelay Asymmetries III⢠Signalsâ rising/falling edges have
different transition delays Req precedes empty,empty
precedes Reqâ To avoid malfunction, ctrl-latch
always slower than data-latch
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UE4UE4
⢠Parallel composition of two WAIT4 -> Up-Edge 4-phase detector
⢠Inv delay ensures 2nd WAIT4 closed before 1st opened
⢠Use a FF here instead?âdoesnât filter out the metastability
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⢠Detect up & down edges for 2-phase⢠Build a Edge 2-phase detector UE2
â âdâ ifferent, âeâmptyâ âUâ even though it is up-and-downâ Note resemblance to MT ctrl logic
UE2UE2
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Pipeline Pipeline InterfacesInterfaces
⢠FIFO indicates ready :â To receive new Wdat: Wrdyâ To send new valid Rdat: Rrdy
⢠Environment enables:â Send of new valid Wdat: Wenbâ Receive of new Rdat: Renb
⢠Data transfer if both rdy and enbâ Transfer item every clock
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Handshaking continues ⌠at next Rclk, state repeats itself
Read-Read-InterfaceInterface
⢠Renb enables Rclk at FFâ Z empty, Rrdy low,
handshake signals equalâ Z becomes full, Rrdy hi,
handshakes differâ Upon next Rclk*Renb,
FF makes handshakes equal again
Following Rclk*Renb, Z passes new Rdat
After T(Latch+EQ), X empties into Y
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Write-Write-InterfaceInterface
⢠Wenb enables Wclk at data+ctrl FFâ âAâ full, handshake
signals differâ âAâ empty, Wack
togglesâ Upon next
Wclk*Wenb,âAâ receives new Wdat
1) C filled from B, ack from C waits at UE2 for Wclk
2) After Wclk, B gets ack, âAâ filled from outside
3) Handshaking continues ⌠at next Wclk, state repeats itself
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Integrated Integrated SynchronizinSynchronizing Circuit in g Circuit in
MT Write CellMT Write Cell
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SummarySummary
⢠Pipeline Synchronizationâ High throughput, embedded sync,
long interconnect, 2-phase
⢠The Mousetrap Cell⢠Synchronization components
â WAIT4, UE4, UE2⢠Buffer Interfaces
â Write and Read sections⢠MT with integrated sync
circuit