pipelining: hazards - cs.utah.edubojnordi/classes/6810/f18/slides/05-pipelining.pdf · overview...
TRANSCRIPT
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PIPELINING: HAZARDS
CS/ECE 6810: Computer Architecture
Mahdi Nazm Bojnordi
Assistant Professor
School of Computing
University of Utah
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Overview
¨ Announcement¤ Homework 1 is duo on Sept. 12th @11:59PM¤ (Late Submission = NO submission)
¨ This lecture¤ Impacts of pipelining on performance¤ The MIPS five-stage pipeline¤ Pipeline hazards
n Structural hazardsn Data hazards
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Pipelining Technique
¨ Improving throughput at the expense of latency¤ Delay: D = T + nδ¤ Throughput: IPS = n/(T + nδ)
Combinational LogicCritical Path Delay = 30
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Pipelining Technique
¨ Improving throughput at the expense of latency¤ Delay: D = T + nδ¤ Throughput: IPS = n/(T + nδ)
Combinational LogicCritical Path Delay = 30
Combinational LogicCritical Path Delay = 15
Combinational LogicCritical Path Delay = 15
Comb. LogicDelay = 10
Comb. LogicDelay = 10
Comb. LogicDelay = 10
D =IPS =
D =IPS =
D =IPS =
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Pipelining Technique
¨ Improving throughput at the expense of latency¤ Delay: D = T + nδ¤ Throughput: IPS = n/(T + nδ)
Combinational LogicCritical Path Delay = 30
Combinational LogicCritical Path Delay = 15
Combinational LogicCritical Path Delay = 15
Comb. LogicDelay = 10
Comb. LogicDelay = 10
Comb. LogicDelay = 10
D = 31IPS = 1/31
D = 32IPS = 2/32
D = 33IPS = 3/33
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Pipelining Latency vs. Throughput
¨ Theoretical delay and throughput models for perfect pipelining
0
5
10
15
20
0 50 100 150 200
Rela
tive
Perf
orm
ance
Number of Pipeline Stages
Delay (D)
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Pipelining Latency vs. Throughput
¨ Theoretical delay and throughput models for perfect pipelining
0
5
10
15
20
0 50 100 150 200
Rela
tive
Perf
orm
ance
Number of Pipeline Stages
Delay (D) Throughput (IPS)
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Five Stage MIPS Pipeline
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Simple Five Stage Pipeline
¨ A pipelined load-store architecture that processes up to one instruction per cycle
Write Back
Inst. Fetch Inst. Decode Execute Memory
Inst.Memory
RegisterFile
ALUData
Memory
PC
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Instruction Fetch
¨ Read an instruction from memory (I-Memory)¤ Use the program counter (PC) to index into the I-
Memory¤ Compute NPC by incrementing current PC
n What about branches?
¨ Update pipeline registers¤ Write the instruction into the pipeline registers
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Instruction Fetch
Memory
PC +
4
NPC
Inst
ruct
ion
Branch Target
PipelineRegister
Why increment by 4?
NPC = PC + 4clock
clock
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Instruction Fetch
Memory
PC +
4
NPC
Inst
ruct
ion
Branch Target
PipelineRegister
Why increment by 4?
NPC = PC + 4
Critical Path = Max{P1, P2, P3}
P1
P2
P3
clock
clock
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Instruction Decode
¨ Generate control signals for the opcode bits
¨ Read source operands from the register file (RF)¤ Use the specifiers for indexing RF
n How many read ports are required?
¨ Update pipeline registers¤ Send the operand and immediate values to next stage¤ Pass control signals and NPC to next stage
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Instruction Decode
RegisterFile
ctrl
PipelineRegister
NPC
NPC
Inst
ruct
ion
PipelineRegister
reg
reg
decode
target
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Execute Stage
¨ Perform ALU operation¤ Compute the result of ALU
n Operation type: control signalsn First operand: contents of a registern Second operand: either a register or the immediate value
¤ Compute branch targetn Target = NPC + immediate
¨ Update pipeline registers¤ Control signals, branch target, ALU results, and
destination
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Execute Stage
ALU
ctrl
PipelineRegister
NPC
Targ
et
PipelineRegister
reg
reg
+
reg
ctrl
Res
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Memory Access
¨ Access data memory¤ Load/store address: ALU outcome¤ Control signals determine read or write access
¨ Update pipeline registers¤ ALU results from execute¤ Loaded data from D-Memory¤ Destination register
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Memory Access
ctrl
PipelineRegister
Targ
et
PipelineRegister
Res
reg
Dat
ctrl
Res
Memory
addr
data data
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Register Write Back
¨ Update register file¤ Control signals determine if a register write is needed¤ Only one write port is required
n Write the ALU result to the destination register, orn Write the loaded data into the register file
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Five Stage Pipeline
¨ Ideal pipeline: IPC=1¤ Is there enough resources to keep the pipeline stages
busy all the time?
+
4
PC+
Mem
Reg.File
ALU
MemReg.File
Inst. Fetch Decode Execute Memory Writeback
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Pipeline Hazards
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Pipeline Hazards
¨ Structural hazards: multiple instructions compete for the same resource
¨ Data hazards: a dependent instruction cannot proceed because it needs a value that hasn’t been produced
¨ Control hazards: the next instruction cannot be fetched because the outcome of an earlier branch is unknown
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Structural Hazards
¨ 1. Unified memory for instruction and data
R1ß Mem[R2]
R7ß R1+R0
R6ß R4-R5
R3ß Mem[R20]
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Structural Hazards
¨ 1. Unified memory for instruction and data
R1ß Mem[R2]
R7ß R1+R0
R6ß R4-R5
R3ß Mem[R20]
Separate inst. and data memories.
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Structural Hazards
¨ 1. Unified memory for instruction and data¨ 2. Register file with shared read/write access ports
R1ß Mem[R2]
R7ß R1+R0
R6ß R4-R5
R3ß Mem[R20]
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Structural Hazards
¨ 1. Unified memory for instruction and data¨ 2. Register file with shared read/write access ports
R1ß Mem[R2]
R7ß R1+R0
R6ß R4-R5
R3ß Mem[R20]
Register access in half cycles.
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Data Hazards
¨ True dependence: read-after-write (RAW)¤ Consumer has to wait for producer
R1ß Mem[R2]
R3ß R1+R0
R4ß R1-R3
Loading data from memory.
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Data Hazards
¨ True dependence: read-after-write (RAW)¤ Consumer has to wait for producer
R1ß Mem[R2]
R3ß R1+R0
R4ß R1-R3
Loaded data will be available two cycles later.
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Data Hazards
¨ True dependence: read-after-write (RAW)¤ Consumer has to wait for producer
R1ß Mem[R2]
R3ß R1+R0
R4ß R1-R3
Nothing
Nothing
Inserting two bubbles.
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Data Hazards
¨ True dependence: read-after-write (RAW)¤ Consumer has to wait for producer
R1ß Mem[R2]
R3ß R1+R0
R4ß R1-R3
Nothing
Inserting single bubble + RF bypassing.
Load delay slot.SW vs. HW management?
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Data Hazards
¨ True dependence: read-after-write (RAW)¤ Consumer has to wait for producer
R1ß R2+R3
R3ß R1+R0
R4ß R1-R6
R5ß R1+R0
Using the result of an ALU instruction.
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Data Hazards
¨ True dependence: read-after-write (RAW)¤ Consumer has to wait for producer
R1ß R2+R3
R3ß R1+R0
R4ß R1-R6
R5ß R1+R0
Forwarding ALU result.
Using the result of an ALU instruction.
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Data Hazards
¨ True dependence: read-after-write (RAW)¨ Anti dependence: write-after-read (WAR)
¤ Write must wait for earlier read
R1ß R2+R1
R2ß R8+R9
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Data Hazards
¨ True dependence: read-after-write (RAW)¨ Anti dependence: write-after-read (WAR)
¤ Write must wait for earlier read
No WAR hazards in 5-stage pipeline!
R1ß R2+R1
R2ß R8+R9
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Data Hazards
¨ True dependence: read-after-write (RAW)¨ Anti dependence: write-after-read (WAR)¨ Output dependence: write-after-write (WAW)
¤ Old writes must not overwrite the younger write
R1ß R2+R3
R1ß R8+R9
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Data Hazards
¨ True dependence: read-after-write (RAW)¨ Anti dependence: write-after-read (WAR)¨ Output dependence: write-after-write (WAW)
¤ Old writes must not overwrite the younger write
No WAW hazards in 5-stage pipeline!
R1ß R2+R3
R1ß R8+R9
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Data Hazards
¨ Forwarding with additional hardware
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Data Hazards
¨ How to detect and resolve data hazards¤ Show all of the data hazards in the code below
R1ß Mem[R2]
R2ß R1+R0
R1ß R1-R2
Mem[R3] ß R2
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Data Hazards
¨ How to detect and resolve data hazards¤ Show all of the data hazards in the code below
R1ß Mem[R2]
R2ß R1+R0
R1ß R1-R2
Mem[R3] ß R2
WAW
WAR
RAW