pixel 2012, inawashiro, ivan peric 1 high-voltage pixel detectors in commercial cmos technologies...

Pixel 2012, Inawashiro, Ivan Peric 1

High-Voltage Pixel Detectors in Commercial CMOS Technologies for ATLAS, CLIC and Mu3e Experiments

Ivan Perić

University of Heidelberg, Germany

Pixel 2012, Inawashiro, Ivan Peric

Overview

• Introduction: The High-Voltage CMOS Sensors and CCPDs• Summary of the older results• New applications:• High-Voltage CMOS Detector for Mu3e experiment at PSI• High-Voltage CMOS Detectors for ATLAS/CLIC at CERN• TEM


High-voltage CMOS pixel detectors


HV CMOS detectors

• We start with a low voltage process:• PMOS and NMOS transistors are placed inside their shallow wells.

PMOS NMOS

Shallow n-wellShallow p-well


HV CMOS detectors

• A deep n-well surrounds the electronics of every pixel.

PMOS NMOS

deep n-well


HV CMOS detectors

• The deep n-wells isolate the pixel electronics from the p-type substrate.

PMOS NMOS

deep n-well

p-substrate


HV CMOS detectors

• Since the pixel-transistors do not “see” the substrate potential, the substrate can be biased low without damaging the transistors.

• In this way the depletion zones in the volume around the n-wells are formed.• => Potential minima for electrons• Charge collection occurs by drift

PMOS NMOS

p-substrate

Depletion zone

Potential energy (e-)

deep n-well

Drift


HV CMOS detectors

• Maximizing of the depleted regions improves performances (less capacitance and noise, more signal) – the best results can be achieved in high-voltage technologies.

• Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60 V and the depleted region depth ~15 m.

• 20cm substrate resistance -> acceptor density ~ 1015 cm-3

PMOS NMOS

p-substrate

Depletion zone


deep n-well

~15µmDrift


HV CMOS detectors

• Maximizing of the depleted regions improves performances (less capacitance and noise, more signal) – the best results can be achieved in high-voltage technologies.

• Example AMS 350nm HVCMOS: Typical reverse bias voltage is 60 V and the depleted region depth ~15 m.

• 20cm substrate resistance -> acceptor density ~ 1015 cm-3

PMOS NMOS

p-substrate

Depletion zone


deep n-well

~15µmDrift

„Smart diode“


Capacitively Coupled Pixel DetectorsCCPDs


Standard hybrid detector

Fu

lly-de

ple

ted

sen

sor

Re

ad

ou

t chip

BumpsMin. pitch ~50 μm

Pixel

Signal charge

Charge signal is transmitted


CCPD with a “passive” sensor

Fu

lly-de

ple

ted

sen

sor

Re

ad

ou

t chip

Min. pitch < 50 μm

Pixel

Signal charge

Signal ~30mV for 250µm thick sensor (Cdet = 100fF)

Voltage signal is transmittedRequires bias resistors on the sensor… that can be implemented as punch-through structure


Active CCPD

Sm

art d

iod

e- o

r fully-d

ep

lete

d se

nso

rR

ea

do

ut ch

ip

Pixel

Signal charge

Signal >30mV for very thin sensors

Sensor implemented as HVCMOSAdvantage: Charge to voltage amplification on the sensor chipTypical voltage signal ~100mVEasier capacitive transmissionCan be thinned without signal loss


Project results


Project history

2006

„Proof of principle“ phase

1) Simple (4T) integrating pixels with pulsed reset and rolling shutter RO(Possible applications: ILC, transmission electron microscopy, etc.)

2) Pixels with complex CMOS-based pixel electronics(Possible applications: CLIC, LHC, CBM, etc.)

3) Capacitive coupled hybrid detectors based on a pixel sensor implemented as a smart diode array

350nm AMS HV technology


Project history

The type 1 chip HVPixelM: Simple (4T) integrating pixels with pulsed reset androlling shutter RO21x21 µm pixel size

Seed pixel SNR 27, seed signal 1200e, cluster 2000e

Spatial resolution 3-3.8µm

Efficiency vs. the in-pixel position of the fitted hit.Efficiency at TB: ~98% (probably due to a rolling shutter effect)


Project history

0 500 1000 1500 20000.0

0.2

0.4

0.6

0.8

1.0

Eff

icie

ncy

Signal [e]

Efficiency - window 800ns

CAPPIX/CAPSENSE edgeless CCPD50x50 µm pixel size

Signals and noise of a CAPSENSE pixel after 1015neq/cm2

Detection efficiency vs. amplitudeDetection of signals above 330e

possible with >99% efficiency.


New projects


Applications:

1) Mu3e experiment at PSIMonolithic CMOS pixels with CSA

2) ATLAS (and CLIC)Capacitive coupled pixel detectors based on smart sensors

3) Transmission electron microscopyintegrating pixels with pulsed reset and rolling shutter RO – in-pixel CDS

4) 65nm UMC LV technology

2006

„Proof of principle“ phase



Sensor concepts

• Pixel electronics is based on a charge-sensitive amplifier and optionally a comparator.• The pixel signal/address is sent as an analog information.• The signal processed by the digital circuits are on the chip periphery or on a separate chip.• 1) Mu3e: The pixel signal is processed on the sensor chip itself -> monolithic pixel detector.• 2) ATLAS: intelligent sensor concept. The pixel address is transmitted to an existing readout chip,

like FEI4 or an strip-readout chip.

ReadoutElectronics

Pixels

ReadoutElectronics


High-voltage CMOS detectors for Mu3e experiment

Collaborating institutes:DPNC Geneva University

PSIParticle Physics ETH Zürich

Physics Institute Zürich University Heidelberg University: Physics Institute, KIP, ZITI


Mu3e experiment

• Mu3e experiment at PSI (Proposal: A. Schöning et. al.)• Search for decay µ+ -> e+ e- e+ (4 orders of magnitude better than previous searches)• This lepton flavor violating decay would be a sign for the theories beyond the Standard Model• Background from other muon decays that generate electron and photons -> 3 electrons and 2

neutrinos• Challenges:• Low electron energy < 53 MeV• High decay rate – 109 µ/s• Good timing resolution• Good momentum resolution – 0.5 MeV/c2 (1T)• Good vertex resolution – 100µm• Little material – 10-3 x0/layer

µ+

W+

γ*

e+

e+

e-

νeνµ

µ+

e+

e+

e-

Standard model: The decay could be the result of the neutrino mixingBranching ratio < 10-50 unobservable

The decay is enhanced (BR 10-16) if one of the following theories apply:Grand unified modelsLeft-right symmetric models Extended Higgs sector Large extra dimensionsBranching ratio < 10-12 (SINDRUM)

?


Mu3e detector

• Proposed: four layers of pixels ~ 80x80m2 size – HV CMOS monolithic detectors• Time stamping with < 100ns resolution required to reduce the number of tracks in an image. • Sensors should be thinned to ~50 m• Triggerless readout• Power ~ 200mW/cm2 cooling with helium• Total area: 1.9 m2

• 275 M pixels• 100 wafers (if 100% yield)

Scintillator tiles

Recurl pixel layers Outer pixel layers

Inner pixel layers

Scintillating fibres

360cm2

3744cm2 7488cm2

B=1T

Al target

µ+


Mu3e detector

Scintillator tiles

Recurl pixel layers Outer pixel layers

Inner pixel layers

Scintillating fibres

B=1T

• Proposed: four layers of pixels ~ 80x80m2 size – HV CMOS monolithic detectors• Time stamping with < 100ns resolution required to reduce the number of tracks in an image. • Sensors should be thinned to ~50 m• Triggerless readout• Power ~ 200mW/cm2 cooling with helium• Total area: 1.9 m2

• 275 M pixels• 100 wafers (if 100% yield)


1cm

2cm

Pixels – active region

~0.5 mmEoC logic

24

Mu3e detector

• The sensors of the size 1 x several cm (2 x several cm outer layers) will be glued onto a self supporting kapton structure and flexible PCBs

• Multi-reticle modules are planned.• We do not need electrical connections between the reticles• The guard rings at the reticle-edges should not lead to insensitivities.• The charge is collected from substrate to nearest pixels.

Kapton PCB &Supporting structure

Thinned chips


1cm

2cm

Pixels – active region

~0.5 mmEoC logic

25

Mu3e detector

• The sensors of the size 1 x several cm (2 x several cm outer layers) will be glued onto a self supporting kapton structure and flexible PCBs

• Multi-reticle modules are planned.• We do not need electrical connections between the reticles• The guard rings at the reticle-edges should not lead to insensitivities.• The charge is collected from substrate to nearest pixels.

Kapton PCB &Supporting structure

Thinned chips


Readout concept for Mu3e

Readout cells

Pixels

• The sensor pixels contain CMOS electronics based on charge sensitive amplifiers.• The amplifier output signals are transferred to the readout cells on the chip periphery.• The readout cells perform comparison with threshold, they store a time stamp when a hit is

detected and they send the data according to the defined priority.• A prototype with the full readout electronics have been submitted in August 2012.• The electronics include:


Sensor pixel

A

LPR

80 µmAmplifier

80 µm


Readout cell

D

4-bit DAC

(CR filter)

In<0:3>

RW

Comparator

BL

Th

TS Memory

S

R

S

R

Priority

Ad

dre

ss

En Read

Rd

TS TSout RAMout

WrIn

x

n

x

HitIn

HitOut


Mu3e test-chip in 180nm technology

30m

39m

0.7m2 metal layers

An

alo

g p

ixels

Dig

ital ch

an

ne

ls

1.8mm

42x36 pixels

Analog pixel layout

Pixel detector chip with a small matrix have been submitted in November 2011 and successfully tested.Pixel size 39x30 micrometers.Separated digital and analog block.Signal time measurements possible.


Signal and noise measurements

• The signal has been measured using various radioactive and x-ray sources.• The capacitive test injection circuit has been used to measure noise and threshold dispersion.• Thresholds can be tuned using in-pixel DACs.

50 100 150 200 250 300 350 4000

50

100

150

200

Nu

mbe

r o

f si

gna

ls

ToT/20ns

Fe55 spectrum0 10 20 30 40 50 60

0

100

200

300

400

500

600

700

800Long windowMean value 36e

Nu

mb

er

of

pix

els

Noise[e]

800 825 850 875 900 925 9500

200

400

600

800

1000 Threshold scanlong windowSigma: 9eMean value: 902e

Nu

mb

er

of

pixe

ls

Threshold[e]


Response speed measurements

• The digital part accepts only the comparator signals that are within the trigger window.• Time resolution tests possible.• Time resolution is the sum of time walk and signal collection time.

Test signal

Ampl. out

Comp out

Window

Test signal

Ampl. out

Comp out

Windowdel1

del2


Time walk measurement

• In-time efficiency vs. signal amplitude (40ns time window).• Detection of signals > 1230 e with 40ns time resolution possible.• Power consumption of the pixel 7.5 µW.• We expect at least 1500 e from MIPs.

0 1000 2000 3000 4000 5000 60000.0

0.2

0.4

0.6

0.8

1.0

40ns windowFit: Mean Val.: 732.20782Sigma: 172.7808

Eff

icie

ncy

Signal [e]


Collection time measurement

• Comparison of the response delay to capacitive test pulse (delay only caused by the amplifier) and the delay to IR pulse (delay caused by the amplifier and collection time).

• To assure that the amplifier delays are equal, we keep the signal amplitudes for both injections the same.

• The amplitudes are measured as ToT.

Test signal

Ampl. out

Comp out

IR laser signal

Ampl. out

Comp out

del2

1400e

1400e

N-well 5µ m

10µ m

60%drift

ToT is proportional to the input charge.It does not depend on the amplifier rise times.

Absorption of 850nm light ~14µmSimilar spatial distribution of the charge generation as for MIPs

Depleted (drift)

40%diffusion


Collection time measurement

• Charge collection time – IR laser, comparison with the fast capacitive injection.• No measurable delay time difference.

0.790 0.795 0.800 0.805 0.81095

100

105

110

115

120

125

130

135

140

145

150 Test pulse IR laser - 850nm

Del

ay [

ns]

Threshold [V]

0 100 200 300 400 40000.78

0.79

0.80

0.81

0.82 Test pulse IR laser - 850nm

Thr

esho

ld[V

]Time[ns]


High-voltage CMOS detectors for ATLAS

Collaborating Institutes (preliminary list): CERN

CCPM Marseille LBNL Berkeley

University of BonnUniversity of Heidelberg


CCPD for ATLAS pixel detector

• We use one of the existing RO chips for the readout of an intelligent HVCMOS sensor.• This approach simplifies the design of sensor and allows us to use the existing readout- and

data-acquisition-systems.• Intelligence: the pixels are able to distinguish a signal from the background and to respond to a

particle hit by generating an address information.

Pixel readout chip (FE-chip)

Pixel sensor

Pixel length = 250 μm

Bump-bond

Pixel electronics based on CSA

Bump-bond pad

We replace the standard bump-bonded sensor with…



• The HV CMOS sensor pixels are smaller than the standard ATLAS pixels, in our case 33μm x 125μm - so that three such pixels cover the area of the original pixel.

• The HV pixels contain low-power (~ 7μW) CMOS electronics based on a charge sensitive amplifier and a comparator.

Glue


Pixel CMOS sensor33x 125 μm

Summing lineTransmittingplate


Bump-bond padCoupling

capacitance

…the capacitive coupled HV CMOS sensor



• The electronics responds to a particle hit by generating a pulse. • The signals of a few pixels are summed, converted to voltage and transmitted to the charge

sensitive amplifier in the corresponding channel of the FE chip using AC coupling.• The FEI4 and HVCMOS sensor are glued onto each other without bump bonding.• Each of the pixels that couple to one FE receiver has its unique signal amplitude, so that the pixel

can be identified by examining the amplitude information generated in FE chip. • In this way, spatial resolution in - and z-direction can be improved.

Glue


Pixel CMOS sensor33x 125 μm

Summing lineTransmittingplate


Bump-bond padCoupling

capacitance


Advantages compared to existing detectors

• No need for bump-bond connection between the sensor and readout chip – lower price, better mechanical stability, less material.

• Commercial technology – lower price.• No need for bias voltages higher than 60V.• Operation at temperatures above 0C is according to tests possible (irradiations to 1015 neq/cm2).

• Increased spatial resolution (e.g. 25m x 125m binary resolution) with the existing FE chip• Smaller clusters at high incidence angles. • Possibility of sensor-thinning without signal loss. Since we do not use bumps and FE chips can

be thinned as well, the amount of material would be very low. • Interesting choice for other experiments where low-mass detectors are needed such as CLIC,

ILC, CBM, etc...


HV2FEI4

• Pixel matrix: 60x24 pixels (readout by 20 x 12 FEI4 pixels)

• Pixel size 33 m x 125 m.

Strip pads

IO pads for CCPD operation

IO pads for strip operation

Pixel matrix

4.4

mm


CCPD operation

2

3

1

2

3

1

Bias A

Bias B

Bias C

FEI4 Pixels

CCPD Pixels

Signal transmitted capacitively


Pixel electronics

A

D D

CCPD bus

Strip bus

4-bit DAC

(CR filter)

Programmable current

SelectG

G

GIn<0:3>

RW

SFOut

Cap. Injection

Amplifier

Filter

NMOS Comparator V-I convertor

CCPD electrode

BL

Th

Resistance


6 pixels – layout

Comparator

Amplifier

Tune DAC

33 µm


Measurement setup


Measurements with active pixels

Injection

HVCMOS

FEI4

Test pad

1700 1800 1900 2000 2100 2200 23000.0

0.2

0.4

0.6

0.8

1.0Mean Val.: 1997.8 esigma: 169.6 e

Nu

mb

er

of

Hits

Injected signal [e]


Measurements with 22Na beta source


Conclusion

• The HVCMOS technology has first planned applications: • Search for Mu->3e decay at PSI.• 1.9m2 , 50 µm thin monolithic pixel sensor is planned, about 270M of 80x80 µm pixels.• Readout is based on time stamps, time resolution 100ns.• A test-chip with simplified readout and small pixels has been tested (measured time resolution <

40ns, noise 40 e). • Test beam measurement done – first results soon.• A larger prototype with full readout electronic have been submitted in August 2012.• Engineering run is planned after the evaluation of the prototype.• LHC experiments ATLAS.• The concept: Intelligent sensors in HVCMOS technology readout by the existing readout ASCIs –

capacitive coupled hybrid detectors.• First module with a HVCMOS chip glued onto a FEI4 ROC works, the noise still high due to non-

optimal setup.• Test beam is planned.• First measurements with a strip readout chips will be done soon.• Irradiation ongoing.• Measurements with HVCMOS chip glued onto TimePix soon.• If the results are fine, we will submit a larger sensor within an engineering run.• Another application for HVCMOS (SDA) detectors: TEM.


Implementation of “smart diodes” in 65nm technology- 2.5 µm pixels


Pixel detector in 65nm technology

55Fe measurement Shadow of 16 m thick golden bonding wire

16µm

• The first “smart diode” (SDA)-detector implemented in a low-voltage (UMC 65nm) CMOS technology.

• The pixel size is only 2.5 x 2.5 micrometers. • We measure a very low noise - an effect of the small diode capacitances.• X-ray shadow image of a small object

Pixel matrix (32x256)


Four transistor pixels

Res Res

Sel

1.1 V

Sensordiode

1.1 V

Reset V.

OutDeep n-well

Transistors

Depleted p-substrate between and underneath n-wells (white area)

Input of the amplifier

N-well contact

2.5 µm

• The pixel electronics is based on 4 PMOS transistors, the pixel output signal is current. • The readout is of rolling-shutter type, the column signals are compensated for offsets on the chip

using 8-bit DACs and compared with a threshold.


Complementary “smart diode”

• Complementary structure – “smart” Pwell in Nwell diode (electronics based on NMOST)• Only the charge generated in the depleted region of a thickness 2.5-5 µm near the chip surface

are collected.• Reduced charge sharing

NMOS

20-50V

6.5 µm2.5 µm

4 µm

Not collected

Collected


Development for the transmission electron microscopy


HPIXEL

-20 0 20 40 60 800.0

0.2

0.4

0.6

0.8

1.0

Nu

mb

er

of

hits

Signal (ADU)

Base line Guassian fit, sig. 2.2 (111e) Fe55 spectrum (peak 33)

• HPixel: an HVCMOS detector with small pixels (25x25 µm) in 180nm AMS HV-technology.• The readout is of rolling-shutter type. • The detector has been successfully tested using various radioactive sources. The signal and

noise have been estimated.


Integrating pixels with CDS

Out

VP

Res

Res Sel

VP

Sel

Sample

Sel

25 µm

• Correlated double-sampling (CDS) is implemented in the pixels using CMOS electronics. The pixel output signals are digitized by 128 on-chip ADCs.

• The readout electronic has been optimized for a fast readout and a low power consumption.



Reset level

VP

Res

Res Sel

VP

Sel

Sample

Sel

25 µm



Reset l.

Signal l.



Signal level

VP

Res

Res Sel

VP

Sel

Sample

Sel

25 µm



Signal l.

Signal l.



VP

Res

Res Sel

VP

Sel

Sample

Sel

25 µm



Reset l.



VP

Res

Res Sel

VP

Sel

Sample

Sel

25 µm



Reset l.

Irradiation


Thank you


Backup slides


Measurements with a test pad

Injection

HVCMOS

FEI4

Test pad


Measurements with a test pad

0.577V -> 2964e =>Capacitance = 0.824fF

0.50 0.52 0.54 0.56 0.58 0.60 0.620.0

0.2

0.4

0.6

0.8

1.0 Mean Val.: 0.57566 VSigma: 0.01463 V

Re

spo

nse

pro

ba

bili

ty

Test pulse [V]

1550 1600 1650 1700 1750 1800 1850 1900 19500.0

0.2

0.4

0.6

0.8

1.0 Mean Val. 1745.0 esig 73.0 e

Re

spo

nse

pro

ba

bili

ty

Injected charge [e]

Calibrated input: FEI4 noise 73e(FEI4 threshold was set to 1300e)


Technology issues – sensor capacitance

• Relatively large size of the collecting electrode.• The high-voltage bias reduces the problem.• Example – large pixels for ATLAS:

N-well

P-well

110 μm15μm

~30fF

~70fF

C_area = 0.015fF/μm2

C_sw = 0.18fF/μm

C_area = 0.148fF/μm2

C_sw = 0.385fF/μm

10 μm

60V

Total :100fF


Technology issues – crosstalk

PSUB

DN

PWNW or SN

1.8v

DP

1.8v NMOSPMOS

• Capacitive feedback into the sensor (n-well)• Many important circuits do not cause problems: charge sensitive amplifier, simple shaper, tune

DAC, SRAM but… • “Active” (clocked) CMOS logic gates and sometimes comparators cause large crosstalk• Possibility 1: Implement the circuits only using NMOST: effects on radiation tolerance, layout

area, power consumption, etc.• Possibility 2: Place the active digital circuits on the chip periphery or on separate chip.• Possibility 3: Isolate PMOST from n-well using an additional standard technology feature – the

deep P-well – we still haven’t tested it…


CMOS pixel flavors

• CMOS pixel flavors:

Standard MAPS INMAPS

„HVMAPS“ – HVCMOS or SDA TWELL MAPS


HV CMOS detectors

• Collected charge causes a voltage change in the n-well.• This signal is sensed by the amplifier – placed in the n-well.

PMOS

N-well

NMOS

DS

G

holes

electrons

P-well

P-substrate


HV CMOS detectors


P-substrate


HV CMOS detectors

P-substrate



HV CMOS detectors

• Charge sharrng due to diffusion

PMOS NMOS

Depletion zone

60V ~15µm

deep n-well

Drift


PMOS isolation

PMOS

STI - FOX

SN

DP

DN

180 nm technology


PMOS isolation

PMOS

STI - FOX

SN

DP

DN

180 nm technology

Short???


Drawbacks

PMOS

LOCOS - FOX

SN

DP

DN

350 nm technology


Complementary structure for TEM

• Complementary structure – smart Pwell in Nwell diode (electronics based on NMOST)• Only the charge generated in the depleted region of a thickness 2.5-5 µm near the chip surface

are collected.• Reduced charge sharing.

P-substrate

N-well

NMOS

P-well

2.5 µm

pixel 2012, inawashiro, ivan peric 1 high-voltage pixel detectors in commercial cmos technologies...

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