pl7 1 language

1

Section Page

PL7-1 Language ContentsX

1 PL7-1 Language 3

1.1 Presentation 3

1.2 I/O Addressing 4

1.3 Operands 5

1.4 Operation Codes 7

1.5 PC Scan Cycles 9

2 PL7-1 Language : Structure and Functions 11

2.1 Characteristics 11

2.2 Timer 12

2.3 Counter 13

2.4 Shift Register 14

2.5 Step Counter 15

2.6 Fast Counter/Timer (TSX 17-20 only) 16

3 PL7-1 Language : Grafcet 17

3.1 Characteristics 17

3.2 Program Structure 18

4 Program Utilities 19

4.1 Mains Power Break/Return 19

4.2 Initialization of the PC 20

4.3 Program and Data Back-up Storage 20

4.4 RUN/STOP Input and SECU Output 20

4.5 Diagnostic Aids 21

4.6 Application Operating Modes 22

4.7 Programming Guidelines 23

4.8 Programming Examples and Rules 24

2

Section Page

X

5 Appendix 25

5.1 Operation Code/Operand Associations 25

5.2 Execution Times 26

Index 27

2 PL7-1 Language: Structure and functions 2

11

A PL7-1 language instruction occupies one memory address and is composed of:A memory address An operation code + An operand

Example : S 0004 A I0,03

A list of instructions is divided into 2 parts :

- One part for the test instructions,

- One part for the action instructions.

The number of test or action instructions is not limited.

The number of lines (i.e. instructions) that can be used is limited by the size of thememory, as follows :

Micro-PC 8 K Memory 24 K Memory

TSX 17-10 925 (from S0000 to SO924)TSX 17-20 925 (*) 2973 (*)

(*) If the Fast task is used, the number of lines of the Master task is reduced by the number of linesof the Fast task.

Example : With an 8 K memory : Master task = from S0000 to S0918Fast task = from F0000 to F0006

The processor reads and executes the instructions in the ascending order of theiraddresses, up to the instruction EP (end of program).Program jump : JMPi and LABiThe execution of the operation code JMPi immediately jumps the program scan tothe line containing the operation code LABi and the part of the program betweenJMPi and LABi is not executed. JMPi and LABi must have the same number; thisnumber has no relation to the line number.

This function simplifies the logic operations A, AN, O, ON, XO between two seriesof instructions.Principle: Before the execution of each L or LN instruction, the logical result ismemorized in IM until the next L or LN instruction.

Program Equivalent program (without the use of “IM”)

2.1 Characteristics

Instructions

Program scan

"IM” function

Example

I0,01 I0,02 O0,06

I0,03 I0,04

Program memory

1

2

2 PL7-1 Language: Structure and functions

12

The Timer function permits the time-delayed control of specific actions. The value ofthe time-delay is programmable and can be modified by the TSX T317 terminal in theAdjust mode (ADJ).

Number 32 (from T00 to T31)Time bases (Ti,B) 4 (10ms, 100ms, 1s, 1mn)Preset value (Ti,P) 0000 to 9999

L, LN, A, AN , tests of the state of the timer (running 0, or done 1).O, ON, XO

= Ti start on state 1 and run while the condition = 1= NTi start on state 0 and run while the condition = 0S Ti start on state 1 and run till timed outR Ti initialization of the timerH Ti halts the timer while the condition = 1

On-delay timer

Use of the operation code =

Use of the operation codes S and R

Remarks : . A program jump over a timer, or the stopping of the PC, does not halt therunning of a timer.

. In the Adjust mode, the current value Ti,V is at 0 if the timer has timed out, hasnot been started, or has been initialized by the operation code R.

. On a cold restart, the current value is reset to 0 and the preset value Ti,P is thevalue that was defined in the Configuration mode (the adjustment value is lost).

2.2 Timer

Characteristics

Test operation codes

Action operation codes

Example

Presentation

Time delay


13

2.3 Counter

PresentationThe counter function permits the upcounting or downcounting of external or internalevents. The preset value can be modified by the TSX T317 terminal in the Adjustmode.

Number 15 (from C00 to C14)Preset value (Ci,P) 0000 to 9999.

L CiK tests of the state of counter i in relation to constant KLN CiK (from 0000 to 9999)

S CiK set counter i to constant K (from 0000 to 9999)R Ci reset the counter to 0CU Ci incrementation on a rising edgeCD Ci decrementation on a rising edge

Since equality is not always the desired condition, the system positions system bitSY17 as follows :. SY17 = 0 if the counter value constant K,. SY17 = 1 if the counter value < constant K.Thus providing 4 additional functions (>, <, , ).

Remarks : . The system bit SY17 can be used several times in the program for one ormore counters. It always affects the counter Ci immediately upstream of theoperand SY17.

. When the counter reaches its preset value (Ci,P) it is automatically reset to0000.

. On a cold restart, the current value is reset to 0000 and the preset value(Ci,P) is the value that was defined in the Configuration mode (the adjustment value is lost).

Characteristics



System bit SY17

Examples

≥

≥ ≤

L C00 K00123

LN C00 K00123

LN C00 K00123AN SY17

Counter C00 equal to 123

Counter C00 different from 123

Counter C00 more than 123

LN C00 K00123A SY17

L C00 K00123ON SY17

L C00 K00123O SY17

Counter C00 less than 123

Counter C00 more than or equal to 123

Counter C00 less than or equal to 123


14

The shift register is a register which enables binary data bits to be moved a prescribednumber of positions to the left or right as a contiguous group.

Number of registers 8 (from SR0 to SR7)Number of bits in a register 16 (from SRi,00 to SRi,15)

L, LN, A, AN tests of a register bit,O, ON, XO

= SRi,j assignment of a state (or its inverse) to a register bit,= N SRi,jS SRi,j sets a register bit to 1,R SRi,j resets a register bit to 0,R SRi resets the 16 bits of a register to 0,CU SRi on a rising edge, shifts the bits one place to the left,CD SRi on a rising edge, shifts the bits one place to the right.

Initial state :

CU SRi shifts the bitsone place to the left

The bit shifted out(bit 15) is lost :

Similarly, CD SRi shifts all the biits of the register one place to the right, in this casethe bit shifted out is bit 00.

If more than 16 bits have to be shifted, several registers can be cascaded in theprogram.

Shift the register one place to the left every second. Bit 00 must take the inverse stateof bit 15.

Program

Remark : On a cold restart, the bits of each register are reset to 0.

2.4 Shift register

Presentation

Characteristics



Operation

Example


15

2.5 Step counter

Presentation

Characteristics



Operation

Input CU

Output CD

No. of step at 1

A step counter is a series of steps which can be associated with actions. The progressfrom one step to another can be controlled by internal or external events.Only one step of a step counter can be at state 1.

Number of step counters 8 (from SC0 to SC7)Number of steps of a step counter 256 (from SCi,000 to SCi,255).

L, LN, A, AN tests of the state of a step of a step counterO, ON, XO

S SCi,j sets step j of step counter i to 1CU SCi on a rising edge, increments by one step (from 000 to 255)CD SCi on a rising edge, decrements by one step (from 255 to 000)

Program step counter 0 to be incremented by input I0,02 and to be reset to 0 by inputI0,03 or when it reaches step 3.

Step 0 controls output O0,01, step 1 controls output O0,02 and step 2 controls outputO0,03.

Program

setting to step 000

incrementation

activation of the outputs

Remark : On a cold restart, the active step is reset to 0 and step 0 of each step counteris set to 1.

Example


16

2.6 Fast counter / Timer (TSX 17-20 only)

PresentationThe TSX 17-20 micro-PC is equipped with a fast counter C15 which, depending onthe way it is configured, can be used as a fast counter or a fast timer. The preset valueis defined in the Configuration mode and can be modified by the terminal in the Adjustmode, or by the program with the operation code S.

. Fast counter (configuration by default) :The maximum frequency of the counter is 2 KHz. It has two physical inputs (acounting input and a reset input) permitting the connection of 5VDC and 24VDCsensors. Counting : 10 000 points.

. Fast timer :In the fast timer, an internal time base of 0.555ms replaces the physical countinginput. A rising edge on the reset input resets the current value of the timer to 0.

L C15K tests of the state of the counter in relation to constant KLN C15K (from 0000 to 9999).SY 17 see Section 2.3.S C15K modification request of the preset value K. This new value is

acquired after the counter has reached the preset value that it hadwhen the modification request was made.

R C15 resets the counter to 0 and resets the preset value to the value thatwas defined in the Adjust or Configuration modes.

When the fast counter C15 reaches its preset value :. system bit SY15 is set to 1,. the Fast task is executed if system bit SY19 has been reset to 0 in the Master task,. the counter is reset to 0.Caution: System bit SY15 must be reset to 0 by the user program.

The 9-pin D-type connector in the top left corner of the TSX 17-20 has twoindependent, isolated inputs :

. Fast counting input :0V = pin 1; 5V = pin 7; 24V = pin 6

. Reset input :0V = pin 5; 5V = pin 8; 24V = pin 9

Remarks . Resetting of the counter to 0 by the physical input resets the current valueonly (the preset value is retained).

. By associating the fast counter with a step counter (in which each step isloaded with a value K), a fast counter with multiple preselections can beobtained.

. On a cold restart, the current value is reset to 0 and the preset value is thevalue that was defined in the Configuration mode.

System bit SY 15

Test and action operation codes

Characteristics

Connecting the fast counter

3 PL7-1 Language: Grafcet 3

17

8

I0,07

9

11

I0,08

13

=1

10

12

I0,09

3.1 Characteristics

Presentation

Instructions

Examples

14

I0,10

15

17

I0,11

18

I0,12.

16

I0,13

I0,14

4

I0,03

5

7

I0,05

I0,04

6

I0,06

1

I0,01

2

3

I0,02

The PL7-1 language comprises 62 Grafcet steps maximum, including the initialsteps. Within this limitation, the number of simultaneously active steps is unlimited.

=*= i initial step i (*),-*- i step i (*),# deactivation of the current step without activation of any other step,# i activation of step i after deactivation of the current step,=*= POST start of Post-processing and end of Sequential processing,X i read/write bit associated with step i.

(*) The first step =*= i or -*- i that is written indicates the start of Sequentialprocessing and therefore the end of Pre-processing.

Linear sequence Sequence selection

Simultaneous sequences

3 PL7-1 Language: Grafcet

18

3.2 Program Structure

A PL7-1 Grafcet program is structured in 3 parts, each of which has aspecific role :

PL7-1 Grafcet program

Conditions and actions

Sj+1....

EP

Post-processing

Sk

=*= POST

S000....

....

....Pre-processing

Sn

....L

Sn+1....

....

Sequential processing

Sj

=*= i

Pre-processing := a series of instructions.RoleProcessing of :- mains break/return,- failures,- application operating modes:

. init : by system bit SY21,

. reset : by system bit SY22,

. prepositioning of the Grafcet by systembits SY22 and SY23,

. freezing of the Grafcet by system bitSY23,

- input logic.

Sequential processing := a series of instructions.RoleSequential processing of the application :steps and transitions and their associatedactions and conditions.

Post-processing := a series of instructions.RoleThe processing of :- the commands from the Sequential processing section concerning

Master task

the control of the outputs, - the output safety interlocks.

The scan cycle is defined in Section 1.5. Only the steps that are active (or to beactivated or deactivated) and their associated instructions are executed in theSequential processing section.Reminder : Grafcet instructions must not be used in the Fast task.

The transition conditions associated with step i are written after the step instructions-*-i or =*=i.The actions associated with the steps can be written either :. In the Sequential processing section, after the step instruction and before the

transition conditions, by using the instructions S and R (scanned when the step isactive).

. In the Post-processing section, after the instruction Xi (scanned on each cycle).

This solution is recommended in the case of outputs linked to safety interlocks.


19

4.1 Mains power Break/Return

. < the autonomy of the power supply: normal execution of the program,

. > the autonomy of the power supply: processor de-energized, with :- saving of the context (program, data, I/O) if the PLC is equipped with a back-up battery,- without a battery, the context is saved for a minimum of 1 hour.

Possible causes :

. mains return after a break of > autonomy of the power supply,

. system bit SY01 set to 1 by the terminal or the program.

Consequences :

. system bit SY01 set to 1,

. all outputs reset to 0 (*),

. unsaved internal bits (B128 to B255) reset to 0,

. saved internal bits (B000 to B127) and Grafcet steps retain their states, and timers,counters, shift registers and step counters retain their values,

. the scan restarts from where it stopped but without updating of outputs at the endof the cycle, the next cycle is executed normally (inputs, program, outputs) andSY01 is reset to 0 by the system.

(*) with PLC software versions earlier than V1.2, all output states are saved.

Possible causes :

. back-up battery defective or absent,

. change of user program back-up cartridge,

. system bit SY00 set to 1 by the terminal or the program,

. initialization of the PLC by the terminal.

Consequences :

. system bit SY00 set to 1,

. all internal bits, I/O bits and current values of functions are reset to 0 (registers at0, step counters at step 0, etc.),

. loss of the adjustment values modified by the terminal and resetting to the valuesdefined in the Configuration mode,

. cancellation of forcings,

. acknowledgement of an I/O fault,

. reinitialization of the Grafcet,

. the scan restarts at the start of the cycle (inputs, program, outputs) and system bitSY00 is reset to 0 by the system.

Remark The Fast task cannot be executed until system bits SY00 and SY01 have beenreset to 0, i.e. not until after the execution of the first complete cycle.

Characteristics of mains power breaks

Hot restart : the context is coherent (program and data)

Cold restart : loss of context (data or program)

4 Program Utilities

20

4.2 Initialization of the PC

PresentationThe PC can be initialized by program by setting system bit SY00 to 1 which cor-responds to a cold restart (see Section 4.1). During a hot restart, it may benecessary to initialize the PC, the example below shows how this can be pro-grammed. The PC can also be initialized by the terminal.

L SY01 If SY01 = 1 (hot restart) then set SY00 to 1 to initialize the PC.S SY00 These two bits are reset to 0 by the system at the end of the next

cycle.

The program and data are stored in the RAM memory of the PC. This memory hasan autonomy of 1 hour. The autonomy of the RAM can be increased to 2 years byinstalling a TSX 17 ACC1 lithium back-up battery (refer to the installation manual).For permanent back-up storage, the user program can also be transferred to a TSXMC70 E38 or E324 EEPROM memory cartridge.

Copying the program to an EEPROM memory cartridge is not mandatory, but isrecommended since it prevents the risk of alterations to the user program due tomains breaks or battery defects.On power up, the PC compares the RAM and EEPROM programs. If they are notidentical, the program in the EEPROM is automatically transferred to the RAMmemory.

The input I0,00 and the output O0,00 of the basic PC module can each be configuredeither as normal I/O or for special functions :

Can be set in the Configuration mode to either :Normal : Normal operation as for any other input,RUN/STOP: State 1 = PC running, program being executed,

State 0 = PC stopped, program halted.

Can be set in the Configuration mode to either :Normal : Normal operation as for any other output,SECU : State 1 = PC running,

State 0 = PC stopped or failed.This output can be used in external safety circuits.

Remarks . IO,00 and O0,00 must be used in the program only for the function thatwas selected in the Configuration mode.

. The RUN/STOP input has priority over a RUN/STOP command from theterminal.

Example

Presentation

4.3 Program and data back-up storage

EEPROM memory module

Presentation

4.4 RUN/STOP input and SECU output

Input I0,00

Output O0,00


21

4.5 Diagnostic Aids

PresentationThe operands described below can be used in the program to facilitate troubleshoot-ing of the PC or the application.

SY10 = 0 : I/O module fault or configuration fault,

SY13 = 1 : Back-up battery absent or defective.

Value of x: 0 : Basic PC module,1 : 1st extension module,2 : 2nd extension module.

Sx,0 = 1 : I/O fault or exchange fault in module x.

Sx,1 = 1 : Sensor voltage fault in module x.

Sx,2 = 1 : Input circuit fault in module x.

Sx,3 = 1 : Short-circuit on the static outputs of module x.

Reminder : System bit SY16 at 1 requests the reconnection every 10seconds of the static outputs disconnected by overvoltageshort-circuit.

Sx,4 = 1 : Internal power supply fault of the coils of the relay outputs ofmodule x.

Remarks . State 1 of any of these fault bits causes :- resetting to 0 of system bit SY10,- illumination of the I/O fault light.

. If the I/O light stays on and SY10 stays at 0 after the fault has beencorrected, use the terminal to initialize the PC.

The significance of the status lights on the front panel of the basic PC variesaccording to the state of system bit SY14 :

SY14 = 0 : MD light out,display of outputs O0,00 to O0,15 (or O0,00 to O0,07 for the TSX 17-10 with 20 I/O),

SY14 = 1 : MD light on,display of internal bits B255 to B240 (or B255 to B248 for the TSX17-10 with 20 I/O).

System biits

Fault bits Sx,j

Display of internal bits B240 to B255

4 Program Utilities

22

Power-upInitialization

Change of moderequest

Input logic

Processing

Processing

YES

NO

NO

YES

4.6 Application Operating Modes

The PL7-1 software enables the operating modes of the application to be organizedin three main groups :

. Checking,

. Operation or production,

. Stopping.

These different operating modes can be obtained by using the following possibilitiesof the Grafcet language :

. Initialization of the Grafcet,

. Resetting of the Grafcet,

. Presetting of the Grafcet,

. Freezing of the Grafcet.

Use of the Pre-processing section and the system bits facilitates control of theapplication operating modes without complicating the program.

The flowchart below shows the structure that should be given to the Pre-processingsection, which is divided into three sub-assemblies as follows :

. Power up,

. Change of mode request,

. Combinational input logic

The Grafcet system bits SY21, SY22 and SY23 must be used only in the Pre-processing section. These bits are automatically reset to 0 by the system and mustbe written by using operating code S only.

Initialization of the Grafcet, SY21Causes :. a hot restart (see Section 4.1),. SY21 set to 1 by the program or the terminal.

Consequences :. deactivation of all the active steps and activation of all the initial steps.

Structure of the Pre-processing section

Grafcet system bits


23

Application Operating Modes (Cont'd.)

Resetting to 0 of the Grafcet, SY22

Cause :. SY22 set to 1 by the program or the terminal.

Consequences :. deactivation of all the active steps,. stopping of the scan of the Sequential processing section.

Presetting of the Grafcet, SY22 and SY23

Procedure :. reset the Grafcet to 0 by setting SY22 to 1,. preset the steps to be activated by S Xi,. validate the presetting by setting SY23 at 1.

Freezing of the Grafcet

. in its initial state, by holding SY21 at 1 by the program,

. in an “empty” state, by holding SY22 at 1 by the program,

. in a predetermined state, by holding SY23 at 1.

Jump instructions should be used with caution. Avoid upstream jumps and avoid longloops in the program which could increase the scan time. Do not make jumps fromone task to another.

Each output bit or internal bit must be turned on or off only once in the program, sinceonly the last state that is scanned is taken into account when the outputs are updatedat the end of the scan cycle.

Sensors that are used in direct safety circuits must not be processed by the PC, butmust be free to act directly on the corresponding actuators.

An automatic restart of the application after a mains power return could be highlydangerous. Users are therefore strongly recommended to make the restarting of theapplication after a mains power return conditional on a manual operation.

Use of jump instructions

Programming of outputs

Field safety sensors

Power return programming

4.7 Programming Guidelines

4 Program Utilities

24

4.8 Programming Examples and Rules

Rules of association of the operation codes

The operation requested by the code A, AN, O, ON or XO is always effected with the logical result of the previous line.

The operation code L or LN always stores the logical result of the previous line in the IM memory until the next operation code L or LN is encountered.

I0,02 I0,05 O0,01

I1,00

B017

X22 O0,02

X5 I0,02 O0,01I0,05 O0,02

I0,02 B017 I1,00

5 Appendix 5

25

5.1 Operation Code and Operand Associations

Operands I/Oi,j Bi SYi Ti Ci SCi Sci,j SRi SRi,j IM Xi SOperations [SC] [SR]

L,LN X X X X X(k) - X - X - X X

A,AN X X X X - - X - X X X X

O,ON X X X X - - X - X X X X

XO X X X X - - X - X X X X

P - X - - - - - - - - - -

S X X X X X(k) - X - X - X -

R X X X X X - - X X - X -

S* X X - - - - - - - - X -

R* X X - - - - - - - - X -

=,=N X X X X - - - - X - X -

=* X X - - - - - - X - X -

CU - - - - X X - X - - - -

CD - - - - X X - X - - - -

H - - - - X - - - - - - -

JMP from 1 to 127LAB

=*=”i” initial steps -*-”i” Grafcet steps i = 1 to 62# “i” transitions

=*= POST Post-processing

EP

NOP

X = Possible associations - = Impossible associations

exceptC15

5 Appendix

26

General

5.2 Execution Times

Table of execution times

µµ

The difference between the minimum and maximum execution times depends on thestate of the operand scanned by the processor, the appearance or not of a rising orfalling edge, and whether or not compilation or interpretation are necessary.

Operation code Operand Minimum Maximum( sec.) ( sec.)

L,LN I; O; B; SY; X; T; S 6 (*) 6 (*)C (kxxxx) 40 51SCi,j; SRi,j 18 18

A,AN,O,ON I; O; B; SY; X; IM; T; S 2 6SCi,j; SRi,j 5 6

XO I; O; B; SY; X; IM; T; S 4 6SCi,j; SRi,j 6 6

P B 19 21S I; O; B; SY; X 2 6

T 2 50C 2 35SCi,j; SRi,j 2 5

R I; O; B; SY; X 2 6T 2 31C 2 35SCi,j; SRi,j 2 18

S* I; O; B; X 2 19R* I; O; B; X 2 20=* I; O; B; X 21 21=,= N I; O; B; X 6 6

T; SRi,j 32 50CU,CD C 14 40

SCi 14 19SRi 14 27

H T 26 28N 3 3JMPi 2 23LABi 11 14=*=, -*-# 2 14NOP 2 2EP 2 2

(*) For a program written in the Fast task, add 8 microseconds to the above executiontimes for the operation codes L and LN assigned to the operands I, O, B, SY, X,T and S.

Index

27

B Battery 19,20

D Diagnostics 21Display of internal bits B240 to B255 6,21

E Event-triggered inputs 4,10

F Fast task 6,10Faults 6,20,21Fault bits 5,21

G Grafcet 6,8,9,17,19,22

I Initialization of the Grafcet 22Initialization of the PC 20Internal bits 5,7,21I/O addressing 4

M Master task 9,10Mains power break/return 6,19,20,22,23

P Printing 3,5Program and data storage 20program jumps 8,10,11,23Program memory 11

R RUN/STOP input 4,20

S Scan cycles 9,10SECU (safety) output 4,20System bits 6

T Transfers to/from EEPROM memory 20,36

W Watchdog 9

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