pla minimization and testing

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Digital System Design

Unit-IV : PLA Minimization And Testing

PLA Minimization-– PLA folding

4.1 PLA Minimization

The canonic sum-of-products implementation of a logic function is

wasteful in two ways: in the number of AND gates used (as many as there are minterms,

2n) and in the number of inputs to each AND gate (n). Suppose we contemplate a

reduced (possibly minimal) sum-of-products implementation. Given a logic function of n

variables, the largest number of terms in a minimal sum-of-products expression

representing this function is 2n–1—just half the number of minterms. That means a

savings of 50 percent in AND gates for the worst single-output case. Since there will be a

reduced set of inputs to the AND gates, this saving in gates is paid for by the need to

program not only the outputs of the AND gates but their inputs as well.

The structure of the circuit that results is called a programmable (or programmed) logic

array (PLA). It is illustrated in Figure 23 for the case n = 3 input variables, m = 4 out-put

functions, and four AND gates. The diagram in Figure 23 is not a circuit diagram but a

schematic diagram. A single line is shown to represent all inputs to each AND and OR

gate. The number of input lines to each AND gate should be 2n, twice the number of in-

puts, to accommodate the possibility of connecting each variable or its complement to

each AND gate. The number of input lines to each OR gate should equal the number of

AND gates, say p. (For simplicity and without fear of confusion, even the gate symbols

can be omitted.) The programmed connections between the inputs and the AND gates,

and between the AND-gate outputs and the OR gates for a specific set of output functions

are shown by the heavy dots at the intersections.

Department of E.C.E, MRITS, Hyd. 1




Figure 1: Structure of a PLA

Maps of the four output functions and minimal sum-of-products expressions are shown in

Figure 24. In this example, a total of only four product terms covers all functions, so only

four AND gates are needed in the implementation. Two sets of lines must be

programmed: the input lines and the output lines. To do this, we construct a programming

table as follows:

• The implicants (product terms) are listed as row headings.

• In one set of columns, the headings are the input variables; this part of the

table must provide the information that tells which variables (or their com-

plements) are factors in each implicant.

• In a second set of columns, the headings are the output functions; this part of

the table must provide the information that indicates the output gate to

which each implicant (AND-gate output) is directed.





In the first set of columns, if a variable (uncomplemented) is present in a particular row,

the corresponding entry is 1; if its complement is present, the entry is 0. If neither is

present, the entry can be left blank, but it is preferable to show some symbol instead; a

dash is often used. In the second set of columns, corresponding to the output functions, if

a particular function covers a particular implicant, then the corresponding entry is 1;

otherwise it could be left blank, but it is customary to enter a dot. To illustrate, consider

row 4. Since the implicant is y'z, the entry in column z is 1, that in column y is 0, and that

in x is a dash. In the output columns, only f1 does not cover implicant y'z; hence, the

entry will be 1 in every column in row 4 except the f1 column, where the entry is •.

Confirm the remaining rows.Once the programming is done, fabricating the links

(connection points) in a PLA is carried out in a similar manner as for the ROM. The PLA

is either mask programmable or field programmable (FPLA). In the case of the FPLA,

with p = the number of AND gates, there will be 2np links at the inputs and mp

Figure 2 Programming the PLA

links at the outputs.For the example in Figure 1,the number of links is 4(6 + 4) = 40. Only

16 of these are to be kept, meaning that, during field programming,24 links are to be

blown out.Typical PLAs have many more inputs, out puts, and AND gates than shown in

the example in Figure 1 (IC type 82S100, for example, has n = 16, m = 8, and p = 48)





When a set of switching functions is presented for implementation with a PLA,a design

goal would be reduction in p (the number of AND gates). The economy achieved is not

derived from a reduction in the production cost of gates. (The production cost of an IC is

practically the same for one with 40 gates as it is for one with 50 gates.) Rather, the

removal of one AND gate eliminates 2n + m links; the main source of savings is the

elimination of a substantial number of links due to the elimination of each AND gate. On

the other hand, reduction of the number of AND gates to a minimum does not mean that

each function should be minimized or that all implicants should be prime implicants. The

implicants should be chosen so that as many as possible of them are common to many of

the output functions.

4.2 PLA Folding

In practical implementations, AND and OR matrices in a PLA are usually sparse, since

the logic minimization is performed. This sparsity can be utilized with an optimization

technique called PLA folding to reduce the array occupied by a PLA, as well as the

capacitance of the lines, which produces faster circuits.

The technique consists of finding a permutation of the columns, and rows, or both, that

produces the maximal set of columns and rows which can be implemented in the same

column, respectively row, of the physical array. In this way, a PLA is split into a few

AND and OR matrices. The splitting is possible when the product terms for diff erent

outputs are disjoint. In the literature, the following cases have been considered.





Figure 3 PLA for f in Example 8.3 with D-AND-OR

Figure 4 Reduced PLA for f in Example 8.3 with D-AND-OR structure

1 Simple folding when a pair of inputs or outputs share the same column or row,

respectively. It is assumed that the input lines and the output lines are either on the upper

or lower sides of the columns,





Figure 5 Reduced PLA for f in Example 8.3 with OR-AND-OR structure

thus, there no intersections between folded lines. Most often, the Input and output lines

are folded in the AND and OR matrix, respectively, due to electrical and physical

constrains.

2 Multiple folding is a more general technique where the input and output lines are folded

as much as possible to minimize the number of columns, respectively rows, in AND and

OR matrices. This method reduces the area. However, routing of the input and output

lines is more complicated, and another metal or polysilicon layer may be required.

Therefore, multiple folding is effi

cient when the PLA is a component of a large systemwhere several metal or polysilicon layers are already required.

3 Bipartite folding is a special example of simple folding where column breaks between

two parts in the same column must occur at the same horizontal level in either the AND

or OR-matrix.

4 Constrained folding is a restricted folding where some constrains such as the order and

place of lines are given and accommodated with other foldings.

It has been shown that PLA folding problems are NP-complete and the number of

possible solutions approximates c! or r!, were c and r are the number of columns and

rows in the initial PLA, respectively. However, the procedure of folding can be

automatized, and many algorithms have been proposed, by using diff erent approaches.





Figure 6 Realizations of f in Example 8.4, by (a) PLA, (b) PLA with folded columns,

and (c) PLA with folded rows.

Example 1 Consider a four-variable two-output function f = (f0 , f1 ), where

f0 = x1 x2 + x1 x2 x4.

f1 = x2 x3 x4 + x3 x4.

Fig. 6 shows (a) a PLA for this function f , (b) the PLAs with columns folded, and

(c) the PLA with rows folded.





4.3 Fault model in PLA

Fault Models

• Stuck-At Faults• Bridging Faults

• Transistor Stuck-On/Open Faults

• Functional Faults

• Memory Faults

• PLA Faults

• Delay Faults

• State Transition Faults

Single Stuck-At Faults

Faulty Response

Fault-free ResponseTest Vector

Assumptions: • Only one line is faulty.• Faulty line permanently set to 0 or 1.

• Fault can be at an input or output of a gate.





Multiple Stuck-At Faults

• Several stuck-at faults occur at the same time

– Important in high density circuits

• For a circuit with k lines

– there are 2k single stuck-at faults

– there are 3k-1 multiple stuck-at faults

Why Single Stuck-At Fault Model?

• Complexity is greatly reduced.

Many different physical defects may be modeled by the same logical

single stuck-at fault.

• Single stuck-at fault is technology independent.

Can be applied to TTL, ECL, CMOS, etc.

• Single stuck-at fault is design style independent.

Gate Arrays, Standard Cell, Custom VLSI

• Even when single stuck-at fault does not accurately

model some physical defects, the tests derived for logic

faults are still valid for most defects.

• Single stuck-at tests cover a large percentage of

multiple stuck-at faults.





Bridging Faults

• Two or more normally distinct points (lines) are shorted together

– Logic effect depends on technology

– Wired-AND for TTL

– CMOS ?

CMOS Transistor Stuck-ON

• Transistor stuck-on may cause ambiguous logic level.

– depends on the relative impedances of the pull-up & pull-down networks

• When input is low, both P and N transistors are conducting causing increased quiescent

current, called IDDQ fault.





CMOS Transistor Stuck-OPEN

• Transistor stuck-open may cause output floating.

• Can turn the circuit into a sequential one

• Stuck-open faults require two-vector tests

PLA Faults

• Stuck Faults• Crosspoint Faults

- Extra/Missing Transistors

• Bridging Faults

• Break Faults

Missing Crosspoint Faults in PLA

• Missing crosspoint in AND-array

- Growth fault





• Missing crosspoint in OR-array

- Disappearance fault

Equivalent stuck fault representation

Extra Crosspoint Faults in PLA

• Extra crosspoint in AND-array

- Shrinkage or disappearance fault

• Extra crosspoint in OR-array

- Appearance fault

Equivalent stuck fault representation





4.3 Test generation and Testable PLA Design

Generation of tests for PLA-s and PAL-s

• Traditional methods for circuits equivalent to PAL/PLA-s;• Random testing

• Exhaustive testing

• Semirandom methods

• Deterministic Methods

Traditional methods for equivalent circuits

Cons:

1.Ineffective due to convergent branching

2. CP faults cannot be described as traditional s-a-0/1 faults





Random testing

Cons:

1. A very large number of tests as in AND array combinations where only one input

is 1 and the rest are 0s

can be used as tests.

2. A very large number of tests as the transport through the OR array requires that

one input equals 1 and

the rest are 0s.

Exhaustive testing and semirandom methods

Exhaustive testing

Cons: A large number of tests when real arrays are considered (for example, 50 inputs, 67

outputs, 190 terms)





Semirandom method

Deterministic Test Generation

Special algorithms oriented at the structure of the array and testing of CP-s.

Example: let us test whether x1x2 has been y1 = x1 x2 x3 + x1 x2 x3 + x1 x2

Added in the function y2 with CP x3. y2 = x1 x2 x3 + x1 x2

Let us define the operation: a # b = a b

Activating the impact of the fault: a = term that can be tested without faults

b = term than can be tested with faults

Example. x1 x2 # x1 x2 x3 = x1 x2(x1 x2 x3) = x1 x2 x3

Transport of the impact of the fault to the output: a =result of the previous operation,

b =functiwithout the tested term





Example. x1 x2 # x1 x2 x3 = x1 x2(x1 x2 x3) = x1 x2 x3

Test : x1 = 1

x2 = 1

x3 = 0

Testable PLA Design

What is the objective?

Must be taken into consideration:

Indicators of testability;

Impact on the original design;

Requirements for the testing environment;

Cost of design

Examples of testable PLA/PAL-s





Concurrent testing of PAL/PLA-s I

Totaly Self Cheking (TSC) Two-rail Checker

If x0 = y0 and x1 = y1 then f = g

PAL/PLA testable with universal tests

It is possible to test an array without knowing how it has been programmed. The

testing is not concurrent.





Decoder of the modified inputs

Universal tests

The length of the tests is 1+m+n, where m is the number of terms and n is that of inputs.


x1 … xi … xn c1 c2 s1 … s j … sm z1 z2

I1 - … - … - - - 0 … 0 … 0 0 0

For j=1, … , m

I j0 0 … 000 … 0 1 0 0 … 010 … 0 1 1

I j1 1 … 111 … 1 0 1 0 … 010 … 0 1 1

For I=1, … , n

Ji0 1 … 101 … 1 0 1 1 … 111 … 1 em -

Ji1 0 … 010 … 0 1 0 1 … 111 … 1 em -




More methods for improving the testability

1. Counting of CP-s. Presupposes the conductivity of bit lines and term lines.

Presupposes that the expected CP numbers are known (functioning array)

2. feedback from the signature analyzer to the inputs

(to the LFSR generating pseudorandom values). Thus ate these blocks united

into one.

3. several signature analyzers are used for testing both the AND and OR part.

For example, one is used for testing even bit lines and the other for odd. It results

in the better use of the chip area as the analyzer behind the bit lines requires more

space than the bit lines.

4. AND and OR arrays are divided into parts that enables to test them

simultaneously. Presupposes that additional requirements are set for thr

programming of PAL/PLA-s.


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