po2011 - a novel method for synthesizing an automatic. matching network and its control unit

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011 2225

A Novel Method for Synthesizing an AutomaticMatching Network and Its Control Unit

F. Chan Wai Po, Member, IEEE, E. de Foucauld, D. Morche, P. Vincent, and E. Kerhervé, Senior Member, IEEE

Abstract—We present a novel method simplifying matching net-work synthesis and design based on a tunable low-pass matchingnetwork topology. This method exploits the Smith chart in a novelway. Analytic expressions for calculating the optimal matching net-work for automatically adapting the load to the source impedanceare derived. This work is applied to a new antenna tuning unitconcept able to calibrate the system in a single iteration processreducing strongly both the speed and the overall consumption ofthe antenna calibration module. The obtained matching networknodal and load quality factors are analyzed and the matching net-work efficiency is evaluated to highlight the impact of the imper-fection in the design. The simulation and experimental results arepresented to validate the proposed method and to evaluate the ob-tained matching efficiency. We perform reflection coefficients lessthan �� dB, high efficiency matching networks with only 258

s to calculate the proper state of the tunable matching networkunder a processor delivering 40 MIPS of performance.

Index Terms—Antenna tuning units (ATU), impedance trans-formers, matching network, control unit.

I. INTRODUCTION

R ADIOCOMMUNICATION modules are widely inte-grated into handheld or portable devices to exchange data

like in mobile phones or in biomedical implants. The antennasused in such modules are typically narrow bandwidth miniatur-ized high-Q antennas [1] easily detuned by unpredictable nearfield environmental factors [2]–[4]. Mismatch of the antennaimpedance significantly degraded the power efficiency of theradio link.

Automatic matching networks are therefore developed tomatch any change in antenna impedance to power sourceimpedance in many RF applications. Most of adaptive antennaimpedance tuning units were developed operating iteratively[5]–[14] to match source and load impedances. This approachmatching time, approximately equal to several hundred mil-liseconds, is strongly affected by the iterative process and is notwell suited to low power applications and is also an obstacle to

Manuscript received July 02, 2010; revised November 19, 2010; acceptedJanuary 04, 2011. Date of publication March 10, 2011; date of current versionSeptember 14, 2011. This work was supported by ELA Medical Sorin Group.This paper was recommended by Associate Editor Y. Massoud.

F. Chan Wai Po was with CEA LETI MINATEC, 38054 Grenoble, France. Heis now with ISEP, 75006 Paris, France (e-mail: [email protected]).

E. de Foucauld, D. Morche and P. Vincent are with CEA LETI MI-NATEC, 38054 Grenoble, France (e-mail: [email protected],[email protected], [email protected]).

E. Kerhervé is with the IMS Laboratory, 33405 Talence, France (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCSI.2011.2112830

Fig. 1. Architecture of the automatic matching system.

the high speed reconfigurability consideration for future radiodevelopments [15].

A fast and accurate way to automatically match a systemin a single step was developed in [16], [17]. The architectureof the single step automatic matching network is illustrated inFig. 1 and its interest on an application was presented in [16].A generic detector made of capacitor is inserted between thepower module and the tunable matching network. The sensedsignals and are attenuated for linearity, down convertedto a lower intermediate frequency and analyzed by a processor.The benefit of the proposed architecture in Fig. 1 is that thedifferent modules used for the design of the antenna impedancetuning units, in particular the down conversion module andthe baseband processor, are already included into commonradio transceiver architecture. Only minor extra hardware istherefore required. In addition, the power consumption of radiocommunication modules is dominated by the power consump-tion of the power amplifier during the transmitting path andby the power consumption of the low noise amplifier duringthe receiving path. The extra power consumptions from thecomputing unit and the extra hardware are very small comparedto the power consumption of the power amplifier. Since theantenna impedance calibration is done during the transmittingmode as described in Fig. 1, to achieve low power antennaimpedance tuning units, we reduce strongly the time requiredfor the calibration. We achieve therefore so fast calibrationthat the extra power consumption from the extra modules iscompletely neglected. At the end of the calibration, the extramodules are switched to the idle mode.

As described by the flow chart in Fig. 2, the processor ex-ploits the magnitude and the phase of the sensed signals to firstcalculate the impedance and/or located in the left and theright port of the detector, respectively. Finally, the extraction of

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2226 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 58, NO. 9, SEPTEMBER 2011

Fig. 2. Flow chart of the antenna impedance tuning processor.

the antenna input impedance exploits the well known deembed-ding techniques to calculate from or . The obtainedantenna input impedance value is used to directly calculate theparameters of the matching network to reach the proper state ofthe system at a selected frequency. The success of the optimiza-tion or the calibration with arbitrary source and load impedancesis achieved with a single iteration. Since iteration is avoided,matching time is strongly reduced by more than several hun-dred times compared to common iterative optimization method[5]–[14] to achieve high speed reconfigurable system and lowpower consumption. This concept is obviously well adapted forthe evolution of wireless communications towards cognitive orsoftware defined radio where the parameters, in particularly thecarrier frequency at a time, are dynamically chosen and con-trolled by a flexible baseband processor [18].

However, the calculation of the parameters of the optimalconfiguration of the network that matches the extracted antennainput impedance to the optimal source impedance is difficult.Indeed, classical methods based on the study of the transferfunction of the matching network were first investigated butlead to heavy calculations that contribute to increase the pro-cessing time limiting the reduction of the calibration speed andthe overall power consumption. To optimize the process, it wasnecessary to develop a novel method for synthesizing an auto-matic matching network quickly and easily.

Here, we propose a new approach to achieve the process withsimple analytical expressions. By reducing the complexity ofthe algorithm, the number of instructions and the required timeto calculate the optimal configuration of the tunable matchingnetwork strongly decrease when the algorithm is implementedin a common embedded synchronous DSP, ASIC, or FPGAwith memory. This approach also lowers the required memorysize for the algorithm implementation into synchronous or asyn-chronous control units.

Since the goal of the automatic matching network design is tooptimize the power efficiency of the radio transceiver, we alsopropose in this paper to study the power efficiency of the de-signed lossy network. Indeed, a well matched network can con-tribute to generate high insertion loss in many RF applications.It is therefore very important to highlight the parameters of the

Fig. 3. Matching network with complex source and load impedances.

matching network that impact on its power efficiency in orderto discuss how to improve our design. Based on the study of thequality factors, the efficiency range of the automatic matchingnetwork is therefore presented to evaluate the performance ofthe obtained matching topology.

So, in this paper, we present the analysis of the automaticmatching network and its design method in Section II. Thequality factor and the efficiency of the automatic matchingnetwork are then evaluated in Section III. In Section IV, theanalytical results are discussed and compared to the simu-lations. The experimental results highlighting the achievedperformance of the algorithm and its application to adaptiveantenna impedance tuning unit demonstrator are presented anddiscussed in Section V.

II. AUTOMATIC MATCHING NETWORK

We present in this section a new design method for auto-matic matching network. This new method is meant to optimizethe overall performance of the control unit of the single stepautomatic matching network presented previously in [16]. Ourstudy uses a low-pass tunable matching network to approachthe design. The design includes a network transformation, thechoice of the inductance value and the matching network de-sign method.

A. Topology

In ATU applications, a tunable matching network is neededfor its ability to adapt a great number of load impedances or anychange of load impedance to the source impedance.

The generic low-pass tunable matching network shown inFig. 3 is chosen as the starting point of our study. As in manyimpedance transformers or ATU applications operating from400 MHz to 2.4 GHz frequency band, the inductor is not tun-able. The tuning ability of the matching network is provided byvariable capacitors made of diode varactors or banks of switchedcapacitors.

B. Matching Network Transformation

In RF applications, source and load impedances to bematched are usually complex. The first step in the proposedmethod is to transform the complex source and load imped-ances into real source and load impedances. The rationalebehind such transformation from complex to real impedancesresults in the fact that the best and the worst cases that affectthe system can not be identified easily while exploiting therange variation of the complex load impedances. This analysisbecomes evident with transformed real load impedance rangewhere the minimum and the maximum real load impedancesare identified. Thus, such transformation simplifies stronglythe design of the optimum values of the matching network, the

CHAN WAI PO et al.: A NOVEL METHOD FOR SYNTHESIZING AN AUTOMATIC MATCHING NETWORK AND ITS CONTROL UNIT 2227

Fig. 4. Transformed matching network with real source and load impedances.

analysis of its quality factor and the study of its power transferefficiency. The transformed matching network topology isillustrated in Fig. 4.

The transformation consists of three steps: i) extraction of se-ries-leg quality factors; ii) extraction of the transformed sourceand load; iii) analysis of the equivalent shunt variable capaci-tors.

We can define the series-leg quality factors and ofsource and load respectively by

(1)

(2)

The transformed source is a resistance in parallel withcapacitor

(3)

(4)

Similarly, the transformed load is a resistance in parallelwith a capacitor

(5)

(6)

The equivalent shunt capacitances and are expressedas follows:

(7)

(8)

C. Choice of the Inductance Value

The dotted area located in the Smith charts in Fig. 5(a) and (b)illustrates the dynamic range of the impedance tuner in Fig. 3simulated at 2.4 GHz frequency with 50 source impedanceusing respectively an inductance value of 2.5 nH and 1.7 nH.The capacitors values vary from 0.2 pF to 10 pF with a 0.2 pFresolution.

Let us consider an example of normalized complex conjugateload impedance variation range represented in the Smith chartsin Fig. 5(a) by the semicircular shape. Any normalized loadimpedance whose complex conjugate is located in the dotted

Fig. 5. Dynamic range of the impedance tuner at 2.4 GHz depending on theinductance. (a) � � �� nH. (b) � � �� nH.

area can be matched to the source impedance; whereas it is im-possible to match to the source impedance any normalized com-plex conjugate load impedance located in the forbidden region.To avoid this type of scenario, it is necessary to correctly set thevalue of the inductance in order to obtain the configuration il-lustrated in Fig. 5(b) where the complete normalized complexconjugate load impedance variation range is included into theimpedance tuner dynamic range.

For our study, we first apply a matching network transforma-tion as described previously to achieve the matching networktopology illustrated in Fig. 4. It becomes therefore evident toidentify the maximum and the minimum load impedance thataffect our system. The range of the transformed and normalizedreal load impedance which varies between and

is illustrated in Fig. 5 by the bold lines.In general, at a given angular frequency and neglecting

the self-resonant frequency of the elements, the forbidden circlewhere load impedance can not be matched depends on the in-ductance value and its diameter is given by

(9)

The inductance value should be set carefully in order to matchany value that could affect the load impedance. Indeed, the for-bidden circle diameter should be smaller than

(10)

Thus, for our single-end matching network topology, in orderto have the ability to match the load variation, the value of thechosen inductance should be smaller than the inductance max-imum value which expression is derived from (9) and (10)as

(11)

where , the transformed source real impedance, is constant., the transformed load real impedance, can reach a value

between min and max .


Fig. 6. Transformation diagram of the impedances of the matching network.

D. Matching Network Design Method

We present a novel method strongly reducing the complexityof the matching network design, providing a quick and easycalculation. It exploits and approaches the Smith chart shownin Fig. 6 in a novel way.

We simplify the analysis by using the transformed matchingnetwork shown in Fig. 4, where source and load impedancevalues are real. The impedances are normalized assuming thecharacteristic impedance to be defined in (3). The goal is tomatch the normalized impedance to the normalized source

equal to 1 and localized at the center of the Smith chart.The steps for matching the normalized load to the source

are as follows:— Since is in shunt with the load , the normalized

real load impedance moves in the clockwise directionon the admittance Smith chart until .

— The next element is a serial inductance . We rotate inthe clockwise direction on the impedance Smith chart until

.— Finally, the shunted capacitor is designed to reach the

final matching goal located at the center of the Smithchart.

The steps and the analytical expressions to calculate the op-timum element values of the tunable matching network are pre-sented below:

Step 1: The node is on the curve 1. In general, we canconsider the capacitor quality factor is high . Therefore,the parasitic resistance of the capacitor is neglected, theanalytical expressions of this curve in the admittance domain

and in the impedance domain are given by

(12)

(13)

Step 2: If is the normalized expression of theinductance and is its normalized parasitic resistance, the

expressions of the curve 2 in the impedance domain andin the admittance domain are

(14)

(15)

Step 3: The node belongs to the curve 2. Moreover, thereal part of the admittance of is equal to the real part of theadmittance of the normalized load . As a result, we obtainthe following equation:

(16)

When the inductance quality factor is high canbe neglected and (16) is reduced to the following second-orderequation:

(17)

Step 4: In general, the quadratic equation (17) has two roots:and

(18)

(19)

The solutions depend on the normalized real load impedance, on the normalized inductance value and on the angular

frequency . Since (19) can lead to negative optimum values ofthe variable capacitors and shown in Fig. 3, only (18) isselected as the unique solution.

Step 5: The admittance of the node and are obtainedfrom (12), (15), and (18) as

(20)

(21)

Step 6: The values of the capacitance and are givenin the admittance domain by the move from until andfrom until , respectively

(22)

(23)

Step 7: Using (7), (8), (22), and (23), the capacitances and, giving the optimal configuration of the matching network,

are calculated

(24)

(25)

Finally, after transforming the matching network andchoosing the inductance value matching the desired load rangeto the source, the matching network design algorithm can be


Fig. 7. Multistage variable matching network.

implemented using only the analytical formulas given by (18),(20), (21), (24), and (25). These formulas can also be used tocalculate the necessary variation range of the capacitors and

suitable to adapt a variation range of load impedances tothe source.

E. Multistage Matching Network Design

A multistage matching network is sometimes preferred to asingle stage topology for efficiency consideration, especiallywhen the impedance transformation ratio betweenthe load and the source impedances is strong. It is demonstratedin [19] that the optimum number of stage is equal or greaterthan two for a resistance transformation ratio greater than nine.Having nontunable stages before the tunable one in the mul-tistage scheme presents the advantage to make the impedancetransformation process in several steps reducing the impedancetransformation ratio of each stage contributing therefore to im-prove the matching network load quality factor and its overallefficiency that will be studied in Section III.

To design a tunable multistage matching network scheme,we propose to insert first nontunable stages before the tunablematching network as illustrated in Fig. 7. The nontunable stagestransform the optimal source impedance to an intermediatereal source impedance as shown in Fig. 7, reducingtherefore the resistance transformation ratio of each stage. Thetunable matching network topology, which is a low passstructure as described previously in Fig. 3, is next designed tomatch the variable load impedance range to the intermediatereal source impedance exploiting the matching networkdesign methodology developed previously. Such methodologyis used to convert the complex load to real load impedance (5),to set the inductance value of the tunable matching network(11) and to find its proper state configuration (24), (25).

For stages network, the values of the intermediate imped-ances are obtained by choosing the transformation quality fac-tors of all stages as follows:

(26)

where and are the transformed real source and loadimpedances, respectively.

Thus, we get the intermediate real impedances of each stageby exploiting the following equation:

(27)

Similarly, as , we can write

(28)

And the intermediate impedances are obtained from (27) and(28) are given as follows:

(29)

(30)

III. QUALITY FACTOR AND EFFICIENCY ANALYSIS

We analyze in this section the quality factors and the powerefficiency of the designed matching network. The goals of thiswork are to evaluate the lossy network performance and to high-light the parameters that contribute to degrade its power effi-ciency in order to discuss how to improve our design.

A. Nodal and Load Quality Factors

Let us start with the matching node . At each node , theequivalent impedance can be expressed in terms of a normalizedseries impedance or admittance

(31)

(32)


Fig. 8. Low pass � matching network with parasitic resistances divided into two sections: (a) a low pass L section and (b) a high pass L section. (c) demonstratesthe Smith chart with impedance transformation.

The nodal quality factor can be found as the ratio ofthe absolute value of the normalized reactance to the cor-responding normalized resistance [20]

(33)

Similarly, can be calculated as the ratio of the absolutevalue of the normalized susceptance to the normalized con-ductance

(34)

By definition, the matching network load quality factoris given by the maximum nodal quality factor. For efficiencyconsideration, it is better to keep the load quality factor ofa matching network as small as possible. Considering thematching topology with two nodes and as illustrated inFig. 6, we can write the matching network load quality factoras follows:

(35)

where and are the nodal quality factors of and ,respectively.

B. Matching Network Efficiency

In order to evaluate the losses in the matching network, theinitial network is divided into a low pass L section and a highpass L section networks as illustrated in Fig. 8. The high passL matching network transforms the impedance intowith a nodal quality factor . The low pass L section trans-forms to with a nodal quality factor . The parasiticresistances are included in Fig. 8(a) and (b). The normalizedsource and load impedances and , matchingnode and impedance transformation are represented inthe Smith chart in Fig. 8(c).

Consider the low pass L section shown in Fig. 8(a). The ex-pression of the powers and , entering the matching net-work from the left and from the right, respectively, are given by

(36)

(37)

If the right port is connected to the load, the impedance ofthe node shown in Fig. 8(a) is obtained from in additionwith the impedance of the series inductance

(38)

The nodal quality factor of the node is easily calcu-lated from (33) and (38)

(39)

If the left port is connected to the source, the admittance of thenode illustrated in Fig. 8(a) can be expressed as the admit-tance minus the admittance of the shunted capacitance

(40)

From (34) and (40), the nodal quality factor associatedto the node is also given by

(41)


The parasitic resistances of the lossy components, like induc-tors or capacitors, used to design the matching network con-tribute to generate the insertion loss. The losses that affect thelow pass L section represented in Fig. 8(a) are the lossin the inductor and the loss in the capacitor

(42)

(43)

where is calcu-lated from (39),

is obtained from (41),and .

If the left port is connected to the source and the right port isconnected to the load, we can write

(44)

From (42), (43), and (44), we obtain therefore the expressionof the low pass L section matching network power efficiencyas the ratio between the output power and the input power

as follows:

(45)

Similarly, we calculate the expression of the power efficiencyexpression of the high pass L matching network illustrated inFig. 8(b). If the left port is connected to the source and the rightport is connected to the load, the ratio between the output power

and the input power is given by

(46)

Finally, from Fig. 8 and (45) and (46), the low passmatching network efficiency expression, with the left

port connected to the source and the right port connectedto the load, is given as function of the network nodalquality factors and of the quality factors

of the network lossy components.

With no approximation and no simplification, the expression ofthe low pass matching network efficiency is

(47)

The initial matching network is divided into two L sec-tions where the inductors have exactly the same ratio betweentheir reactance and their parasitic resistance, consequently theyhave the same quality factor . Also, thenodal quality factors are most of the time small compared to thequality factors of the matching components to avoid high inser-tion loss. In this condition and for simplicity, we can transform(47) into

(48)

For the case of high efficiency, when, we can

simplify (48) as

(49)

It is well known that the quality factor of capacitors is strongcompared to the quality factor of inductors. Forand , the capacitor loss can be neglected and theonly loss to be considered is the inductor loss. In this case, (49)can be approximated as

(50)

When the entire inductor quality factors are identical andgiven by , the multistage matching network in Fig. 7 achievesan overall efficiency approximated by

(51)

where to are the quality factors of L section nontun-able matching networks and are the nodal qualityfactors of the tunable matching network.

IV. CALCULATION AND SIMULATION RESULTS

The previous sections presented the design method of the au-tomatic matching network and its efficiency analysis. In this


TABLE ICALCULATED PARAMETERS OF THE OPTIMAL MATCHING NETWORK

Fig. 9. Flow chart of the matching network design algorithm.

section, we apply the analysis in order to match the load tothe source impedance. The calculations and the simulations aredone using the matching network topology illustrated in Fig. 3.The results are compared and the efficiency of the designedmatching network is finally verified by calculations and simula-tions.

A. Automatic Matching Network Design Results

Below, we elaborate three scenarios where complex loadimpedance values of and

need to be matched to the source impedancevalues of at 400 MHz, at 900MHz and 100 at 2.4 GHz, respectively, using the automaticmatching network in Fig. 3. The matching network designalgorithm whose flow chart is illustrated in Fig. 9 is executedby simulation and calculation to set the optimum values of thenetwork.

The transformed real source impedance and real loadimpedance values are calculated using (3) and (5) respec-tively. The maximum inductance Lmax is calculated from (11).

equal to 32.8 nH, 14.4 nH, and 6.63 nH are calculatedfor a chosen minimum value of the transformed load impedance

of 100 at 400 MHz, 50 at 900 MHz, and 100 at2.4 GHz, respectively. The chosen inductance values should besmaller than Lmax as demonstrated in Section II. Thus, we se-lect L equal to 30 nH, 10 nH, and 5 nH, respectively for the first,the second and the third scenario. The values of are given by(18), by (20), and by (21). The optimal values of thecapacitors and , allowing maximum power transfer fromthe source to the load, are finally extracted using (24) and (25),respectively. The numerical results are summarized in Table I.

Fig. 10. Simulated reflection coefficient.

The designed matching networks are simulated with ad-vanced design system (ADS) tool in S-domain and the obtainedreflection coefficients are shown in Fig. 10. The simulationsshow excellent results. In all cases, reflection coefficient valuesare less than dB.

B. Evaluation of the Matching Network Efficiency

The matching network efficiency developed in Section III ismainly used to estimate the losses of our design, but can be alsovery useful to decide on the topology of the automatic matchingnetwork, in particular its number of stages, to achieve a reason-able load quality factor Q (35) for efficiency. Typically, the ef-ficiency of a matching network is function of its nodal qualityfactors (33), (34) and the quality factor of the components usedfor its design. For high efficiency low-pass networks, wherethe quality factor of the components are high compared to thenodal quality factors of the network, the efficiency of the au-tomatic matching network is estimated from (49). In addition,assuming the quality factors of the selected matching networkcapacitances are high compared to the inductor quality factors

; the formula (50) is preferred.The design results obtained previously and summarized in

Table I are used below. The normalized nodal admittancesand are used to evaluate the nodal quality factors and

exploiting (34). The simulations and the calculations aredone using inductances quality factors ofand . As illustrated in Table II, the nodal qualityfactors and are small compared to the quality factor

of the inductors. The matching network efficiencies can betherefore evaluated from (50). However, it is important to men-tion that the practicability of (50) is limited for high efficiencymatching network. In the case where the nodal quality factors


TABLE IICOMPARISON OF CALCULATED AND SIMULATED MATCHING NETWORK EFFICIENCY

Fig. 11. Efficiency range of the automatic matching network versus �� and �� .

are not small enough compared to the quality factors of the com-ponents, it is better to exploit the formula (47). Finally, as ex-pected, the computed efficiency results for

and are in good agreement with the simulationsas summarized in Table II. The maximum efficiency is 98% andthe minimum is 86%.

Next, for a given complex load impedance range to matchto a source impedance using a tunable matching network, wecan obviously predict the efficiency range of the well-matchednetwork. Exploiting the design methodology developed inSection II, we evaluate first the node impedances or admit-tances (20), (21) range of the network followed by the extractionof the nodal quality factors range from (33) or (34). For highefficiency network, the efficiency range is obtained applyingthe nodal quality factors range in (50) for a given inductancequality factor. We use this method to match a complex loadimpedance range, whose real part can vary from 60 to260 and imaginary part from 100 to 100 , to 100source impedance at 2.4 GHz using the low-pass automaticmatching network in Fig. 3. The efficiency results calculatedfor an inductance quality factor of are represented inFig. 11. We show that the automatic matching network reachesefficiency values ranging from 90% up to 98%.

The efficiency of a high impedance transformation ratioscenario has also been calculated and simulated using

respectively a single-stage matching network shown in Fig. 3and a two stage network illustrated in Fig. 12 to match the

Fig. 12. Two stage matching network with real source and load impedances.

load impedances to the source impedance as summarized inTable III. In a single-stage topology, applying the design methoddeveloped in Section II gives a chosen inductance nHand the nodal quality factors and .For , we achieve a simulated efficiency of 82.5%and a calculated efficiency from (50) of 80%. For ,we obtained in both case a efficiency approximately equal to94%. The two stage matching network illustrated in Fig. 12aims to reduce the load quality factor (35) of the network inorder to improve its power efficiency. As illustrated in Fig. 12,the load impedance is first matched to a desired intermediatedimpedance , calculated from (30), using a tunable matchingnetwork. The obtained impedance is next matched to the sourceimpedance with a nontunable matching network.Two nodal quality factors andare derived from the tunable matching network. The nodalquality factor of the non tunable low pass L section matchingnetwork is given by . For , the simulatedmatching efficiency is 90.5% and the calculated efficiency from(51) is 88.5%. For the efficiency is approximatelyequal to 97%. Compared to the single stage network, we reducethe load quality factor (35) from 11.523 to 3.594, and weimprove the efficiency of our design by more than 8% and 2%for and , respectively. In general, in singleand two stage networks, the calculation and simulation fit well.The difference is due to the approximation made in (50) and(51) to calculate the efficiency.

V. EXPERIMENTAL RESULTS

The simplified block diagram of the automatic an-tenna-impedance tuning unit presented in our previous work[16] is illustrated in Fig. 13. The detector module allows thesystem to extract phase/magnitude information. The data aredown converted to a low intermediate frequency and analyzedby the control unit. As shown in the flow chart of the controlunit in Fig. 2, the processor analyses the information to extract


TABLE IIICOMPARISON OF THE ESTIMATED AND SIMULATED EFFICIENCY OF A SINGLE STAGE AND MULTISTAGE MATCHING NETWORK

Fig. 13. Automatic antenna impedance tuning unit (AATU) simplified blockdiagram.

Fig. 14. AATU prototype including the matching control unit.

Fig. 15. Simplified structure of the varactor.

the load complex impedance. The matching design algorithmshown in Fig. 9 is executed to match the load impedance to thesource impedance applying the developed matching networkdesign method in Section II.

A first prototype of the automatic antenna tuning unit that op-erates only at the MICS 402–405 MHz frequency band is shownin Fig. 14. The control unit has been implemented as an AnalogDevices microcontroller ADUC7026. The microcontroller coreis an ARM7TDMI, 16/32 bits RISC processor, offering up to 40MIPS peak performance. The tunable matching network con-sists of a low pass matching network in Fig. 3 with an induc-tance and two variable capacitors made of varactors [21] whichsimplified structure as shown in Fig. 15. 12-bit DACs control theDC voltage of the varactors with a resolution of 750 V LSB.

Fig. 16 shows two experimental reflection coefficient mea-surements. The first one shown in Fig. 16(a) was done before thecalibration process in the presence of a detuned tunable low-pass

Fig. 16. Measured reflection coefficient: (a) before the calibration routine and(b) after single iteration calibration process.

Fig. 17. Postcalibration measured reflection coefficient obtained for differentload scenarios.

matching network. With knowledge of the load impedanceand source optimal impedance, the developed matching networkdesign algorithm in Fig. 9 is executed to set the proper state ofthe network. As illustrated in Fig. 16(b), we achieve a postcal-ibration reflection coefficient up to dB at the desired fre-quency of 403 MHz. Experimental postcalibration reflection co-efficient has been also measured for different load impedancesas illustrated in Fig. 17. We obtained a S11 up to dB at403 MHz. Moreover, the synchronous processor spends no morethan 258 s to compute the matching network design algorithmunder a processor speed of 40 MIPS as illustrated in Fig. 18 andrequires only 2512 bytes of memory size for its implementation.The algorithm was implemented under Keil embedded develop-ment tools. It was coded in C language; compiled and down-loaded into Flash EEPROM memory using JTAG interface.

VI. DISCUSSION

The study and results presented so far have left a few ques-tions unanswered, while also opening up new avenues of re-search. We address these points in this section.


Fig. 18. Time to calculate the optimal network configuration.

We have shown a method that strongly reduces the automaticmatching network design. It is extremely efficient to matchany load impedance to the source using the matching topologyin Fig. 3. The impedance transformations are performed, thechoice of the inductance is discussed, and matching networkdesign is achieved with simple analytical expressions. Theexpressions are exploited to implement the matching networkdesign algorithm of a novel ATU control unit [16] whose flowchart is illustrated in Fig. 9. The resulting algorithm complexityis low and hence reduces the tuning time. Matching the systemin a single step but with an algorithm of high complexityhas little interest. Therefore, this approach simplifying thematching process can be considered as a key point of the singlestep adaptive load impedance tuning units. This contributesto reduce the matching time, the power consumption and therequired memory for its implementation.

The load impedance can be well matched to the source, butthe matching network can be also strongly affected by losses.Thus, we developed the analytical expressions of the powertransfer efficiency to identify the impacts of the matching net-work parameters, as nodal quality factors and the quality fac-tors of the inductors and capacitors. Even if design techniquessuch as multistage network design are helpful for increasingmatching network efficiency, it is clear that investigation shouldbe lead in the development of inductors with high quality factor.Indeed, to improve the fully integration of ATU, the qualityfactor of integrated inductors should increase. Moreover, thevariability of inductors is limited today. The use of variable in-ductors should be investigated in the future to demonstrate itsability to improve automatic matching network nodal qualityfactors and increase the overall matching efficiency. The in-ductor variability should be not necessary continuous but canbe also discrete.

VII. CONCLUSION

This paper presents a method for automatic matching net-work design and its synthesis. The method is developed to re-duce the matching design complexity. The analytic expressionsto achieve the optimal configuration of the automatic matchingnetwork are derived and its efficiency is evaluated. Both simula-tion and measured results are presented to validate the method.The experimental results show that a reflection coefficient up to

dB is reached with the presented method applied to an ATU

application. The implemented matching network design algo-rithm takes 258 s to calculate the optimal network and requires2512 bytes Flash EEPROM memory space in the ADUC7026microcontroller from Analog Devices.

ACKNOWLEDGMENT

The authors would like to thank ELA Medical (Sorin Group)for supporting this work. The authors would also like to thankE. Isa for contributing to improve the quality level of this paper.

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Francis Chan Wai Po (M’10) received the Engi-neering diploma from Ecole Nationale Supérieured’Electronique, Informatique et Radiocommuni-cations de Bordeaux (ENSEIRB), France, and thePh.D. degree in microelectronics from the Universityof Bordeaux 1, France, in 2004 and 2010, respec-tively.

His Ph.D. work was carried out at CEA LETI incollaboration with ELA Medical and the IMS Lab-oratory and was mainly focused on the design of alow power RF front-end transceiver with automatic

power efficiency optimization for biomedical implants. He has since joined theMINARC research team at Institut Supérieur d’Electronique de Paris (ISEP),France, where he is currently an Assistant Professor in Microelectronics. Hiscurrent field of research is the design of analog and radiofrequency integratedcircuits for biomedical applications.

Dr. Chan Wai Po is a member of the IEEE Cicuits and Systems Society.

Emeric de Foucauld received the Ph.D. de-gree from IRCOM-University of Limoges,France, in 2001. This study was focused onradio-frequency voltage-controlled oscilla-tors for TETRA-TETRAPOL application ofEADS-Telecom.

He joined the Wireless Division of STMicroelec-tronics in 2001, and worked on the Frequency Syn-thesizer IP team as RFIC design engineer. In 2003, hejoined the RF design team of CEA-LETI, Grenoble,France, and he is currently involved in analog inte-

grated circuit design for wireless systems.

Dominique Morche received the Engineer diplomafrom the Ecole Nationale Supérieure d’Electricité etde Radioelectricité de Bordeaux (ENSERB), France,in 1990 and the Ph.D. degree in electronics from theInstitut National Polytechnique de Grenoble (INPG),France, in 1994. His Ph.D. mainly focuses on sigma-delta ADC.

From 1994 to 2001 he was employed by FranceTelecom as a research engineer. He has been in-volved in architecture and design of analog circuitsfor telecom application. He is currently working at

CEA-LETI, Grenoble. His current field of research is in the specification anddesign of RF architecture for UWB and 4G systems.

Pierre Vincent received the M.Sc. degree in micro-electronic engineering from the University of Mont-pellier (ISIM), France.

In 1990 he worked as an Analog RF developmentengineer and technical group leader in Thomson CSFsemiconductor for space, military, and avionic ap-plications. In 2000 he joined Infineon TechnologiesEchirolles France at its start-up. He was responsiblefor setting up the Analog IC development for 40Gbps high-speed optical network applications. Hejoined the CEA-LETI, Grenoble, France, in 2003 as

a design manager and responsible for RF architecture and the RF IC design lab.He is involved in millimeter wave and RF MEMS cointegration design.

Eric Kerhervé (M’96–SM’09) received the Ph.D.degree in electrical engineering from University ofBordeaux, France, in 1994.

He joined IPB ENSEIRB-MATMECA and theIMS Laboratory in 1996, where he is currently aProfessor in Microelectronics and Microwave Appli-cations. His main areas of research are the design ofRF, microwave and millimeter-wave circuits (poweramplifiers and filters) in silicon, and BAW technolo-gies. He is or was involved in European projects,such as MEDEA+ UPPERMOST, FP6 MOBILIS,

MEDEA+QSTREAM, CATRENE PANAMA, and ENIAC MIRANDELAto develop silicon power amplifiers and BAW duplexer. He has authored orcoauthored more than 190 technical papers in this field, and was awarded 17patents.

Prof. Kerhervé has organized six workshops on advanced silicon technologiesfor radiofrequency and millimeter-wave applications. He is involved in the tech-nical program committees of various international conferences (ICECS, IMOC,NEWCAS, EuMIC, SBCCI) and he was the chair of the international IEEEICECS2006 conference. Since 2010, he has been an Associate Editor of IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS—PART II: EXPRESS BRIEFS.

po2011 - a novel method for synthesizing an automatic. matching network and its control unit

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