Pole-Zero Analysis of Low-Dropout (LDO)Regulators: A Tutorial Overview

Annajirao Garimella, Punith R. Surkanti and Paul M. FurthVLSI Laboratory, Klipsch School of Electrical and Computer Engineering

New Mexico State University, Las Cruces, NM 88003, USAEmail: garimella@ieee.org, punith@nmsu.edu and pfurth@nmsu.edu

Abstract—Analyzing poles and zeros of a circuit is oftenessential for (a) choose the appropriate topology for givenspecifications, (b) understanding the frequency response of thecircuit and (c) stabilizing the circuit by choosing appropriatefrequency compensation techniques. Analyzing poles and zerosof a low-dropout (LDO) voltage regulator is often intriguing as(a) the voltage/current control loop need to be broken for small-signal analysis and (b) the location of poles move with outputload current. The objective of this tutorial is to provide a step-by-step procedure for analyzing poles and zeros in LDO regulators.To this end, two recent state-of-the-art LDO regulators from theliterature are analyzed, explaining several intricacies involved.During the process, several frequency compensation techniquesare elucidated.

Index Terms—Frequency compensation, pole-zero analysis,low-dropout (LDO) regulators, cascode compensation, currentbuffers, LHP zero, power-supply rejection (PSR).

I. INTRODUCTION

Stability at various loading conditions with improved lineand load transient response is often the objective of low-dropout (LDO) voltage regulator design [1]–[9]. A prioriknowledge of poles and zeros assists the designer in choosingthe correct topology before implementing the transistor leveldesign. Finding the transfer function, and thus poles and zeros,of the voltage and/or current loops of the LDO regulator oftenhelps in developing intuition of the circuit and parametersaffecting the loop gain, pole-zero locations, gain-bandwidthproduct, phase margin and other stability conditions [10],[11]. In this tutorial, we explain a step-by-step procedure forperforming small-signal analysis and deriving the equations ofpoles and zeros in LDO regulators. Two recent state-of-the-art LDO regulators [9], [12] are analyzed. The outline of thepaper is as follows: Section II outlines the steps for findingpoles and zeros. Section III illustrates pole-zero analysis ina three-stage LDO with reverse nested Miller compensationusing current buffers [9]. Sections IV and V laid a backgroundfor analyzing poles and zeros of a high PSR current-modedual loop LDO [12] in Section VI. Conclusions are drawn inSection VII.

II. STEPS FOR FINDING POLES AND ZEROS

The steps for obtaining the DC gain, poles and zeros of aLDO regulator are

1) For the given topology, draw the small-signal model2) Break the corresponding voltage or current loop

gm1

SV

R C

C

1 1

–gm2

R C2 gs R C3 OUT

–gmp

gmCG

V

Cgd

RC2

1V 2V

YV

gmCG

1

C2

C–

mBU

C1g XV

gmBU

1Ai =+1

Ai = –1

OUT

Fig. 1. Block-level architecture of LDO with reverse nested Miller Com-pensation using current buffers.

3) Apply Kirchhoff’s Current Law (KCL) at each node4) Solve the KCL equations using symbolic manipulation

software to obtain the transfer function5) Set s (= jω) = 0 to find the DC gain of the amplifier6) Factor and solve the numerator to obtain zeros7) Applying the assumption of widely-separated poles,

solve the denominator to obtain the poles, OR applyingthe assumption of widely-separated poles with a com-plex pole pair, solve the denominator to obtain the poles

III. LDO WITH REVERSE NESTED MILLERCOMPENSATION USING CURRENT BUFFERS

In this section, the three-stage LDO regulator of [9] ischosen as an example and detailed pole-zero analysis isperformed. The block-level architecture of the LDO regulatoris shown in Fig. 1 and the adapted transistor-level schematic isshown in Fig. 2. This regulator uses with reverse nested Millercompensation using current buffers (RNMCCB). RNMCCBallows cancellation of a non-dominant pole with left-half plane(LHP) zero, forming a stable LDO with adequate phase margin(>75o) with improved transient line and load response.

Referring to Fig. 2, the first stage is an NMOS folded-cascode differential amplifier (gm1) formed by transistors M1-M9 and the second stage is an NMOS common-source am-plifier (gm2) formed by transistor M10 with diode-connectedtransistor load M11. The third stage is the power stage (gmP ),formed by pass transistor Mpass and sampling resistors Rf1

and Rf2. The output resistance of the first stage is R1 and

VREF

ILOAD

Rf1

Rf2

GND

V

CC1

M11

M6

M4

M5

M3

M2

M10

M1

gm1

gm2

V

Vb1

Vb4

Vb3

M9M8

Cgd,PASS

MPASS

gmP

V2

V1

M7

COUT

VX

OUT

LINE

VY

RC2 CC2

XXBreak Loop Here

gmBU

gmCG

Cgs,PASS

FBV

Fig. 2. Schematic of the three-stage LDO regulator with reverse nested Miller compensation using current buffers, adpated from [9]. Generation of two LHPzeros using 1) cascode compensation 2) current mirror (as inverting current buffer) compensation is highlighted.

g

+

-

vS R1 C1

mBUg v

X

CC2RC2 v2v1

vY mCG

g1

gmCG

vY

m1vS

R2

Cgs,PASSm2v1g

CC1 vOUT

mBUg1

vX

ROUT COUTmPv2g

Cgd,PASSiC2

igd

iC1RF1

RF2

+

-

vFB

Fig. 3. Small-signal model of the LDO regulator of Fig. 2

the lumped parasitic capacitance is C1. For the pass transis-tor MPASS , significant parasitic capacitances Cgd,PASS andCgs,PASS are considered for pole-zero analysis. The outputresistance of the second stage at node V2 is R2 and the lumpedparasitic capacitance can be approximated as Cgs,PASS . Theoutput resistance of the power stage at node VOUT is ROUT

and COUT is the output capacitor, either integrated or externalcapacitor.A. Compensation Network

Reverse nested Miller compensation (RNMC) uses oneinner loop and one outer loop [13]. Compensation capacitorCC1 is connected from node VOUT to low-impedance inputnode VX of the current mirror formed by transistors M8-M9

with transconductance gmBU . The current mirror acts as aninverting current buffer [9], [14]–[17], denoted as gmBU inFig. 1. CC1 and gmBU form the outer loop of the RNMC.

The inner loop is between nodes V2 and V1 formed by com-pensation capacitor CC2, series resistor RC2 and common-gatecascode transistor M7, whose transconductance is gmCG. Thecompensation capacitor CC2 and resistor RC2 are connectedbetween V2 and VY , where VY is the source node of thecommon-gate transistor M7, whose transconductance is gmCG

in Fig. 1. Transistor M7 acts as a positive current buffer [9],[14], [18]–[22] and the compensation network is popularlyknown as cascode compensation or Ahuja compensation.

B. Small-signal ModelingThe feedback is broken between node vFB and gate input

of transistor M2 as shown in Fig. 2. Let vS be the differential

TABLE ISMALL-SIGNAL PARAMETERS OF LDO USING RNMCCB(FIG. 3)

gm1 gm of M1, M2

R1 ro9||gmCGro7 (ro5||ro2)

C1∗ Cgd7 + Cgd9 + Cgs10

gmBU gm of M8

gmCG gm of M7

gm2, ro10 gm, ro of M10

R21

gm11||ro10

C2∗ Cgd10 + Cgs11 + Cgs,PASS ≈ Cgs,PASS

gmP , roP gm, ro of MPASS

ROUT roP ||(Rf1 +Rf2

)||RL

C3∗ Cgd,PASS + COUT ≈ COUT

* Omitting bulk capacitances for simplicity

input voltage between the reference voltage vREF and thefeedback voltage vFB . The open-loop small-signal diagramof Fig. 2 from vS to vFB is shown in Fig. 3. The first stageis non-inverting so as to ensure that the overall gain fromvREF to vOUT is non-inverting. Equations for the small-signalparameters of the regulator of Fig. 3 are given in Table I.

The first-stage differential amplifier is represented withvoltage-controlled current source (VCCS) gM1vS . The outputof the first-stage is v1. The second-stage is represented withVCCS gM2v1. The output of the third-stage is vOUT . Thecompensation capacitor CC2 and resistor RC2 are connectedbetween v2 and vY , where vY is the source node of thecommon-gate transistor M7, whose impedance to ground is

1/gmCG. The positive current buffer between vY and v1 isrepresented with VCCS gmCGvY . The compensation capacitorCC1 is connected between vOUT and vX , where vX is the lowimpedance node with 1/gmBU as the impedance to ground.The inverting current buffer between vX and v1 is representedwith VCCS gmBUvX . Cgd,PASS is connected between v2 andvOUT , which forms a feedforward path.

C. Applying Kirchhoff’s current law (KCL)

We apply KCL at every node in Fig. 3. The set of KCLequations are

vS = vREF − vFB

v1 = (gm1vS − gmBUvX + gmCGvY )Z1

v2 = (−gm2v1 − iC2 + igd)Z2

vOUT = (−gmP v2 − iC1 − igd)Zout

vFB = βvOUT

β = RF2RF1+RF2

vX = iC1gmBU

vY = iC2gmCG

(1)

Z1 = R1|| 1sC1

= R11+sC1R1

Z2 = R2|| 1sCgs

= R21+sCgsR2

Zout = ROUT || 1sCOUT

= ROUT

1+sCOUT ROUT

iC1 = sCC1 (vOUT − vX)

iC2 = (v2−vY )

RC2+1

sCC2

= sCC2(v2−vY )1+sCC2RC2

igd = sCgd,PASS (vOUT − v2)

D. Pole-Zero Equations

Solve the equations in (1) so as to eliminate v1, v2, vOUT ,vX , vY , iC1, iC2 and igd to obtain the transfer functionALDO−RNMCB(s) = vFB(s)/vS(s) using symbolic manipu-lation software. Assuming that C1 � (CC1, CC2 and COUT ),and the poles are widely separated, small-signal analysis yieldsthe transfer function given by

ALDO−RNMCCB(s) ≈

ADC

(1 + sRC2CC2)(1 + s CC1

gmBU

)(1 + s

ωP1

)(1 + sRC2CC2)

(1 + s COUT

gmBU RC2gmP

) (2)

The open-loop dc loop gain of the regulator is given by

ADC = βgm1R1gm2R2gmPROUT , (3)

where β is the feedback factor. The dominant pole ωP1 occursat the output of the first stage and is given by

ωP1 ≈ −1/R1CC1gm2R2gmPROUT (4)

The second pole ωP2 is due to the inner loop compensationnetwork, given by

ωP2 ≈ −1/RC2CC2 (5)

Two LHP zeros are formed, one due to the outer loop and onedue to the inner loop, given by

ωZ1 = −gmBU

CC1(6)

ωZ2 ≈ −1/RC2CC2 (7)

From (5) and (7), we see that LHP zero ωZ2 effectively cancelsthe second pole ωP2. The third pole ωP3 is a non-dominantpole situated much after ωGBW . Higher order poles and right-half plane (RHP) zero due to Cgd,PASS are neglected. Theequations of poles and zeros of the LDO are given in Table II.The gain-bandwidth product is approximated as

Re

Im

ωP1

ωZ1ω

P2

ωZ2

ωP3

LDO - RNMCCB

ωZ3

≈

Fig. 4. Diagram illustrating pole-zero locations of Fig. 2 (not to scale).

ωGBW ≈gm1

CC1(8)

The Phase Margin of LDO can be expressed as

PM = 180o − tan−1

(ωGBW

ωP1

)+ tan−1

(ωGBW

ωZ1

)− tan−1

(ωGBW

ωP3

)(9)

≈ tan−1

(g2

m1COUT + g2mBUCC1gmPRC2

gm1gmBUCOUT

)As evident from Fig. 4, the LDO regulator’s response is

similar to that of a single-pole single-LHP-zero response withadequate phase margin (> 75o), depending on the locationωZ1.

TABLE IIPOLE-ZERO EQUATIONS OF LDO WITH RNMCCB (FIG. 2)

Parameter EquationADC βgm1R1gm2R2gmPROUT

ωP1 − 1R1CC1gm2R2gmP ROUT

ωZ1 − gmBUCC1

ωP2, ωZ2 − 1RC2CC2

ωP3 − gmBU RC2gmPCOUT

ωZ3 + gmPCgd,P ASS

IV. SOURCE DEGENERATED DIFFERENTIAL AMPLIFIER

The schematic of a bipolar differential amplifier with sourcedegeneration is shown in Fig. 5(a). The circuit contains de-generation resistor RDEG and degeneration capacitor CDEG.The source degenerated amplifier acts as a band-limited highpass filter whose high-pass corner frequency is defined by1/ (2πRDEGCDEG).

VIN+

IC

RDEG

QC1 QC2VIN-

IC

gmC

QC3 QM4

VOUT

VIN+

IC

RDEG

2CDEG

QC1 QC2VIN-

IC

gmC

QC3 QM4

VOUT

2CDEG

2 RDEG 2

mCg (vS–vA)

vS

vOUT

ROUT COUT

Ri

RDEG 2CDEG2

vA

(a) (b) (c)

CDEG

Fig. 5. (a) Schematic of the differential amplifier with source degeneration,(b) alternate representation, and (c) equivalent small-signal model.

Resistor RDEG can be represented with two series resistorsof value RDEG/2 and similarly, capacitor CDEG can berepresented with two series capacitors of value 2CDEG withthe intermediate nodes as virtual ground as shown in Fig. 5(b).The equivalent small-signal model of the differential amplifierwith source degeneration is shown in Fig. 5(c). The amplifier ismodeled with a VCCS gmC (vS − vA) in series with RDEG/2and 2CDEG in parallel to ground as shown in Fig. 5(c).

Let vS ≡ VIN+ − VIN−. Resistor ROUT and capacitorCOUT include any load attached to node VOUT . ApplyingKCL at every node in Fig. 5(c), the set of equations are

0 = gmC (vS − vA) +vOUT

ROUT+ sCOUT vOUT

0 = −gmC (vS − vA) +vA

0.5RDEG+ 2sCDEGvA(10)

Solving (10), we obtain the transfer function. The dc gainand the pole-zero equations of the source degenerated ampli-fier is given by

ADC =(

11/gmC + 0.5RDEG

)ROUT (11)

ωZ1 =1

RDEGCDEG(12)

ωP1 =1

ROUTCOUT(13)

ωP2 =gmC

2CDEG(14)

Observing the poles and zeros in (12)-(14), depending onthe values of RDEG and CDEG, zero ωZ1 is often designedappear first, followed by the first pole ωP1, and the secondpole ωP2, as shown in Fig. 6, to obtain the characteristic of aband-limited high pass filter (Fig. 7).

Re

Im

ωP1

ωZ1

ωP2

Fig. 6. Diagram illustrating pole-zero locations of Fig. 5 (not to scale).

V. PHASE-LEAD COMPENSATOR

Compensation techniques are used to achieve adequatephase margin for improving stability. Most of the compensa-tion techniques introduce an LHP zero to increase phase mar-gin (phase-lead). Often LDOs are compensated with external

Fig. 7. Magnitude and phase plot of source degenerated differential amplifier,shown as an example.

output capacitor equivalent series resistance (ESR) LHP zero,achieving phase-lead by inserting an LHP zero just before anon-dominant pole. This technique can also be implementedat an internal node of LDO by adding a resistor RZ in serieswith capacitor CC to ground as shown in Fig. 8.

gm1

VX

CC

RZR CX X

VS

vX

RXCC

m1vSg

RZ

CX

(a) (b)

Fig. 8. (a) Phase-lead compensator, (b) equivalent small-signal model.

The small-signal model of the phase-lead compensator isshown in Fig. 8(b).

Fig. 9. Magnitude and phase response of the amplifier with and withoutcompensator, shown as an example.

Applying KCL to the small-signal model and solving theequation, we obtain the transfer function. KCL equation is:

0 = −gm1vS +vX

RX+ sCXvX +

vX

RZ + 1/sCC(15)

Assuming the magnitude of CX and CC are comparable andR1 � RZ , the DC gain and pole-zero equations of the

VSENSE–

IC

RDEG

CDEG

QC1QC2

COUT

CFF

VLINE

VSENSE+

VSENSE–

VSENSE+ ILOAD

IC

IM IM

VBIAS1

VBIAS2

VREF

QD

CEA

RZ

VFB

QS QP

VOUT

RESR

RFB1

RFB2

VEA

QM5 QM6

QM3 QM4

QM1 QM2 QV1 QV2

IVIP

VB

RS

RD

D1

GV

gmD

gmD11

GI(s)

gmSgmP

gmi

gmi

Fig. 10. Transistor-level schematic of high power-supply rejection (PSR) current-mode LDO Regulator, adapted from [12].

IG (s)vIS

vIS

GVvS

vB

RB CB

mDvEA

gREA

vEA

RZ

CEA

vOUT

ROUT COUTmP

vBg

mS(vg

RS

viFB

B-v )

iFB

RESRR

FB1

RFB2

CFFvFB

i f

vS

Ri,v

Ri,iiEA

XXBreak Current Loop Here

XXBreak Voltage Loop Here

Fig. 11. Small-signal model of high PSR current-mode LDO Regulator in Fig. 10.

amplifier with phase-lead compensator are given by

ADC = gm1RX (16)

ωP1 =1

RX (CX + CC)(17)

ωP2 =1

RZ (CX ||CC)(18)

ωZ1 =1

RZCC(19)

where CX ||CC = CXCC/(CX +CC). Observing the expres-sion for the non-dominant pole ωP2 and LHP zero ωZ1 in (18),we note that the zero appears approximately one octave beforethe non-dominant pole. This helps in achieving phase-lead asshown in Fig. 9.

VI. HIGH PSR CURRENT-MODE DUAL-LOOP LDOFig. 10 shows the transistor-level schematic of the bipolar

current-mode dual-loop LDO of [12] with high power-supplyrejection (PSR) performance. This LDO contains two feedbackloops, a voltage loop and a current loop. The small-signalmodel and architecture of the LDO is shown in Figs. 11 and12.

The voltage loop is formed by GV with input pair QV 1 −QV 2, common-emitter transistor QD (−gmD), pass transis-tor QP (−gmP ) with sampling resistors RFB1, RFB2. Thecurrent loop is formed by sense transistor QS (gmS) withdegeneration resistor RS , high-pass filtering transconductanceGI (s) implemented with transistors QC1−QC2, degeneration

GV

REFV

Gi

gmD

RC

EA

EA

VEA

gmP

GmS(s)

RZ

VB VOUT

COUT

RESR

RFB2

RFB1 CFFROUT

RS

iS

iEA

R CB B

GmS1

gmS

1 RS

VFB

Fig. 12. Architecture of LDO with both voltage and current loops [12].

resistor RDEG and capacitor CDEG, and is fed into the voltageloop. GI (s) forms a high-pass filter characteristic with a bandlimited beyond the unity-gain-frequency of the voltage loop.The purpose of the amplifier QD is to decouple QP ’s largeparasitic capacitance from node vEA. Fig. 11 shows the small-signal model and the places to break the current and voltageloops. Equations of small-signal parameters of the LDO ofFig. 11 are given in Table III.

We apply KCL at every node in Fig. 11. The set of KCLequations obtained are

0 = iEA +GI(s) +GV vs

iEA = vEA

REA+ vEA

RZ+1/sCEA

0 = gmDvEA + vB

RB+ vBsCB (20)

0 = gmS (vB − viFB) + gmP vB + vOUT

ROUT+

vOUT

RESR+1/sCOUT+ if

gmS (vB − viFB) = viF B

RS

if = vOUT−vF B

RF B1+ (vOUT − vFB) sCFF

if = vF B

RF B2

TABLE IIISMALL-SIGNAL PARAMETERS OF LDO IN FIG. 11

GV gm of QV 1,QV 2

Ri,V βPNP /GV

gmC gm of QC1,QC2

GI(s)

(1

1gmC

+0.5RDEG

)1+sRDEGCDEG

1+s2CDEG

gmC

Ri,I βNPN/GI(s)

gmD , roD gm, ro of QD

gmS , roS gm, ro of QS

GmS1

1/gmS+RS

gmP , roP gm, ro of QP

gm4, ro4 gm, ro of QM4

ro6 ro of QM6

REA

(12ro6gm4ro4

)||βNPN/gmD ≈ βNPN/gmD

RB (1/gmD1 +RD) ||roD||βPNP /GmS ||βPNP /gmP

CB CbeQP + CbeQS + CbcQD

ROUT roP ||roS ||RL

βFB RFB2/ (RFB1 +RFB2)

The pole-zero equations obtained are tabulated in Table IV.The zero ωZ1 from GI (s) precedes the pole at output ωP1,as shown in Fig. 13. At higher frequencies, gmC (gm ofQC1/QC2) increases and forms a pole ωP2 with degenerationcapacitor CDEG. Pole ωP3 is due to CEA at node VEA andzero ωZ2 is due to RZ and CEA. Zero ωZ4 is due to RESR

and COUT .

TABLE IVPOLE-ZERO EQUATIONS OF LDO REGULATOR OF FIG. 10

Parameter Location EquationADC−LDO βFBGV REAgmDRBgmPROUT

ADC−GI (s)gmC

1+0.5RDEGgmC

ωZ1 GI (s) − 1RDEGCDEG

ωP1 VOUT − 1ROUT COUT

ωP2 GI (s) − gmC2CDEG

ωP3 VEA − 1CEA(REA+RZ)

ωZ2 VEA − 1RZCEA

ωP4, ωZ3 VFB − 1CF F (RF B1||RF B2)

ωZ4 VOUT − 1RESRCOUT

Re

Im

ωP1

ωP3

ωZ2

ωZ1

ωP2

ωP4

ωZ3

ωZ4

Fig. 13. Diagram illustrating pole-zero locations of Fig. 11 (not to scale).

VII. CONCLUSIONS

In this tutorial, we have analyzed poles and zeros of twostate-of-the-art LDO regulators. We outlined the steps forfinding poles and zeros and applied those steps to a three-stageLDO and a high PSR LDO. A wide range of compensationtechniques were illustrated including RNMC using currentbuffers, phase-lead compensation and current-mode feedbackwith a high pass filtering characteristic. The derived analytic

expressions for poles and zeros help in developing intuition ofcircuit behavior.

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