politecnico di milano · quest’anno ricorre il decimo anniversario dalla scoperta del grafene e...

POLITECNICO DI MILANOSchool of Industrial and Information Engineering

Master’s Course in Electronic Engineering

GRAPHENE FET LARGE-SIGNAL

MODELING FOR ANALOG

CIRCUIT-DESIGN

Master’s thesis by Valerio Lo Muzzostudent number: 787422

Supervisor: Prof. Andrea Leonardo LacaitaPolitecnico di Milano

Co-supervisor:Prof. Eduard AlarconUniversitat Politecnica de Catalunya

Academic year 2013 - 2014

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Preface and acknowledgements

Generally a master’s thesis represents the master’s studies end and in some-way the end of a student-life. From an engineering point of view it couldbe seen as the threshold between the passive learning-time, where the stu-dent has to absorb a lot of information, and the active proposal-time, wheresomething new has to come out from the future engineer. It is like a gamewhere the student has to learn the rules in order to become a player, thus anengineer.This thesis job would like to break the rules of the silicon-age, exploring a newtechnology that seems very promising in the long term. However silicon haschanged the world as well as fusel oil and their close looks rather similar, be-cause the silicon-scaling, as the oil reserves, will perish soon even though wedon’t know yet when it will happen, hence something new is required by theelectronics industry and in this case we are talking about graphene, which isoften defined as the material of the 21st century. I think that graphene couldrepresent a great opportunity for a young electronics engineer, comparing itto silicon 50 years ago. Moreover graphene could offer great opportunities toEurope, which is not living a good moment, hence an intrinsic political valueis hidden into each carbon atom.

Due to the reasons above illustrated, this thesis is not written just toachieve a final mark, but it would like to make a point on GFET-technologyand to develop something new of it. In this case "something new" means atransistor large-signal compact model and its circuit-level characterization,which I hope it could be useful for people working in the same field. Thewriting-spirit of this thesis is mainly described by the loop: goal-problem-

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proposed solution-validation, but sometimes the latter cannot be verified dueto the absence of feasible experiments. Furthermore the divide et impera andrepetita iuvant latinism approaches are followed to find where is the problemand to recall and link those concepts which have a closer-meaning but arenot-so-close in the thesis structure.

Moving on some personal acknowledgments, I would like to thank prof. Ed-uard Alarcon because he gave me the opportunity to join this world-classproject as visiting researcher at UPC Barcelona (Spain) in cooperation withresearchers at KTH Stockholm (Sweden) and University of Siegen (Ger-many), while there is no huge "thank you" that could requite Mario Iannazzo(UPC Barcelona), technically my co-supervisor, practically a loyal profes-sional reference. Moreover a sincere "thank you" for their useful feedbacks isdirected to prof. David Jimenez (UAB Barcelona), Gerard Landauer (UPCBarcelona), Saul Rodriguez, Ana Rusu (KTH Stockholm) and prof. MaxLemme (University of Siegen). A great "thank you" is aimed to prof. AndreaLeonardo Lacaita (Politecnico di Milano), which welcomed my proposal assupervisor and gave me some significant professional-suggestions.

Valerio Lo MuzzoMilan, December 2014

Abstract

This year occurs the 10th anniversary of graphene discovery and giving aquick look to the past the enormous quantity of scientific productions explainwhy graphene is defined as the material of the 21st century. Thanks to itsamazing properties such as high carrier mobility and high saturation velocity,graphene could replace semiconductors in the long term, especially in the RFfield.

On the other hand, many drawbacks are associated to graphene-basedstructures,which are affected by parasitics, a typical issue in immature tech-nologies. Nevertheless, many circuits have already been implemented pavingthe way to the future carbon-based electronics.

In this master’s thesis the state-of-the-art of graphene technology is pre-sented, focusing the attention on graphene field-effect-transistors. Hence theGFET compact modeling state-of-the-art is analyzed and a new compact-model for large-signal circuit-design is presented. The model, based on thedrift-diffusion transport, has been implemented in Verilog-A language andcarefully characterized in a circuit simulator environment, proving its robust-ness for different transistor and circuit parameters. The proposed compact-model is well matched to DC-experimental measurements, while the lackof data related to GFET dynamic behavior cannot confirm the simulationresults.

Furthermore design-oriented characterizations of ring-oscillator (RO) andcascode circuits are presented using both a bottom-up approach to providethe circuits guidelines and a top-down approach to refine GFET models andin turn GFET technology.

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The transient simulations of 3-cell RO take the operating frequency and thevoltage dynamic-range as performance metrics, while the cascode DC-basedsimulations take the output conductance and the saturation voltage. In thefirst case a design-space exploration is covered using as input variables thegate-oxide thickness tox and channel-length L.

Sommario

Quest’anno ricorre il decimo anniversario dalla scoperta del grafene e lagrande quantità di ricerca scientifica condotta nel corso di questi anni sp-iega perché il grafene è spesso definito come il materiale del 21esimo sec-olo. Grazie all’elevata mobilità dei portatori e alla loro altrettanto elevatavelocità di saturazione il grafene è un ottimo candidato per sostituire i co-muni semiconduttori in un futuro a lungo termine, specialmente nel campodell’elettronica a radiofrequenza. Nonostante lo stato dell’arte dei dispositivia grafene è attualmente limitato dai parassitismi (piú o meno chiari), alcunicircuiti integrati sono stati realizzati aprendo così le porte ad una elettronicafuturistica avente come elemento di riferimento il carbonio e non piú il silicio.

In questa tesi viene inizialmente presentato lo stato dell’arte della tecnolo-gia a grafene, concentrando lo studio principalmente sui transistori ad effettodi campo, alias GFET. Successivamente viene analizzato lo stato dell’arte delGFET-compact-modelig e viene presentato un nuovo modello a largo segnale.Detto modello, basato sul trasporto dei portatori di tipo diffusivo, è statoimplementato in linguaggio Verilog-A, quindi attentamente caratterizzato inun simulatore tipo SPICE. La robustezza e l’affidabilità del modello sonostate provate per mezzo di simulazioni sia di tipo transistor-level che di tipocircuit-level. I risultati delle simulazioni transistor-level risultano compatibilicon le misure sperimentali estratte in DC, mentre l’assenza sia di misure chedi simulazioni fisiche attendibili in AC non permette alcun riscontro modello-misure per ció che riguarda il comportamento dinamico del dispositivo.

Infine alcune caratterizzazioni a livello circuitale vengono presentate com-

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binando gli approcci bottom-up, al fine di produrre le linee guida per unoscillatore ad anello ed un amplificatore cascode, e top-down al fine di avereun feedback utile sia per il modeling che per la tecnologia.L’oscillatore ad anello è stato caratterizzato per mezzo della frequenza di os-cillazione e del dynamic-range, mentre l’amplificatore cascode è stato carat-terizzato per mezzo della conduttanza d’uscita e della tensione di saturazione.Nel caso dell’oscillatore ad anello vengono anche analizzati gli effetti dovutialla variabilità della lunghezza di canale L e dell’ossido di gate tox.

Contents

Preface and acknowledgements i

Abstract iii

Sommario v

1 Introduction 1From silicon to graphene electronics . . . . . . . . . . . . . . . . . . 1

2 Graphene Technology 72.1 Relevant graphene properties . . . . . . . . . . . . . . . . . . 72.2 Graphene fabrication . . . . . . . . . . . . . . . . . . . . . . . 112.3 Graphene transistors . . . . . . . . . . . . . . . . . . . . . . . 11

3 GFET compact modeling 173.1 State-of-the-art of GFET DC-models . . . . . . . . . . . . . . 19

3.1.1 Thiele’s model . . . . . . . . . . . . . . . . . . . . . . . 203.1.2 Fregonese’s model - GFET9 . . . . . . . . . . . . . . . 233.1.3 Extrinsic resistances modeling . . . . . . . . . . . . . . 263.1.4 GFET9 - Characterization and comparison to measure-

ments . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.2 Our new DC odel proposals . . . . . . . . . . . . . . . . . . . 30

3.2.1 First model proposal: GFET 13 . . . . . . . . . . . . . 303.2.2 Understanding the artefact nature in GFET9 . . . . . 333.2.3 Second model proposal: GFET12 . . . . . . . . . . . . 35

3.3 State-of-the-art of GFET AC-models . . . . . . . . . . . . . . 36

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3.3.1 Thiele capacitances modeling . . . . . . . . . . . . . . 393.3.2 Fregonese capacitances modeling . . . . . . . . . . . . 41

3.4 New AC-model proposals . . . . . . . . . . . . . . . . . . . . . 423.4.1 First AC-model proposal: GFET13 . . . . . . . . . . . 423.4.2 Second AC-model proposal: GFET15 . . . . . . . . . 46

3.5 Our final compact-model proposal - GFET14 . . . . . . . . . . 473.6 Chapter conclusions . . . . . . . . . . . . . . . . . . . . . . . . 47

4 GFETs circuits characterization 504.1 Large signal compact-models comparison . . . . . . . . . . . . 514.2 Characterization of GFET based

inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554.3 Characterization of GFET based

Ring-Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . 584.4 Characterization of GFET based

DC Cascodes . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.5 Chapter conclusions . . . . . . . . . . . . . . . . . . . . . . . . 62

5 Final Conclusions 65

A Relevant analog/RF transistor FOMs 67

References 69

List of Figures

1.1 Modern scaling enhancements [10]. . . . . . . . . . . . . . . . 31.2 Logic technology roadmap and alternatives. [14], modified. . . 31.3 More Moore, More than Moore and Beyond CMOS concepts [15]. 41.4 Graphene roadmaps [27]. . . . . . . . . . . . . . . . . . . . . . 5

2.1 Carbon allotropes derived from graphene. Fullerene (green),carbon nanotubes (purple) and graphite (blue) [41]. . . . . . . 9

2.2 Graphene bandgap structure [33]. . . . . . . . . . . . . . . . . 102.3 a)Ambipolar conduction; b)Different graphene bandstructures.

[34] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.4 a)Mobility vs bandgap comparison for different materials [34];

b)Different fabrication methods trade-off [55]. . . . . . . . . . 122.5 Properties of graphene obtained by different methods [55]. . . 132.6 Cross-sectional schematic of the device proposed in [60, 61]. . 142.7 DC measurements [60, 61]. . . . . . . . . . . . . . . . . . . . . 142.8 Measured DC I-V curve in [62]. . . . . . . . . . . . . . . . . . 15

3.1 Carrier transport in MOSFETs depends on relative dimensionof the device size and the mean free path [85]. . . . . . . . . . 19

3.2 GFET equivalent circuit [79]. . . . . . . . . . . . . . . . . . . 203.3 GFET device symbol with extrinsic resistances included. [38],

modified. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273.4 IDS vs VDS for different VGS values - Cadence simulations. . . 283.5 DC measurements from [60]. . . . . . . . . . . . . . . . . . . . 293.6 GFET9 - Distortion details. . . . . . . . . . . . . . . . . . . . 313.7 GFET13 IDS − VDS and IDS − VGS characteristics. . . . . . . 34

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3.8 y1, y2 integral extremes curves and IDS-VGScharacteristic -Cadence simulations. . . . . . . . . . . . . . . . . . . . . . . . 35

3.9 GFET13 vs GFET12 characteristics comparison. . . . . . . . . 373.10 GFET small-signal equivalent circuit [76]. . . . . . . . . . . . 393.11 Cgs(VGS) curve based on Thiele’s modeling. . . . . . . . . . . . 403.12 CGS(VGS) and CGD(VDS) curves based on Fregonese’s modeling. 423.13 GFET13 - CGS(VGS) curve for L = 440nm,W = 1µm, VDS =

0.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433.14 GFET13 -QCH(VGS) and CGS(VGS) curves for L = 440nm,W =

1µmVDS = 3V . . . . . . . . . . . . . . . . . . . . . . . . . . . 443.15 GFET13 QCH(VGS), CGS(VGS), QCH(VDS), CGD(VDS) curves. . 453.16 L vs DEN2 comparison. . . . . . . . . . . . . . . . . . . . . . 463.17 GFET15 QCH(VGS), CGS(VGS), QCH(VDS), CGD(VDS) curves. . 483.18 A GFET symbol and a hybrid-π model for large-signal analysis. 49

4.1 A device-level comparison between our GFET14 (solid lines)and Rakheja (dashed lines) models fitted to Meric technology. 54

4.2 A device-level comparison between our GFET14 (solid lines)and L&J (dashed lines) models fitted to Meric technology. . . 56

4.3 A Ring Oscillator (a) based on 3 Complementary Inverters (b)implemented with 2GFETs. . . . . . . . . . . . . . . . . . . . 57

4.4 A circuit-level comparison between our GFET14 (solid lines)and Rakheja (dashed lines) models fitted to Meric technology.The circuit parameters used include a transistor aspect-ratioof (W

L)1,2 = 1µm

440nm. . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.5 A circuit-level comparison between our GFET14 (solid lines)and Rakheja (dashed lines) models fitted to Meric technology.The circuit parameters are (W

L)1,6 = 10 and VDD = 5V . . . . . 59

4.6 A GFET cascode (a) and a GFET self-cascode (b) circuitsimplemented with 2 GFETs. . . . . . . . . . . . . . . . . . . . 61

4.7 A circuit-level comparison between our GFET14 (solid lines)and L&J (dashed lines) models fitted to Meric technology. . . 63

A.1 A FET transistor small-signal equivalent circuit [34]. gm is thetransconductance, gds is the output conductance, Cgs is thegate-source capacitance and Cgd is the gate-drain capacitance.RD , RG and RS are parasitic extrinsic resistances, while Ri

is the intrinsic gate resistance. . . . . . . . . . . . . . . . . . . 68

List of Tables

2.1 Meric technology parameters [60]. . . . . . . . . . . . . . . . . 14

3.1 Physical vs Compact model parameters fitted with Meric tech-nology [79, 60]. . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.1 GFET14 model parameters fitted with Meric technology [79, 60]. 524.2 MIT+IBM (Rakheja) Compact model parameters fitted with

Meric technology [72, 60]. . . . . . . . . . . . . . . . . . . . . 534.3 L&J Compact model parameters fitted with Meric technol-

ogy [84, 60]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

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Chapter 1

Introduction

From silicon to graphene electronics

With the transistor invention, occurred in the late 1947, the word "end"was written on the vacuum tube era which was going to be replaced by theemerging semiconductor electronics that offered new scenarios, new possibil-ities and new challenges.At that time the semiconductor field was not so known by the scientificcommunity and the Bell Labs team, headed by W. Shockley and S. Morgandecided to work on the two simplest semiconductors: silicon and germanium.That was a right decision because two years later they reached the goal torealize the first transistor, but no one knew what was the theory that wasmastering such a magic device. A clearly answer came out when W. Shockleywrote down the theory that the world was looking for and when he imple-mented the first germanium npn junction transistor in 1950 [1]. In the sameyear Shockley’s theory became a book titled: Electrons and Holes in semi-conductor with applications to transistor electronics [2].On the way of enthusiasm during ’50s, most scientists and engineers, at-tracted by the potential and the possibility to control those powerful mate-rials, spent a lot of time in order to understand how semiconductors workand how humans can influence and manage such materials. Moreover theNobel Prize in physics assigned to W. Shockley, J.Bardeen and W. Brattain

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CHAPTER 1. INTRODUCTION

"for their researches on semiconductors and their discovery of the transistoreffect" in 1956 amplified the scientific community interest in the semiconduc-tors field. In 1952 the first unipolar transistor, whose concept was previouslypatented in 1926 by Lilienfeld [3], was realized by I. Ross and G. Dacey [4]and in 1960 the first MOSFET was developed at Bell Labs by M.M. Atalla’sgroup [5]. Once the device was created the semiconductor companies bornduring ’50s were looking for a process in order to start a mass-production.Therefore in 1957 Texas Instruments invented the mesa transistor that al-lowed J. Kilby to build the first integrated circuit. The second step was donein Fairchild semiconductors when J. Hoerni developed the planar process fortransistor [6] and R. Noyce made his integrated circuit using that technologyin 1959. Thereupon the way of any electronic/semiconductor company wasoutlined, thanks to two transistor types and the planar process that allowedtheir connection [7].From 1960 up to early 2000s thanks to Dennard’s scaling rules [8], the semi-conductor industry had been the ability to shrink the MOSFET device fol-lowing the exponential speed predicted by Moore in 1965 [9], but with the130nm node the classical Dennard scaling ends and the "More Moore" (MM)era started. The MM concept does not change the CMOS physical principle,but introduces new technological aids in order to further downscale the de-vice. In a nutshell, the 130nm was the last CMOS generation that allowedbetter performance just thanks to its smaller dimensions. Therefore, sincethe 90nm generation an important change happened: the channel lattice wasstrained to get better performance. This was the first signal that opened thedoor to new materials in order to replace the silicon channel in the future.Later on others enhancement (as high K + metal gate) were added in the45nm node and few years ago, for the first time after more than 4 decades,the planar structure was replaced by the 3-dimensional architectures, gener-ically called multiple gate architectures (MuGFET) as shown in Figure 1.1.

Nowadays the 2013 ITRS predicts the implementation of high-mobilityCMOS channel materials in the near term 2013-2020 [11]. At the time ofthis writing Intel has just marketed the 14nm node and it is looking for

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(a) Strain and Hi-K-MG contributions. (b) Multiple-gate architectures.

Figure 1.1: Modern scaling enhancements [10].

the next 10nm generation. Another big manufacturer, IBM, has recentlystarted the program 7nm and beyond which is looking for new materials andcircuit architecture designs compatible with the CMOS process. For thisreason IBM decided to invest 3 billion dollars in III-V technologies, nextgeneration low power transistor as tunnel field effect transistors (TFETs),Carbon nanotubes (CNT) and Graphene transistors (GFETs) [12]. IBMhas played an important role on GFETs development and the world’s firstgraphene based integrated receiver front end for wireless communication wasdemonstrated by Big Blue in the late 2013 [13]. Taking as reference theIBM timeline we could affirm that the introduction of GFETs technologywill occur beyond the 7nm generation as shown in Figure 1.2.

Of course Graphene is just one of the aspirant materials that could re-

Figure 1.2: Logic technology roadmap and alternatives. [14], modified.

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Figure 1.3: More Moore, More than Moore and Beyond CMOS concepts [15].

place Silicon in the next future. Despite it was discovered quite recently (just2004) it is seen as the magic material that could revolutionize the entire elec-tronic future scenario, because it founds a lot of electronic applications inthe so called "More than Moore" and "Beyond CMOS" segments.The "More than Moore" (MtM) concept incorporates all those technologiesthat enable non digital micro/nanoelectronic functions which do not neces-sarily respect the Moore law, while the "Beyond CMOS" (BC) definition in-corporates all those technologies where the information is not charge-based,but it is carried by new state variables as spin, molecular state, photons,phonon, magnetic flux, etc. Figure 1.3 summarize the concept.Graphene broadband photodetection [16], graphene NEMS [17], graphenebased hot electron transistor (GBT) [18] and others [19, 20, 21, 22, 23] arejust examples of MtM graphene devices, while BiSFET [24], graphene ther-mal logic and graphene p-n junction logic are few examples of beyond CMOSgraphene technology [25] . Further information on alternative state variablesfor graphene transistors are available in [26].

All these experiments related to graphene electronics proof why the world

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(a) Schematic presentation of the scientific and technological roadmap.

(b) A technology-oriented graphene roadmap.

Figure 1.4: Graphene roadmaps [27].5


looks at this wonderful 2D material with an optimistic view. Thanks tothe Nobel Prize 2010 in Physics awarded to A. Geim and K. Novoselov "forgroundbreaking experiments regarding the two-dimensional material graphene",the research on graphene electronics has grown drastically and in 2013 theEuropean Commission announced a 1 billion euro investment in grapheneresearch and development that will be spread in the next 10 years. This bigproject, dubbed "The Graphene Flagship" , wants to start the commercial-ization of graphene based electronics during the 2020s and it proposes thegraphene roadmaps illustrated in Figure 1.4

Out of all fields where graphene could be used, this master thesis focusesits attention in the "More than Moore" segment related to analog/RF appli-cations. GFETs look as a good candidate in order to develop the future RFtransceivers, thanks to the amazing properties of graphene that are describedin Chapter 2. Taking the results from GFETs physics, in Chapter 3 a com-pact model is implemented in VerilogA language, to be used in SPICE-likesimulators. Other models are also commented and analyzed. As a final stepChapter 4 describes the results achieved by simulating circuits as Cascodes,Ring Oscillators and Inverters benchmarking different models.This thesis book is presented in a bottom-up way, as common in IC maturetechnologies, where the flow design is implemented from device to circuitlevel, but as the reader will understand during his reading path, in an emerg-ing technology, as graphene, there is a concurrent top-down and bottom-upinteraction from circuit design to device model and vice-versa. Therefore ourphilosophy is based on a co-design approach.

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Chapter 2

Graphene Technology

The big-ben year for graphene was the 2004 when Novoselov and Geim iso-lated it for the first time using the so called scotch-taped method [28]. Lateron its electrical properties were investigated and the first Top-gated graphenetransistor was realized by Lemme in 2007 [29]. A lot of graphene structureswere developed during last years and the first integrated circuit, a mixer upto 10GHz, came out in 2011 [30].In this chapter we are going to explore the graphene properties, the most usedtechniques to produce large-area graphene sheets and the current saturationeffect on graphene field effect transistor (GFET).

2.1 Relevant graphene properties

Graphene is the 2D atomic layer of carbon atoms used to describe othercarbon-based structures as fullerene, carbon nanotubes and graphite as shownin Figure 2.1. Natural large-area graphene has been presumed not to existin free state until the Manchester University group job was published.

Electrical properties The crucial property that makes graphene inter-esting for high speed electronics is the high mobility which record value of3 · 106cm2V −1s−1 was measured in suspended samples at low temperatureand low carrier densities [31, 32]. Of course mobility depends on technology

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CHAPTER 2. GRAPHENE TECHNOLOGY

and is afflicted by the substrate mismatch. A mobility of 2.5 ·105 cm2V −1s−1

has been achieved using a h−BN substrate, while in devices based on SiO2

substrate the mobility falls down in the range 1000 − 40000 cm2V −1s−1 aswell benchmarked in [33]. As comparison Silicon MOSFETs show a chan-nel mobility on the order of few 100 cm2V −1s−1, while III-V semiconductortransistors present values up to 10000 cm2V −1s−1.Despite graphene is just one-atom thick it could provide a minimal carriersheet density in excess of 1012 cm−2 that is enough for FET operations [34].Furthermore, carrier saturation velocity shows its dependence from the car-rier density as a function 1/n0.5 [35] and presents peak values of the orderof 107cm/sec [36, 37, 38]. The maximum carrier speed achievable in 2D-graphene is theoretically the Fermi velocity vF = 106 m/s which has in-teresting relativistic consequence as explained in [33]. Another importantelectric property involves the carrier mean free path that is strictly relatedto scattering phenomena. In the Manchester group job a mean free path of0.4µm was measured [28], while a larger value than 1µm was reported in [39].The mean free path is an important property that rigorously depends on thegraphene quality and plays an essential role on the transport phenomena aswe will see in Chapter 3. Other important properties are deeply describedin [40].

Bandstructure Looking at the graphene structure, valence electrons aresp2 hybridized with the pz orbital that forms a π-electron responsible for thelow energy transport and optical properties. The lattice is a benzene-ringstructure, where the bond length between adjacent carbons, Lb, is 1.42 Å andthe lattice constant a is 2.46 Å. Each bonding π-state forms the valence band,while the antibonding π* forms the conduction band. The two bands intersectat a single point of zero states dubbed "Dirac-point" or "charge neutralitypoint" CNP. Hence the global lattice bandstructure is composed by six el-ementary two-band systems as shown in Figure 2.2. In intrinsic (undoped)graphene the Fermi level is situated at the Dirac point of each coin-shapedband structure, but it can be changed by applying an electric field that could

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Figure 2.1: Carbon allotropes derived from graphene. Fullerene (green),carbon nanotubes (purple) and graphite (blue) [41].

mutate the material into n-doped or p-doped depending on the polarity.

To understand that we assume to apply a positive voltage that moves theFermi level from the equilibrium point EF2 to a new level in the conductionband depicted EF1 in Figure 2.3 a). Hence the material becomes n-doped andif we image it as a channel in a MOS structure, there will be an electrons fluxcorresponding to the drain current ID1. The same effect happens applying anegative voltage that moves down the Fermi level into the valence band EF3

and makes the channel p-doped with a holes flux instead of electrons-fluxthat is the origin of a drain current ID3 if an electric field is applied betweensource and drain. This behavior is called ambipolarity since the symmetri-cal bandstructure around the Dirac point implicates that electrons and holesshould have the same properties in pure graphene. This explain the simme-try between holes current and electrons current.Standing to the theory, the Dirac-point presents zero available states, thusit could be an off-point for a MOS device, but it is practically not achiev-

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Figure 2.2: Graphene bandgap structure [33].

able due to some puddles originated by the inevitable disorder that causesa minimal conductivity [42]. From this analysis it is clear how a possiblegraphene FET structure cannot presents an off-state that is a fundamentalrequirement for a VLSI digital design. For this reason, nowadays, a FETtransistor based on single-layer large-area graphene looks to be applied inthe analog/RF field where an off-state is not strictly necessarily.

Bandgap opening The question now is: should we find a way to opena gap between the valence and the conduction bands? A first solution isoffered by graphene nanoribbons (GNR) which are formed when graphene ispatterned into a narrow ribbon trying to confine the carriers in a quasi one-dimensional (1D) system. Ab-initio calculations have predict how changingthe graphene geometry a band-gap could be induced [43]. Experimentalresults have been reported [44, 45, 46] and a record value of 0.5eV was mea-sured in a 2.5nm wide ribbon [47]. Nevertheless the bandgap origin in GNR isstill not clear and probably consequence of other physic effects as Coulombblockade and Anderson localization [48, 34]. Further details on electronicproperties of GNR are available in [49].A band-gap opening was observed in bi-layer graphene which bandstructureis still gapless, but is tunable reaching values of 200− 250meV if an electricfield is applied vertically to the bi-layer [50, 51, 52]. Figure 2.3 b) summarizebandstructure differences. Besides a 200meV gap was opened by straining

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the graphene sheet [53], but the minimum required gap for a digital logic is of360−500meV [52]. Unfortunately as a general trend in physic semiconductorthe larger is the bandgap, the lower is the mobility as shown in Figure 2.4a).Experimental results confirm this trend [54].

2.2 Graphene fabrication

A high-quality, scalable, Si CMOS compatible and economical graphene pro-cess is the first requirement in order to produce graphene electronics. The"scotch taped method" proposed by Novoselov and Geim [28] is a rough ex-ample of mechanical exfoliation technique, which offers high quality samplesbut has not industrial relevance due to its scaling limits. Samples of indi-vidual crystals can reach millimeter range which makes this technique usefuljust for the study of fundamentals properties.

Looking at those process that are scalable a low cost-low quality option isoffered by liquid-phase exfoliation tecnique, suitables for flexible electronics.A good quality-costs trade-off is offered by SiC thermal decomposition, whichmajors drawbacks involves the SiC high cost and the high process tempera-ture (in the range 1200− 1600 ) that makes this technique not compatiblewith a standard Si-CMOS process. The best solution looks to be the chemi-cal vapor deposition (CVD), which offers high quality graphene sheets thatcan be transferred into any substrate such SiO2 and h−BN , hence makingthe process Si-CMOS compatible. Recently a roll-to-roll CVD process hasproduct a 100m long high quality graphene sheet [56]. Many issues have tobe solved in order to make CVD widely used, but it looks the most promisingoption in the future [55, 33, 31, 34, 38]. Figures 2.4 b) and 2.5 give a compactvisual trade-off between different processes.

2.3 Graphene transistors

A lot of graphene transistor structures have been proposed during last years.In this section will be analyzed the classical MOSFET architecture having a

11


(a) (b)

Figure 2.3: a)Ambipolar conduction; b)Different graphene bandstructures.[34]

(a) (b)

Figure 2.4: a)Mobility vs bandgap comparison for different materials [34];b)Different fabrication methods trade-off [55].

12


Figure 2.5: Properties of graphene obtained by different methods [55].

large-area gapless graphene sheet as a channel, called GFET in the following,applied for analog/RF purposes. Other transistor structures, as GBL-FETs,GNR-FETs and Tunnel graphene FETs are not considered.In order to compare GFETs with other transistor types two important FOMsas fT and fmax are used. The reader could find a brief FOMs description inAppendix A.Projections predict that the more mature III-V semiconductor technologywill be replaced by GFETs in the early 2020s, when device requirements willbe more stringent, asking for fT up to the THz range. Nowadays GFETscompetitive values of fT have been reported, reaching a maximum measure-ment of 427 GHz in a 67 nm transistor [57], which is not so far from the688 GHz record measured in 40 nm GaAs mHEMT. Furthmore GFETs the-oretical fT values of the order of 1THz have been predicted [58], while themaximum fT expected for III-V material will not accomplish the 850GHz

requirement [55].Unfortunately GFETs maximum fmax registered was just70 GHz, really far if compared with the several hundreds of GHz of III-VFETs [59].

For this thesis job the reference technology is the top-gated GFET tran-sistor presented by I. Meric in [60], where a graphene channel is grown on ah−BN substrate by using a high-pressure high-temperature method as de-picted in Figure 2.6. Three GFETs with different channel length (3µm, 1µmand 440nm) were realized. DC curves illustrated in Figure 2.7 show howcurrent saturation occurs in each samples. The most important parametersrelated to the 3µm transitor are summed up in Table 2.1.

13


Physical

µ mobility 10000 cm2V −1s−1

W/L aspect ratio 3.4 µm/2.8 µmtox gate-oxide thickness 8.5 nmn0 minimum sheet carrier concentration 2.2 · 1011 cm−2

Small signal

gm (peak) transconductance 400mS/mmgm · ro intrinsic-gain 46

Table 2.1: Meric technology parameters [60].

Figure 2.6: Cross-sectional schematic of the device proposed in [60, 61].

Figure 2.7: DC measurements [60, 61].

14


Current saturation The basic question related to GFETs is: why doescurrent saturation occur? The answer has to be sought into the gaplessnature of graphene. This section gives just a qualitative analysis in order tounderstand the physical principle. A deep explanation is done in Chapter 3.First of all the gate-bulk volgate defines the carrier type depending by thepolarity. Let assume a fixed positive Vgb which makes the channel p-dopedif Vds = 0. To drawn an I-Vds curve, we increase continuously the drainvoltage detecting a linear current response. In a nutshell: the higher Vds is,the intense is the current as shown the first part I of Figure 2.8.When the drain voltage achieves the gate voltage value, the graphene sheetat the drain point reach the CNP, for that we have the lowest conductivitydue to the minimal carriers density. Therefore the current does not increaseas well is done by Vds, but shows a sort of saturation effect marked as II inFigure 2.8.Further increases of drain voltage will move the CNP toward the source, whilethe channel part near the drain becomes n-doped due to the negative gate-channel voltage. Once the electrons charge is greater than the hole charge, thecurrent intensity starts to increase again linearly with Vds as depicted in part

Figure 2.8: Measured DC I-V curve in [62].

15


III of Figure 2.8. Hence current saturation effect is a direct consequence of thesmoothly change from p-doped channel to n-doped channel. The CNP pointin the ambipolar regime is the place where recombinations occur betweenholes coming from the source and electron flowing from the drain. Due to thegapless nature of graphene, no energy is released in this recombination [62].

Drawbacks Many handicaps afflict the GFETs behavior such as low on-off current ratio, degraded carrier mobility caused by surrounding materials,high metal-graphene contact resistance, Klein tunneling and low current sat-uration which impairs high intrinsic-gain. The bandgap opening could im-prove the on-off ratio and the current saturation, while the Klein tunnelingeffect could be visible for device with L < 100nm [63, 64, 65].The main drawback is related to the contact resistance due to the metal-graphene junction, minimized if palladium electrodes are used [66]. Moreoverdue to the metal-graphene workfunction difference, the graphene-underneaththe electrode will result doped hence an heterojunction between graphene-underneath-metal and graphene-in-channel-region is formed. Since the chan-nel is gate-controlled, the heterojuction could be p-p’ at the source and p-n atthe drain (or vice-versa) hence asymmetric electric current for electrons andholes could be observed, especially for short-channel GFETs. Another sourceof deterioration is the access resistance included between the source/drainedge and the gate edge. Its contribution could be nil if source, drain andgate are properly aligned as common in a CMOS process. Unfortunately theion implantation used for CMOS device is not applicable for GFETs due tothe graphene too fragile 2D structure [31]. Hence new solutions are neededas the T-shaped GFETs proposed in [67, 68].

16

Chapter 3

GFET compact modeling

As emerged from previous chapters, the most promising scenario related tocurrent GFETs state-of-the-art involves applications in small-signal analogand extremely high-frequency (EHF) circuits. To design and simulate basicGFETs circuit as mixers, LNAs, oscillators ans so on, compact-models haveto be developed trying to describe the physical phenomenas as accurate aspossible and in the simplest mathematical way.

Commonly in engineering modeling, a physical phenomenon responds tosome laws depending by its macroscopic/microscopic nature. In the electron-ics field it is better to talk about microscopic/nanoscopic modeling, becausethe transport of a carrier is strictly related to its mean free path. Hencethe question is: how long is the mean free path (MFP or λ) in graphenetransistors? The answer is not trivial due to the strong dependence of thegraphene sheet quality. In the sample reported by Manchester group [28],the mean free path registered was around 400nm, while micrometer valueshave been reported in graphene under proper experimental conditions [39].On the contrary, under practical conditions for common dielectric substrates,room temperature and ambient environment, MFPs of a few hundreds nmhave been registered [69, 70]. However the mean free path limiting factorsare still under debate [69].

17

CHAPTER 3. GFET COMPACT MODELING

The drift-diffusion (DD) theory used up to today to simulate electronicdevices is still applicable while the transistor gate length is bigger thanthe MFP. Otherwise the carrier transport is mastered by quantum ballisticphysics as shown in Figure 3.1. Therefore, standing to the common MFPsvalues, for channel lengths (L) above 1µm the drift-diffusion theory is stillapplicable with accuracy, while in the sub-100nm range ballistic transporthas to be considered. For 100nm < L < 1µm, transistors work under theso-called "quasi-ballistic regime" where the drift-diffusion description is notso more accurate due to the weak scattering condition. Even if L ∼ λ arecent study has shown how the current-voltage characteristic of nanoscaledevices is stil well described by DD models if mobility and saturation velocityare treated as fitting parameters. Unfortunately the channel charge vs gatevoltage is overestimated making the AC modeling a bit complex [71].For GFETs in the sub-100nm range numerical models are a must to pre-dict their performance, thanks to the accurate modeling of band-to-bandtunneling phenomena and ballistic transport. These models are numeri-cal and are based on non-equilibrium Green’s function (NEGF) [65], hencethey are very time consuming in computation terms. However the imma-ture graphene process has not implemented ultra-short GFETs yet, but topredict the graphene scaling trend the sub-100nm modeling is a big chal-lenge for the future. Recently a Si-nanoMOSFET compact-model based onquasi-ballistic transport was adapted to GFET technology [72], followingprevious works done during last years [73, 74], while several other proposals,both analytical and numerical, are based on the most common DD the-ory [75, 76, 62, 77, 78, 79, 80, 81, 82, 83, 84].

Despite there are two-different physical approaches in modeling, the finalresult oriented to circuit simulators has to be an analytical/compact modelwhich requires just closed-form equations, even if some physical effects have amathematical translation into iterative equations. Therefore approximationsand mathematical tricks come into play, trying to be as accurate as possible.In this chapter drift-diffusion models are analyzed both in DC and AC andsome new proposals are presented.

18


Figure 3.1: Carrier transport in MOSFETs depends on relative dimension ofthe device size and the mean free path [85].

3.1 State-of-the-art of GFET DC-models

The main difference between common Si-MOSFET and GFET is the pres-ence of a quantum capacitance Cq due to graphene finite density of states(DOS), hence the global gate capacitance (per unit area) CG has to be de-scribed by the series connection between Cq and Cox [76].

The quantum capacitance modeling it’s the first obstacle that inducestroubles. Some models do not consider its presence [78, 86], while the pioneer-ing job proposed by I. Meric et al. [62] considers Cq as a parameter. Thiele etal. [76] explained how the quantum-capacitance voltage dependence is impor-tant for an accurate modeling of GFETs and proposed a linear dependenceon the channel-voltage which implies a bit of accuracy-loss around Dirac.Based on Thiele’s work a very compact-model was implemented by Jimenezet al. [87] and by Fregonese et al. [79], but a big distortion around the CNPmakes the latter not suitable for large-signals as well as its simplified versionthought for analog circuit-design reported by S. Rodriguez et al. [82]. Moreaccurate Cq modeling has been proposed by G. Landauer et al. [84] and byK. Parrish [81], but the first one is based on iterative equations which are not-welcome in compact-modeling, while the second one does not take account of

19


Figure 3.2: GFET equivalent circuit [79].

the saturation velocity charge-dependence as well as does Jimenez et al. [77].Generally vsat is linearly dependnt on the channel-charge [76, 62, 87, 79, 82],while other solutions have been reported in [88, 84].Furthermore a drift-diffusion model based on explicit distributions of chem-ical potential in graphene channels have been reported by Zebrev et al. [89]and a model which takes account of the Klein tunneling has been presentedby Fregonese et al. [63].

In this section the model proposed by Thiele [76] is discussed as well asits compact-model implementation proposed by Fregonese [79].

3.1.1 Thiele’s model

The drain current ID of a field-effect-transistor modeled assuming a driftcarrier transport can be expressed as:

ID = −qρsh(x)v(x)W = −qρsh[V (x)]v[V (x)]W (3.1)

where q is the elementary charge, ρsh is the free carrier sheet density per unitlength, v(x) is the carrier drift velocity per unit length and W is the gatewidth. On the right-hand-side of Eq. 3.1 the ρsh and the v channel-positiondependence is changed to a channel-voltage dependence.

To compute the total net mobile sheet charge density Qsh the equivalentcircuit depicted in Figure 3.2 is taken as a reference. As reported by T. Fang

20


et al. [90] the quantum capacitance is defined as Qsh derivative respect tothe channel voltage Vch:

Cq =dQsh

dVch(3.2)

which result is:

Cq =2q2kBT

π(~vF )2ln

[2

(1 + cosh

qVchkBT

)], (3.3)

where kB is the Boltzmann constant, ~ is the reduced Plank constant, vF isthe Fermi velocity and T is the temperature. Under the condition q Vch KBT

the previous becomes:

Cq =2q3|Vch|π(~vF )2

(3.4)

which is a closed-form relation. Notice that for low Vch values the quantumcapacitance is under-estimated, especially for Vch = 0, but this is the cost topay in order to have a first-order analytical form. Combining Eqs. 3.2 and 3.3:

Qsh =

∫CqdVch =

1

2CqVch (3.5)

that is not equal to CqVch as a common plate capacitor due to the Cq voltagedependence.The drift velocity comes out fromMonte Carlo simulations, which have shownhow the steady-state velocity-electric field relationship is well-approximatedby the expression:

v =µε

1 +µ|ε|vsat

. (3.6)

where µ is the mobility, vsat is the carrier saturation velocity and ε is theelectric field.

21


Therefore two different current saturation mechanisms occurs in GFETs. Thefirst mechanism explained in Subsection 2.3 is related to ambipolar conduc-tion, while the second occurs when a big electric field ε causes carrier velocitysaturation. As assumed for the mobility, also vsat is supposed to be the samefor both electrons and holes, but its nature is strongly related to carrier-phonon coupling, making it charge dependent. A first relation was proposedby J.H. Chen et al. [91]

vsat =ω

√πρsh

, (3.7)

then I. Meric et al [92] suggested that this modeling overestimate vsat andadded an empirical term to correct it. Finally Thiele proposed the followingrelation:

vsat =ω

(πρsh)0.5+AV (x)2, (3.8)

where ~ω is the surface phonon energy of the substrate and A is and empir-ical factor of the order of 10−3. Note that J.H. Chen’s and I. Meric’s studieswhere based on a GFET structure using a SiO2 substrate. Now, applyingthe well-known relation:

ε = −dV (x)

dx(3.9)

to the Eqs. 3.6, 3.8 and 3.1, we get the drain current:

ID = −qWρshµ(−dV (x)/dx)

1 +µ| − dV (x)/dx|

vsat

(3.10)

which solved by using variables separation, integrating over x from x = 0 tox = L and over Vch(x) from Vch(0) = 0 to Vch(L) = VDS, gives:

22


ID = qµW

∫ VDS

0ρshdV

L+ µ|∫ VDS

0

1

vsatdV |

. (3.11)

3.1.2 Fregonese’s model - GFET9

A compact model, based on Thiele’s job, was developed by Fregonese etal. [79]. Considering the equivalent circuit depicted in Figure 3.2, the totalcharge density in the channel can be written as:

qρsh = Qsh = CTOP [VGS − V (x)− VCH(x)] (3.12)

where CTOP is the gate insulator capacitance, V (x) models the voltage dropin the channel using the gradual-channel-approximation (GCA) and VCH isthe channel potential along x. Eq. 3.12 has to be equal to Eq. 3.5, where alittle correction due to an hypothetical doping is applied:

Qsh = β|VCH(x)|VCH − eNf . (3.13)

Here β = e3/π(~vf )2 and Nf represents the total intentional/unintentionaldoping contribution which is responsible of shifting the Dirac point. Com-bining Eqs. 3.12 and 3.13 a second order linear equation in VCH comes out:

β|VCH(x)|VCH + CTOPVCH(x)− eNf − CTOP [V (x)− VGS] = 0. (3.14)

Therefore:

VCH = s−CTOP +

√C2TOP + 4B|CTOP [VGS − V (x)] + eNf |

2B(3.15)

23


with s = sign(CTOP (VGS − V (x)) + eNf). Note that out of the two solutionthe previous is the only one that respects the hypothesis VCH > 0. Thisresult does not mean that VCH is always positive, but that its sign dependson the bias imposed by VGS and V (x). Merging Eqs. 3.14 and 3.15, the netbias dependent carrier charge Qnet = QSH − eNf could be written as:

Qnet(x) = βs

[−CTOP +


2B

]2.

(3.16)

The Qnet analytical form is a key factor in oder to model the drain currentand the saturation velocity. A new variable npuddle takes account of the resid-ual carrier density due to the spatial inhomogeneity in the graphene sheet.This allows a really good modeling around Dirac and avoids the saturationvelocity divergence due to the absence of carrier when VGS = V (x). From [93]npuddle = ∆2/π(~vf )2 where ∆ is a fitted parameter which takes account ofthe spatial inhomogeneity of the electrostatic potential. Due to this change,Eq. 3.11 becomes:

ID = µW

∫ VDS

0(|Qnet|+ enpuddle)dV

L+ µ

∣∣∣∣∫ VDS

0

1

vsatdV

∣∣∣∣ . (3.17)

which is written in a more compact form as:

ID = µWNUM

DEN, (3.18)

where NUM =∫ VDS

0(|Qnet|+ enpuddle)dV and DEN=L+ µ|

∫ VDS

0

1

vsatdV |.

The numerator is then defined as:

NUM = NUM1 +NUM2 =

∫ VDS

0

|Qnet|dV + enpuddleVDS (3.19)

24


therefore a closed form for NUM1 is required. Combining now Eqs. 3.19 and3.16:

NUM1 = β

∫ VDS

0

[−CTOP +


2B

]2dV.

(3.20)

By introducing the change in variable z = CTOP [VGS − V (x)] + eNf , theprevious has the following analytical solution depending on the sign of z:

NUM1(z>0) = − 1

β2CTOP

[CTOP

4

32−CTOP (CTOP

2 + 4βz)3/2

12+β2z2

2+βCTOP

2z

2

]z2z1

(3.21)

NUM1(z<0) = − 1

β2CTOP

[−CTOP

4

32−CTOP (CTOP

2 − 4βz)3/2

12−β

2z2

2+βCTOP

2z

2

]z2z1

(3.22)

where z1 = CTOP (VGS + eNf ) and z2 = CTOP (VGS − VDS + eNf ) [79, 82].Following the divide et impera process, also the denominator is split in:

DEN = L+ |DEN2| = L+

∣∣∣∣∣∫ VDS

0

µ

vsatdV

∣∣∣∣∣ (3.23)

and a symbolic solution is needed for DEN2. vsat depends on Qnet henceon V and in Fregonese’s job an average value for the saturation velocity isassumed in order to simplify the integral solution. Hence an average channelvoltage of VDS/2 is considered, which leads:

Qnet−AV = βs

[−CTOP +

√C2TOP + 4B|CTOP [VGS − VDS/2] + eNf |

2B

]2.

(3.24)

25


Merging the Eqs. 3.7 and 3.24 and applying the npuddle correction:

vsat−AV =ω√

π|QnetAV

|q

+ npuddle

(3.25)

therefore:

DEN2 = µ

√π|QnetAV

|q

+ npuddle

ω|VDS|. (3.26)

In Subsection 3.1.4 a Verilog-A version developed by S. Rodriguez et al. [82],called GFET9, is used to characterize a GFET at the device level.

3.1.3 Extrinsic resistances modeling

As explained in Subsection 2.3 source/drain metal contacts induce some per-formance degradations due to:

• the metal-graphene junction;

• the graphene-undearneath-metal and the graphene in channel regionheterojunction.

Out of those, in this thesis-job just the first one is model as a non-desiredchannel width W dependent contact resistance Rc. The second junctionmodeling is not considered due to its high complexity that involves Kleintunneling phenomenas which, nowadays, is still under investigation. More-over, if the gate and drain/source are not properly aligned as illustrated inFigure 3.3, an access resistance Ra is considered in order to model the chan-nel part not covered by the top-gate. Therefore:

Rd−s =Rc[Ωµm]

W [µm]+Ra[Ω]. (3.27)

26


Figure 3.3: GFET device symbol with extrinsic resistances included. [38],modified.

3.1.4 GFET9 - Characterization and comparison to mea-

surements

The compact model proposed by Fregonese has been implemented in Verilog-A language and has been validated by fitting it with different technologiesDC measurements [79, 82]. Out of the fitted technologies we have chosenthe one presented by I. Meric et al. [60] since the three channel lengths mea-surements can validate the model scalability. Figure 3.4 shows how a reallygood matching was achieved between the experimental results presented byMeric (see Figure 3.5) and the compact-model (with its parameters shownin Table 3.1).

Although there is really a good agreement between simulations and ex-perimental results, a non-desired artefact has emerged for some VGS-VDScombinations. As shown in Figure 3.6, this artefact introduces a strong dis-tortion both on the characteristic IDS vs VGS and IDS vs VDS, making theGFET9 not useful for large-signal modeling. The model is well matched withthe experimental results just because the distortion magnitude is not so high

27


(a) Lg = 440nm

(b) Lg = 1µm

(c) Lg = 3µm

Figure 3.4: IDS vs VDS for different VGS values - Cadence simulations.

28


Figure 3.5: DC measurements from [60].29


Parameter Physical/extracted value in [60] Compact model value

L[µm] 0.4, 1, 3 0.4, 1, 3W [µm] 1 1Tox[nm] 8.5 8.5εr 3 to 4(h−BN) 3.5µ[cm2/V s] 8.5k for e-, 10k for h+ 7kNf [cm

−2] Dirac point close to 0V 0Rs,Rd[Ω] built-in 172~ω[meV ] 40 56npuddle[cm

−2] 2.21011[cm−2] 3.21011 induced by ∆∆[meV ] not physical parameter 66.8

Table 3.1: Physical vs Compact model parameters fitted with Meric technol-ogy [79, 60].

in the considered range. In the following subsections two new proposals willovercome this issue.

3.2 Our new DC odel proposals

3.2.1 First model proposal: GFET 13

A first look to Figure 3.6 shows how the artefact magnitude strongly de-pends on VDS values. The bigger the VDS, the worse is the artefact. Furtherinvestigations have shown how the artefact effect is strictly related to thedenominator calculation, especially for short gate lengths. Therefore thequestion is: should we find a closed form for the integral dubbed DEN2?The following resolution try to look for an answer. The integral to solve is:

DEN2 =µ

ω

√π

e

∫ VDS

0

√|Qnet|+ enpuddledV (3.28)

where:

30


(a) Distortion in the IDS(VDS) characteristic for different VGS values - Lg = 440nm

(b) Distortion in the IDS(VGS) characteristic for different VDS values - Lg = 440nm

Figure 3.6: GFET9 - Distortion details.

31


|Qnet|+ npuddle =

=1

4β

[CTOP

2 − 2CTOP

√CTOP

2 + 4β|CTOP [VGS − V (x)] + eNf |+

+ C2TOP + 4β|CTOP [VGS − V (x)] + eNf |+ 4βnpuddle

].

(3.29)

Making a change in variable: y =√CTOP

2 + 4β|z|, reminding that z =

CTOP [VGS − V (x)] + eNf , the previous could be reduced as:

|Qnet|+ npuddle =1

4β(y2 + by + c) (3.30)

where b = 2CTOP and c = CTOP2+4βenpuddle. The change in variable implies

a change into the differentiator:

dV = −s y

2βCTOPdy (3.31)

where s = sign(z) and the integral extremes are:

y(0) =√CTOP

2 + 4β|CTOPVGS + eNf | =√CTOP

2 + 4β|z1| = y1 (3.32)

and

y(VDS) =√CTOP

2 + 4β|CTOP [VGS − VDS] + eNf |

=

√CTOP

2 + 4β|z2| = y2.(3.33)

Hence, the new integral to solve is:

DEN2 = −s µ

4ωβ3/2CTOP

√π

e

∫ y2

y1

x√y2 + by + cdy (3.34)

32


which closed form solution is:

DEN2 = −s µ

192ωβ3/2CTOP

√π

e

[2√y2 − by + c(−3b2 − 2by + 8(c+ y2))+

− 3(b3 − 4bc) ln(−b+ 2y + 2√y2 − by + c)

]y2y1.

(3.35)

A GFET-13 Verilog-A version has been implemented and the code wascarefully debugged trough several simulations both at transistor and circuitslevel proving it robustness for different transistor and circuit parameters.Figure 3.7 shows how the artefact distortion is completely eliminated.

3.2.2 Understanding the artefact nature in GFET9

The introduction of the function s = sign(z) explains how DEN2 is modeledin a sort of two-pieces regions. In graphene we could distinguish an ambipo-lar conduction and a mono-polar (p or n type) one. If we consider the GFETin ambipolar conduction, which occurs if 0 < VGS < VDS, there will be apoint x where V (x) implies a negative VCH , hence the equation 3.15 couldbe rewritten as:

VCH = −−CTOP +

√C2TOP + 4β[CTOP [V (x)− VGS] + eNf |

2B. (3.36)

A negative VCH has a direct effect when V is changed in y, because the differ-entiator sign change depending on the x position in the channel. In Figure 3.8y1 and y2 curves depending on VGS are plotted. If the sign function of Eq. 3.31is not considered, when the extremes of the integral have the same value theEq. 3.35 gives DEN2 = DEN2(y2) − DEN2(y1) = 0, while taking accountof the sign function, the previous becomes DEN2 = DEN2(y2) +DEN2(y1)

therefore the denominator under-estimation around Dirac is solved.Moreover the current-peak around Dirac in Figure 3.8 is similar to the

distortion seen in the GFET9 and the similarity could be explained by a

33


(a) GFET13 IDS − VDS characteristic for different VGS values - Lg = 440nm

(b) GFET13 IDS − VGS characteristic for different VDS values - Lg = 440nm

Figure 3.7: GFET13 IDS − VDS and IDS − VGS characteristics.

34


Figure 3.8: y1, y2 integral extremes curves and IDS-VGScharacteristic - Ca-dence simulations.

wrong application of the mean value theorem. When the Qnet−AV is appliedto the integral in Eq. 3.23 the inside incorporate information about the signis lost and this lack causes the artefact. In Figure 3.8 is evident how the bad-modeled zone is enclosed between 0V and VDS, which explains the artefactVDS dependence. Of course the artefact is less influent as longer is the channeland this explain why the 3µm channel DC simulations are not distorted asthe simulations with L = 440nm.

3.2.3 Second model proposal: GFET12

As understood from the previous subsection, the integral in Eq. 3.28, requiresa detailed modeling around the Dirac point. Some others models proposedin literature use a fixed vsat value in order to simplify the algebra, so makingthe compact modeling easier and faster [77, 81] . This approximation isacceptable for those channel length of the order of some µm, but it startsto be less accurate for shorter channels. The GFET13 solution, proposed

35


some a moment ago, provides an accurate modeling around the CNP, buta two-regions modeling is always delicate because the switching point couldcause some discontinuities in SPICE-like simulators.

For this reason another model was developed neglecting the quantum ca-pacitance effect on the carrier saturation velocity. This approximation mayseem rough, but offers a good trade-off between simplicity and accuracy.Therefore, assumed Cq as a short-circuit in Figure 3.2, we could write:

QSH = CTOP |VGS − V (x)|+ eNf (3.37)

which implies:

|Qnet| = CTOP |VGS − V (x)|. (3.38)

Hence the Eq. 3.28 is simplified in:

DEN2 =µ

ω

√π

e

∫ VDS

0

√CTOP |VGS − V (x)|+ enpuddledV (3.39)

which has the form of∫ √

ay + bdy and its closed solution is:

DEN2 =2µ

3ω

√π

e[VGS

√CTOP |VGS|+ enpuddle+

−(VGS − VDS)√CTOP |VGS − VDS|+ enpuddle].

(3.40)

Simulation results show how GFET12 curves are well matched with theGFET13 curves. Figure 3.9 shows how close the characteristics are.

3.3 State-of-the-art of GFET AC-models

The key physical quantity in a modeling process is the total charge insidethe channel QCH . A GFET large-signal compact-model usable for transient

36


(a) GFET13 (green) and GFET12 (red) IDS(VGS) characteristics forVDS = 3 and VDS = 5.

(b) GFET13 (green) and GFET12 (red) IDS(VDS) characteristics forVGS = −2 and VGS = −1.

Figure 3.9: GFET13 vs GFET12 characteristics comparison.

simulations requires the QCH evaluations in order to derive the dynamic in-trinsic parameters, as transconductances and capacitances.The capacitance approach could follow the Meyer model [94] which is non-charge conservative, but it offers a good trade-off between simplicity andaccuracy in circuit simulations. Unfortunately in some particular cases (i.e.dynamic RAM and switching capacitor circuits) the Meyer’s models fails, butthanks to some corrections assembled by D. Ward and R. Dutton [95] thecharge-conservation issue was solved at the cost of introducing a capacitive-matrix which adds a bit of complexity. Note that both Meyer and Ward-

37


Dutton modeling approaches assume the so called quasi-static-operation ap-proximation, where the charge per unit area at any time t is considered iden-tical to the charge calculated as if a DC voltage was applied at the same time.In other words, if vg(t), vd(t) and vs(t) are the varying terminal voltages, thecharge calculation will consider: VG = vg(t), VD = vd(t) and VS = vs(t).Practically the fluctuation of the varying terminal voltages is assumed tobe slow, so the stored charge could follow the voltages variations. This ap-proximation works really well in many MOSFETs circuits, but it sometimefails, especially with long channel devices operating at high switching speeds,when the load capacitance is very small and for digital circuits.

The theories previously described are developed for MOSFETs, but theconcept of channel charge and its relations with space, voltage and capac-itances are conceptually applicable for any type of MOS structure includ-ing GFETs. The reader could find more details about MOSFETs modelingin [96, 97, 98, 99].

In GFETs literature some models are based on the Meyer’s approachthanks to its simplicity [76, 79, 63, 82], while other jobs develop directlythe Ward-Dutton modeling [77, 72]. The big challenge in graphene dynamicmodeling is related to the calculation of the intrinsic capacitances, becauseat the time of this writing there is no reliable data. In this thesis job, thanksto the collaboration with KTH Royal Institute of Technology, we tried toextract and de-embed some capacitance values from measurements, but therepeatability was low due to biasing issues and to huge contact resistanceswhich also needs to be de-embedded.

Summing up, if the DC measurement could be considered as "the truth"for a DC modeling, there are no measurements or numerical simulationsreferences yet to contrast compact AC-model results.

38


Figure 3.10: GFET small-signal equivalent circuit [76].

3.3.1 Thiele capacitances modeling

The three-port electrical equivalent circuit proposed by Thiele et al. [76] isillustrated in Figure 3.10. Of course the equivalent circuit considers mainlythe intrinsic parameters (transconductances and intrinsic capacitors), whileextrinsic parameters are added in a second-step due to theirs layout depen-dence as done for RS and RD (see Subsection 3.1.3).

The transconductance and the ouput conductance are simply defined as:

gm =dIDSdVGS

∣∣∣∣∣VDS=const.

, gds =1

rds=dIDSdVDS

∣∣∣∣∣VGS=const.

, (3.41)

while the capacitances follow the Meyer modeling:

Cgs = −dQCH

dVGS


, Cgd = −dQCH

dVDS


. (3.42)

The overall net channel charge is computed as:

Qch = qW

∫ L

0

[p(x)− n(x)]dx = −W∫ L

0

(Qnet(x) + enpuddle)dx (3.43)

then the x dependence changes to the V (x) dependence. Note that the ab-solute value of Qnet used in the drain current equation 3.18 is not present

39


Figure 3.11: Cgs(VGS) curve based on Thiele’s modeling.

here, thus the integration overall the channel could be positive, negative ornil. The voltage-dependent-charge calculation proposed by Thiele is:

Qch = −W∫ VDS

0

(Qnet(x) + enpuddle)

(QshµW

IDS+

µ

vsat

)dV. (3.44)

A MATLAB code was developed in order to describe Thiele’s modeling anda capacitance overestimation came out. To understand why, we refer ourstudy to the Meric technology, which parameters are listed in Table 3.1 withLg = 440nm and VDS = 3V . The Cgs simulation result is shown in Fig-ure 3.11.

To verify the result trustworthiness we need to have an idea of the Cgs val-ues, but the equivalent circuit depicted in Figure 3.2 is a non linear networkwhich also depends on the channel position, while Cgs is a lumped parameter.However, roughly considering CGS as the series CG+CQ, if CQ >> CG it hasto be CGS = CG, where CG = CTOPWL. Therefore:

40


CG = ε0εrWL

tox= 1.6fF (3.45)

which leads at the conclusion that the values got in Figure 3.11 are out ofrange, hence something dubious has to be clarified. The Verilog-A modelGFET9 used in the DC section is based on Thiele’s dynamic considerations.

3.3.2 Fregonese capacitances modeling

Fregonese et al. [63] roughly assumes an average electric field within thechannel, which leads to:

dx

dV=

L

VDS. (3.46)

Merging the previous with Equation 3.43, the overall charge inside the chan-nel is given by:

Qch == −W L

VDS

∫ VDS

0

(Qnet(x) + enpuddle)dV. (3.47)

A MATLAB code was developed in order to simulate CGS and CGD shapes,which are shown in Figure 3.12.

As could be seen, under this approximation, CGS shows a minimumaround VDS/2, which is similar to the shapes preseted by Champlain etal. [100] and Zebrev et al. [101]. On the other hand Jimenez et al. [77]and Rakheja [72] predict a maximum instead of a minimum value. Hencethe question is: how could we explain that difference? First in Fregonese’sapproximation the saturation velocity effect is not considered and second theaverage approximation implies a whole unipolar channel which is not alwaystrue, especially when the channel work under the ambipolar regime. Onceagain some issues come out when the channel is populated by both electronsand holes, therefore further investigations are needed in order to clarify the

41


(a) (b)

Figure 3.12: CGS(VGS) and CGD(VDS) curves based on Fregonese’s modeling.

dynamic model under these conditions.

3.4 New AC-model proposals

3.4.1 First AC-model proposal: GFET13

Working on the solid base proposed by Thiele, a little, but meaningful, changewas applied to Equation 3.44:

Qch = −W∫ VDS

0

(Qnet(x) + enpuddle)

(QshµW

IDS− µ

vsat.

)dV (3.48)

where the minus sign instead of the plus came out from Equation 3.7. More-over the Meyer’s capacitance are computed as:

Cgs = −dQCH

dVGS


, Cgd = +dQCH

dVDS


. (3.49)

New CGS shapes are shown in Figures 3.13 and 3.14, where the asymptoticvalue is less than 1.6fF as supposed in Equation 3.45, but a capacitance peak

42


Figure 3.13: GFET13 - CGS(VGS) curve for L = 440nm,W = 1µm, VDS =0.5V .

around VDS/2 is present. This peak does not respect the argument aboutthe capacitances series, but we have to remind that i) the equivalent circuitin Figure 3.2 is non-linear, ii) when the channel is in the ambipolar regimesome classic rules could not be applicable. On the other hand the capacitancepeak is explainable by its charge-derivative definition. Figure 3.14a) showshow QCH changes its sign around VDS/2 wich is a direct consequence of theambipolar conduction.

To understand that, we consider that VDS is fixed and VGS sweeps from0 to VDS, therefore the whole channel is p-doped, pinched-off at the sourceand the overall charge is positive. By increasing VGS the pinch-off positionmoves toward the drain, hence the channel becomes less positive and theoverall charge decrease with VGS. This explains the minus presence in theCgs definition. A nil QCH value is obtained when the channel is pinched-off

43


(a) (b)

Figure 3.14: GFET13 -QCH(VGS) and CGS(VGS) curves for L = 440nm,W =1µmVDS = 3V .

at the middle point L/2 and further increases of VGS leads a negative to-tal channel charge. Of course two asymptotic values will limit the integraldue to source and drain fixed potentials. The described curves are shown inFigure 3.14a). Similar Cgs shapes are presented in Jimenez model [77] andRakheja [72], while other studies predict a minimum capacitance value whenthe Dirac point occur at the middle of the channel [75, 100, 82, 101] as shownin Figure 3.12a), remaining the question still open.

Although we could consider acceptable the Cgs-VGS characteristic, someproblems come out when the Cgd-VDS is plotted as shown in Figure 3.15d).Due to the non-monotonic behavior of QCH(VDS) [Figure 3.15b)], Cgd as-sumes both values positive and negative, therefore some troubles have to beunderstood and solved. We observe that the channel charge starts to bemonotonically for values of the channel, more or less above 8µm and an ac-ceptable shape is proposed in Figure 3.15a). The QCH positive slope respectto VDS explains the plus sign in the Cgd definition. Moreover a numericalmatch occurs between Cgs and Cgd values which are of the order of some tensof fF at the same gate length L = 10µm as shown in Figures 3.15 c) f).

For the above-mentioned reasons the GFET13 AC modeling could be

44


(a) (b)

(c) (d)

(e) (f)

Figure 3.15: GFET13 QCH(VGS), CGS(VGS), QCH(VDS), CGD(VDS) curves.

45


(a) (b)

Figure 3.16: L vs DEN2 comparison.

considered acceptable only for gate-lengths greater than a fixed one, whichdepends on the parameters, hence on the technology. It could appear as along channel modeling, but the current computed in Equation 3.18 and thenused in Equation 3.48 is affected by the carrier saturation velocity effect,which is more dominant for shorterer channels. For a quantitative analysiswe could remind Equation 3.23, which is non linear due to the vsat charge-dependence. As soon as L > DEN2 the charge modeling is acceptable,while for low values some troubles happen. A comparison between L andDEN2 is shown in Figure 3.16 for L = 10µm and L = 1µm. The conclusionof this argument requires further investigation on the space(x)-voltage(V )

relationship which is the origin of the dynamic drawbacks.

3.4.2 Second AC-model proposal: GFET15

The main drawbacks illustrated so far are related to un unclear charge be-haviors in the ambipolar regime and un unclear perception due to the carriersaturation velocity when the channel becomes shorter. In this subsection anew proposal is based on the simple drift modeling where the vsat effect isneglected both in the current computation and in the charge computation.

The GFET15 assumes the same DC modeling developed for the GFET13,

46


while the charge computation is not referred to the effective IDS but to thecurrent that will flow into the device if the carriers are non-velocity-saturated(NVS). As the Fregonese’s approximation, this assumption does not have arigorous physical sense, but its results are acceptable both in shapes and invalues. Hence:

dx

dV=

µWQsh

IDS−NV S(3.50)

where:

IDS−NV S = µW

L

∫ VDS

0

(|Qnet|+ enpuddle)dV. (3.51)

One more time a MATLAB code was developed in order to run a numericalsimulation and some charge/capacitance curves are illustrated in Figure 3.17.

3.5 Our final compact-model proposal - GFET14

In the previous sections we have proposed two DC and two AC compact-models. At the end of this chapter we propose a complete compact-modelcombining the DC proposal in Subsection 3.2.1 and the Fregonese’s capac-itances modeling explained in Subsection 3.3.2. Moreover we take care ofsome extrinsic parameter as illustrated in Figure 3.18.

A Verilog-A code, called GFET14, of this model has been developed andit will be benchmarked with other models in the next chapter.

3.6 Chapter conclusions

Having considered some previous works in this chapter we have implementedan accurate, scalable and robust DC compact model, called GFET13, whichhas been validated by fitting it with some experimental results showing a

47


really good agreement between measurements and simulations. This modeljust takes care of the GFET intrinsic behavior and considers just the sourceand drain contact resistance as extrinsic fitting parameters. Furthermore astill accurate simplified version, called GFET12, has been implemented.

If the DC modeling could be considered well developed, the situation isnot so clear when a dynamic GFET behavior is considered. The main issuethat makes awkward the capacitance modeling is related to the absence of ex-perimental measurements or physical simulations which could give a referenceas is a IDS-VDS characteristic for the DC modeling. Hence the capacitance

(a) (b)

(c) (d)

Figure 3.17: GFET15 QCH(VGS), CGS(VGS), QCH(VDS), CGD(VDS) curves.

48


Figure 3.18: A GFET symbol and a hybrid-π model for large-signal analysis.

modeling is mainly based under some physical assumptions and predictiveideas. In this chapter two kind of charge/capacitive modeling proposed byother people have been analyzed and two new ideas have been proposed.

Finally a Verilog-A complete (DC+AC) compact-model which takes careof some extrinsic parameters (GFET14) has been presented and it will bebenchmarked in the next chapter.

In order to find some experimental answer our approach is based on thebottom-up top-down correlation. In other words, a charge modeling is pro-posed under some physical assumptions and a ring oscillator circuit simu-lation is run to predict some performance metrics which are strictly relatedto the intrinsic modeling. A second step requires a circuit characterization,which has to extract and de-embeds the intrinsic parameters in order to verifythe hypothesis done in the modeling process. Unfortunately to accomplishthis approach a strong collaboration between modeling and technology is re-quired, hence the simulations proposed in the next chapter will be consideredjust as predictions.

49

Chapter 4

GFETs circuits characterization

A Test-Bench for Large-Signal Compact-Models

The research area on graphene FETs circuit design is really at the embry-onic state due to the immaturity of both graphene technology and scientificcommunity which has discovered the wonder material of the 21st centuryjust 10 years ago. In order to push the ongoing research on graphene, themain contribution has to come from the technology, but it requires time asconfirmed by Sir Alex Geim which, during an interview, said: "It’s a bit sillyfor society to throw a little bit of money at something and expect it to changethe world. Everything takes time."

Despite the technology is not so mature some really basic circuits with fewtransistors are presented in literature. The first GFET IC was introduced onJune 2011 by Lin et al. [30], where a single GFET on SiC substrate operatesas a broadband radio-frequency mixer at frequencies up to 10GHz. Thenother works have been developed and we could classify them in four groups:amplifiers [102, 103, 104, 105, 106], multipliers&mixers [107, 108, 109, 110,111, 112, 113, 114, 115], sources&detectors [116, 117, 118, 119] and oscilla-tors [120, 121], which find their application in the RF field and hopefullycould pave the way to TeraHertz Electronics. Current technologies couldreach several hundreds of GHz under experimental conditions, but the THz

50

CHAPTER 4. GFETS CIRCUITS CHARACTERIZATION

target is distant at the moment, hence graphene comes into play in orderto achieve the not allocated band from 300 GHz to 3THz. Many servicescan operate above 300GHz as THz communications and earth explorationsatellite systems, which require a mass-production process hence cheap elec-tronics [122, 123, 124].

The GFETs state-of-the-art reminds the situation of RF Si-MOSFETs inthe late 90s, when they showed-off competitive fT but poor fmax. At thattime Si-MOSFETs were afflicted by high gate resistance which was the mainreason of fmax low values, but in GFETs the situation is more complex andprobably hidden in the intrinsic current saturation combined with too highdrain-source resistances, which deteriorate their power gain and fmax [34].

In this chapter a DC cascode and a ring oscillator based on complementary-inverters are simulated using the GFET14 model proposed in the previouschapter. To validate our model assumptions other two different models areused: the first implemented by Landauer&Jimenez et al. [84] based on drift-diffusion transport and the second implemented by IBM and MIT people etal. [72] based on virtual-source transport.

4.1 Large signal compact-models comparison

In Subsection 3.5 we have developed a compact-model based on the drift-diffusion carrier transport, then we have fitted it with the technology pro-posed by I. Meric et al. [60](Meric technology) verifying its scalability withL. Its parameter are listed in Table 4.1.

IBM+MIT virtual-source model Rakjeja et al. [72] has reported aGFET compact-model Verilog-A implementation and has shared it on nanoHUBfor free access to the community. This model is based on the virtual-sourceconcept developed for nano-MOSFET and then adapted to graphene FETs.Its parameters have been fitted with Meric technology and are summed up

51


Parameter Description Value

L[µm] channel length 0.4,W [µm] channel width 1Tox[nm] gate-oxide thickness 8.5εr gate-oxide relative permittivity 3.5µ[cm2/V s] mobility 7kNf [cm

−2] Net doping 0Rc[Ωµ] metal-graphene contact-resistivity 172Ra[Ω] channel access resistance 0~ω[meV ] surface phonon energy of the substrate 56∆[meV ] spatial inhomogeneity of the electrostatic potential 66.8

Table 4.1: GFET14 model parameters fitted with Meric technology [79, 60].

in Table 4.2.

A device-level comparison between the two model fitted to the same tech-nology is performed and the results are shown in Figure 4.1a) . As we couldsee there is a good matching between the two models and the experimentalresults especially for those VGS values quite far from the Dirac point. Thetwo models differ a bit around the CNP, where the virtual-source model as-sumes a flat characteristic, which implies a tranconductance gm distortion.The GFET14 model results more accurate and fits better the experimentalcurve.

Furthermore the gate capacitance is plotted for both models and theresults are illustrated in Figure 4.1b). Here two main differences are present:

• the drift-diffusion model exhibits a clear minimum at the Dirac pointwhich widens with VDS, while the virtual-source shows a maximumin the same point which widens with VDS. This difference could beexplained by the approximations used in order to compute the wholechannel charge, hence CGS and CGD in the drift-diffusion model. Theminimum/maximum controversial was yet described in Chapter 3 andthis comparison may help to identify the approximations validity.

52



L[µm] channel length 0.4W [µm] channel width 1Cg[nF/cm

2] top gate oxide capacitance 360C[pF/m] extrinsic parasitic capacitivity 100Qdis[nC/cm

2] disorder induced charge 500µ[cm2/V s] mobility 7kvxo[cm/s] virtual source injection velocity 7MRelec, Rhole[Ωµm] electrons/holes-branch resistance 172Rg[Ω top gate resistance 1.22Vmin,0[V ] Dirac-point voltage 0∆V [V ] Shift in Dirac voltage due to traps 0ζ Energy transfer factor 82.5 · 10−3

β saturation parameter 1.8α shift in threshold voltage 6n non ideality factor 2

Table 4.2: MIT+IBM (Rakheja) Compact model parameters fitted withMeric technology [72, 60].

• The asymptotic values achieved when the channel is totally p or ndiffers by a factor of 1.5 which could be explained as the charge over-estimation due to the drift-diffusion modeling as reported in [71, 125].Unfortunately, due to some technical issues in measuring GFET ca-pacitances, there are no experimental measurements in order to clarifywhich of the two modeling approach is more accurate.

Landauer&Jimenez drift-diffusion model A very accurate solution,based on a compact model presented by Jimenez et al. [77], has been pre-sented some months ago by Landauer et al. [84]. In his model proposal,Landauer considers a root-square approximation, instead of the classical lin-ear one, for the quantum capacitance and presents an alternative vsat two-regions description. Further information about Landauer’s models are avail-able in [126]. Unfortunately the L&J model does not consider GFETs dy-namic behavior, hence it is useful only for DC circuit. Once again, this model

53


(a) GFET IDS-VGS characteristics for selected VDS.

(b) GFET Cgg capacitances for selected VDS.

Figure 4.1: A device-level comparison between our GFET14 (solid lines) andRakheja (dashed lines) models fitted to Meric technology.

has been fitted with Meric technology and its parameters are listed in Ta-ble 4.3.

A device-level comparison between our GFET14 model and the L&Jmodel is performed. Figure 4.2a) illustrates both the IDS-VGS ambilpolarcharacteristics, where the Dirac-voltage increases with VDS in both cases.The curves are practically the same around Dirac, but a little difference isobserved for VGS values far from Dirac, where L-J model’s gm estimation

54



L[µm] channel length 0.4W [µm] channel width 1tox[nm] gate-oxide thickness 8.5k gate-oxide relative permittivity 3.5~Ω[meV ] surface phonon energy of the substrate 75µ[cm2/V s] mobility 7kRD,S[Ωµm] metal-graphene contact resistivity 172Vgs,0[V ] flat-band voltage top-gate 0∆V spatial inhomogeneity of the electrostatic potential 0

Table 4.3: L&J Compact model parameters fitted with Meric technology [84,60].

results lower than in our model.In Figure 4.2b) both the IDS-VDS characteristics are illustrated. The GFETsaturation voltage VSAT increase with VGS in both models, except for VGS = 0

where the channel is not pinched-off, hence not saturated. Due to the similarcharacteristics the output-conductance gds is essentially the same for bothmodels. The gm and gds mathematical definitions have been reported inEquation 3.41.

4.2 Characterization of GFET based

inverters

An inverter represents the basic structure of all digital designs. Once un-derstood its behavior the more complex structures design is simplified, butas already said, GFETs are not suitable for digital-design due to the lack ofan off-state. However the complementary inverter could be interpreted froman analog/RF design perspective, where the main performance metrics areidentified by a delay and a non-linear gain. Some GFET INVs have alreadybeen implemented with top-gate [127, 128, 129], back-gate [130] and side-gate [131].

55


(a) GFET IDS-VGS characteristics for selected VDS.

(b) GFET IDS-VDS characteristics for selected VGS.

Figure 4.2: A device-level comparison between our GFET14 (solid lines) andL&J (dashed lines) models fitted to Meric technology.

In Figure 4.3b) a two GFETs inverter is implemented remembering theclassic CMOS structure, but with an enormous device-difference which doesnot require different doped transistors. In fact, thanks to the ambipolar-characteristic, the two GFETs depicted in Figure 4.4a) are the same whichcould represent an amazing advantage thinking to a mass-production pro-cess.In this section a circuit-level comparison between our model and the one

56


Figure 4.3: A Ring Oscillator (a) based on 3 Complementary Inverters (b)implemented with 2GFETs.

presented by Rakheja is performed. The results will provide the guidelinesfor INVs design and at the same time will validate (or not) some model as-sumptions.

In Figure 4.4a) the VOUT -VIN characteristic is plotted for different supply-voltages VDD. As we could see, the VOUT transition from the high-voltageVDD to the low voltage VSS (and vice-versa) is sharpest in the drift-diffusionmodel, which implies high voltage gain. The softer transition that occurs inthe virtual-source model is probably due to the flat curve around Dirac, asdiscussed in the previous section.

Furthermore a transient-simulation is performed with an input signal from0V to VDD = 2.5V at fCLK = 5GHz. The transient-waveforms are plottedin Figure 4.4b), where the drift-diffusion model shows a small-discontinuity,hence the virtual-source models seems to describe a more realistic behavior.

57


(a) GFET INV output-voltage VOUT against input-voltage VIN for selected VDD

(b) GFET INV output-voltage VOUT and input-voltage VIN transient simulations

Figure 4.4: A circuit-level comparison between our GFET14 (solid lines)and Rakheja (dashed lines) models fitted to Meric technology. The circuitparameters used include a transistor aspect-ratio of (W

L)1,2 = 1µm

440nm.


Ring-Oscillator Circuits

GFET ring-oscillators (ROs) based on complementary-inverters(INVs) areconsidered the ideal circuits in order to characterize graphene process antransistors since they could be described quantitatively by two performancemetrics: the operating-frequency fOSC and the voltage dynamic-range VOSC .Moreover these two metrics are easily extractable from simple experimentalmeasurements, hence minimizing the cost of the RF equipment required for

58


an experimental test. Few GFET ROs based on top-gate devices have alreadybeen presented in [120, 121]. As done in previous section, the following sim-ulations will be useful for two purpose: i) provide guidelines for GFET ROscircuit design and ii) provide guidelines for GFET device compact-modelsrefinement and technology optimization.

(a) GFET ROs oscillation frequency fOSC(L) for se-lected tox

(b) GFET ROs voltage dynamic-range VOSC(L) for se-lected tox

Figure 4.5: A circuit-level comparison between our GFET14 (solid lines)and Rakheja (dashed lines) models fitted to Meric technology. The circuitparameters are (W

L)1,6 = 10 and VDD = 5V .

Generally a ring-oscillator consist of a chain of inverters connected in aloop which causes a proper oscillation if the Barkhausen’s criterion are ac-

59


complished. Its requires an odd number of INVs and we choose to minimizethem in order to minimize the overall transistors number.Figure 4.3 illustrates a GFET RO based on 3-INVs. General practice incircuit-design characterization, some performance-metrics and design-parametersare chosen. In this study the performance metrics are represented by fOSCand VOSC while the design-parameters chosen are the transistor channel-length L and the gate-oxide thickness tox. To perform a circuit-level com-parison between our model and the one presented by Rakheja, both fittedto Meric technology, the circuit parameters used are: (W

L)1−6 = 10 and

VDD = 5V . Moreover the channel length L is chosen to be greater than300nm in order to avoid some performance degradations due to tunnelingeffects [63].

Figure 4.5a) shows the operating-frequency fOSC calculated against l forselected tox. Generally tox is fixed by the process, but using it as a parameterdelivers more insight to technologists. As expected, for both models fOSCincreases while L decreases, especially when L < 500nm. Furthermore fOSCincreases while tox increases for the drift-diffusion model, but this trendsweakens for tox > 20nm. In the virtual-source models fOSC increases whiletox increases, but in this case the increments are smaller. However fOSCstarts to decrease when tox = 20nm.The dynamic voltage-range VOSC is plotted in Figure 4.5b) against L for se-lected tox. For both models VOSC increases while L decreases, while differentmodel behavior are detected by varying tox. In the virtual-source model,VOSC increases while tox decreases. In the drift-diffusion model VOSC alsoincreases while tox decreases, but the increments are smaller and VOSC startsto decrease when tox = 6.5nm.

Summing up, considering the drift-diffusion model, a thicker dielectricincreases fOSC but does not have a big impact on VOSC . On the other hand,considering the virtual-source model, thinning the dielectric does not changeseriously fOSC , but it increases VOSC .

60


Figure 4.6: A GFET cascode (a) and a GFET self-cascode (b) circuits im-plemented with 2 GFETs.


DC Cascodes

In this section a DC circuit-level characterization is performed in order toi) analyze the effect of GFETs low output-resistance on circuits such a cas-code; ii) verify the GFET14 compact-model approximation using more ac-curate models as the one proposed by Landauer and Jimenez. Of coursedue to the immature GFET-techonology, we do not expect the same behav-ior of a CMOS cascode, but a circuit-characterization is suitable in orderto give a feedback to the technologists, remarking our philosophy on thebottom-up&top-down interaction. At the moment, the lack of a bandgap inmonolayer-GFETs causes a low output resistance and this study verify itscircuit-level effect, while the technologists are trying to improve the GFEToutput-resistance at the device-level.

The main purpose of a cascode circuit is to decrease the output-conductancegds in order to de-couple the output-load and increase the intrinsic-gain for

61


the widest biasing range, where:

Av =gmgds

. (4.1)

A GFET cascode implementation is depicted in Figure 4.6a), where the gdsreduction is achieved through a proper GFET2 biasing. In Figure 4.7a) areshown some IOUT -VOUT characteristics for different input-voltages VIN , whichact as a comparison between the two models already cited. The circuit pa-rameters are W/L = 1µm/440nm and VBIAS = 2.5V . As we could see, thecharacteristics are very similar for both models and comparing them withthe IDS-VDS device-level characteristics [see Figure 4.2b)] a qualitative im-provement in current saturation is seen for low input-voltages VIN .

In Figure 4.6b) a self-cascode circuit is implemented with two GFETs.This time the output-conductance gds reduction is achieved through the op-timized size ratio (W/L)2. The circuit-level simulation is performed with thefollowing parameters: (W/L)1 = 1µm/440nm and (W/L)2 = 1.5µm/440nm.In Figure 4.7b) are plotted some IOUT -VOUT characteristics for the same VINvalues as before. A qualitative improvement in current saturation is achievefor high-input voltages VIN if we compare them with the characteristics inFigure 4.2b), while comparing them with the others in Figure 4.7a) also animprovement in current saturation is seen for high-input voltages VIN , but aworsening is seen for low input-voltages VIN . The discountinuity in the greencurve is probably due to convergence problems in the simulation.

4.5 Chapter conclusions

In this chapter we have validated the compact-model developed in the pre-vious chapter by comparing it with two other different model both at thedevice-level and at the circuit-level, taking as reference the technology devel-oped by Meric in [60].

62


The first device-level comparison against the virtual-source model (theVerilog-A is available on nanoHUB) , developed by Rakheja, has shown howour drift-diffusion model describes better the DC behavior, while some differ-

(a) GFET cascode output-current against output-voltage IOUT (VOUT )for selected VIN . The circuit parameters are (W/L)1,2 =1µm/440nm and VBIAS = 2.5V .

(b) GFET self-cascode output-current against output-voltageIOUT (VOUT ) for selected VIN .The circuit parameters are (W/L)1 =1µm/440nm and (W/L)2 = 1.5µm/440nm.

Figure 4.7: A circuit-level comparison between our GFET14 (solid lines) andL&J (dashed lines) models fitted to Meric technology.

63


ences appear when the dynamic behavior is considered by taking account ofthe gate-capacitance. Unfortunately due to the lack of charge/capacitancesmeasurements we cannot say which model describes properly the gate capac-itance.A second device-level comparison against another very accurate drift-diffusioncompact-model based on iterative solutions, developed by Landauer&Jimenez(the Verilog-A is available on IEEE), has validated our model assumptions,especially about Cq and vsat. Sadly L&J model does not consider a dynamicmodel.

Moreover basic circuits (inverters, ring oscillators and DC-cascodes) havebeen simulated in order to compare the models at circuit-level and to providedesign-guidelines.

64

Chapter 5

Final Conclusions

The "final product" of this thesis job is a GFET compact-model suitable forlarge-signal circuit-design implemented in a standard Verilog-A language.This model, called GFET14, is based on the drift-diffusion carriers transportconsidered in two already existing models. The assumption of this transporttype is not trivial due to the long graphene mean-free-path which requiresfurther investigations, however a good match has been observed betweensimulation results and experimental measurements. The exact analyticalcalculation of the current denominator ensures improved accuracy aroundthe Dirac point which has a direct effect on analog properties as transcon-ductance gm and output conductance gds.The GFET14 dynamic behavior considers an average electric field within thechannel which seems rough but leads interesting results. Due to the lack ofdata a comparison among few GFET AC models has been presented.

Our solution has been benchmarked both at device-level and at circuit-level against a virtual-source compact-model through transient-based sim-ulations. The results have shown how our compact-model fits better theexperimental DC-measurements, while the AC differences remain unverifieddue to the absence of experimental data and physical simulations.Once again the GFET14 has been benchmarked both at device-level and atcircuit-level against a more accurate DC-compact-model, through DC-based

65

CHAPTER 5. FINAL CONCLUSIONS

simulations. Similar results have been observed for both models.Moreover the circuit-level characterization has provided the guidelines forring-oscillators circuit-design.

Future works will encompass the noise modeling and the parameter fit-ting of the model to next generation GFET technologies. In particular thecontact-resistance modeling is something not really clear and requires fur-ther studies as well as the drift-diffusion/quasi-ballistic threshold, which hasto be investigated due to its direct effect on the modeling science. Thusan important contribution has to come from the technology to clarify somesecond-order effects especially when the channel length reach the sub-µmrange.

66

Appendix A

Relevant analog/RF transistorFOMs

In RF field several different figure-of-merits (FOMs) are used in order to char-acterize transistors. Out of those the most important are described as follows.

The small-signal analysis assumes a small perturbation around a certainoperating point in order to model the transistor non-linear characteristic asthe straight line tangent at the operating point. A typical MOS small-signalπ-equivalent-circuit is illustrated in Figure A.1. The first important FOM isrepresented by gm = dIDS

dVGSwhich models the output current variations caused

by changes in the gate-source voltage. Of course gm has to be as high aspossible in order to maximize amplification. On the other hand, the outputconductance gds = 1

rds= dIDS

dVDS, which describes the current variations due to

any change of VDS, should be immune to any change of VDS hence low ggs

values are required. The amplification-capability of a transistor, genericallycalled intrinsic gain depends both on gm and gds hence a more practical FOMis defined as: gint =

gmgds

.

The transistor dynamic behavior is characterized by two well-known FOMs:fT and fmax. The first, called transit frequency, is the frequency at whichthe current gain h21 of a small-signal common-source amplifier stage falls

67

APPENDIX A. RELEVANT ANALOG/RF TRANSISTOR FOMS

Figure A.1: A FET transistor small-signal equivalent circuit [34]. gm isthe transconductance, gds is the output conductance, Cgs is the gate-sourcecapacitance and Cgd is the gate-drain capacitance. RD , RG and RS areparasitic extrinsic resistances, while Ri is the intrinsic gate resistance.

into unity, while the second, called maximum oscillation frequency, is thefrequency at which the unilateral power gain equals one.The latter are defined as:

fT =gm

2π(Cgs + Cgd), (A.1)

fmax =gm

4πCgs

1√gdsRi

. (A.2)

Notice that only fmax depends on the output conductance. If some extrinsicparameters are considered, such as gate, source and drain resistances, bothfT and fmax become:

fT =gm

2π(Cgs + Cgd)

1

1 + gds(RS +RD) +Cgdgm(RS +RD)

Cgs + Cgd

, (A.3)

fmax =gm

4πCgs

1√gds(Ri +RS +RG) + gmRG

CGDCGS

. (A.4)

hence a performance-loss comes out.

68

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