power amplifier design

Power Amplifier Design

TriQuint MMIC Design Training

AWR Confidential

TriQuint MMIC PA Design – AWR Confidential2

Summary

• An Example of a 2.5 GHz Amplifier to Show:– Setting hotkeys and customizing the AWRDE– Creating and editing schematics and layouts– Using TriQuint DRC and LVS– Simulation and tuning– Optimization and using statistics– Nonlinear noise analysis and contributors– Routing iNets– Automated Circuit Extraction (ACE)– Axiem– System analysis


Slide Notation

• This class is a step by step tutorial on the AWR Design Environment.• Complete instructions are provided in the text and in the screen shots / pictures on

each slide• The graphic below is always shown on slides where there is interaction with the

Project, Elements, or Layout tabs of the AWR project manager. The correct tab for the required action is always selected indicating to the user where the items they are looking for are located.

2.5 GHz PA Amplifier Target Design


Target Design

• 3-D view of the target design

Loading Libraries (PDK’s)


Libraries - Installing

• Before using a PDK (Process Design Kit), it must be installed on your computer (this procedure is how all PDK’s in the AWRDE are installed)

• Browse to the installer file (TQOR_TQPEDi_1_1_2x_xx.msi) in the folder that was provided to the class and run the installer

• Accept all the default settings

Note: Your PDK version number will be different.


Libraries

• Start the AWRDE and read in a process definition by choosing File > New With Library > TQOR_TQPED• If you already had other versions installed, you can choose the specific version of the PDK you would like to use


Project Save

• Save your project using File > Save Project As• Choose any project name…


Project Frequencies

• Go to Options > Project Options• Click on the Frequencies tab• Enter “2.5” for the Start frequency and check the box next to Single Point• Click Apply before clicking OK

Setting Hotkeys


Hotkeys

• Add a couple of custom hot keys by choosing Tools > Hotkeys

Note: We can customize:

• Hotkeys

• Toolbars

• Menubars


Hotkeys - 2

• For Categories, choose Window and then select WindowTileHorizontal• Click in the “Press the new hotkeys” field and then press the “H” key• Leave Standard as the editor• Press the Assign button• Also assign the “V” key to “WindowTileVertical”• Also assign the “R” key to “EditRotateRight” (under Edit category)

Note: You can use the Shift, Ctrl, and Alt keys in addition to letters to make a hotkey.

Creating And Editing Schematics

(Unified Database / Editing Layouts)


New Circuit Schematics

• Go to the Project tab and make a new circuit schematic named “IV_Test” by right-clicking on Circuit Schematics and choosing New Schematic

Note: It is generally a good idea not to use spaces, esp. with artwork cells. Use the underscore “_” instead.


Layout View of Schematic

• Open the layout view of the schematic by clicking on the View Layout button

Tip: There is a Schematic and Layout view associated with every circuit schematic.

Note: There are several toolbar menus - RC in a blank spot of the toolbar browser area to see the choices.

Standard ToolbarSchematic Design Toolbar

Equations Toolbar


Clean Workspace

• Tile the schematic and layout views by using the new “H” hotkey (or select Window > Tile Horizontal)

Note: You can change the color of the layout background using a built-in script Scripts > Global Scripts > Examples > Toggle_Layout_Color


Element Placement

• Elements are found on the Elements tab• Element categories appear in the top of the pane, elements appear in the bottom• Elements are placed by dragging from the bottom pane to the schematic and then

letting go of the mouse – this pulls up a ghost image that can then be placed

Elements tab


Element View

• Like Windows Explorer, the element view can be changed by right-clicking in the lower pane of the “Elements” tab – Show Details is a common setting.

Tip: You can get help on any element by RC > Element Help.

Tip: The classification of the elements in the element browser is the same as in the Element catalog.


Element Placement

• Elements can also be placed using the Element button

• You can also use the built-in hotkey Ctrl + L• This will bring up the “Add Circuit Element” dialog

• With this dialog, you can find an element by typing in its name or searching by keyword in the description

Note: Use Ctrl + click on the column header to change the field on which you search


Element Rotation

• Prior to placement, elements can be rotated with the right mouse button

Tip: You can also flip the elements about their horizontal axes using:

• Horizontal axis - Shift + right mouse button.

• Vertical axis - Ctrl + right mouse button.


Element Categories

• Elements for this exercise can be found in the following categories:

Libraries > *TQOR TQPED > PHEMT >TOM3 > PHEMT_Instances > TQPED_EHSS_T3_Inst MeasDevice > IV > IVCURVE

• Ports, Grounds, and Subcircuitscan be found on the tool bar (Schematic Design Toolbar)

Tip: Hot Keys

• Port – Ctrl+P

• Ground – Ctrl+G

• Subcircuit – Ctrl+K


Swp Step

IVCURVEID=IV1VSWEEP_start=0 VVSWEEP_stop=8 VVSWEEP_step=1 VVSTEP_start=0 VVSTEP_stop=1 VVSTEP_step=0.1 V

1

2

3

TQPED_EHSS_T3iID=EHSSi1W=100NG=20TQPED_EHSS_T3_MB=EHSS_T3

Test Bench Assembly

• Assemble the schematic shown below

Note: The circled parameters are NOT using default values. Watch the schematic layout as you change the W and NG parameters.


Test Bench Assembly

Creating Graphs and Adding Measurements(Using Simulation)


Adding Graphs

• Add a new rectangular graph named “IV_Curves” by right-clicking on Graphs and choosing New Graph


Adding Measurements

• Add a new measurement to the graph by right-clicking on the graph and choosing Add Measurement

• Choose “Measurement Type” Nonlinear > Current and “Measurement” IVCurve and note that it points to IV_Test


Duplicating Measurement - Aplac

• Copying measurements is a quick way to add similar measurements to the same graph or other graphs

• You can copy a measurement by dragging an existing measurement onto the top of the graph icon

• This method of copying works with Schematics, Data Files, System Diagrams, Optimization Goals, Yield Goals, EM Structures, etc.


Duplicating Measurement - Aplac

• Once the Measurement copy is created, it can be edited by double-clicking on it

• Change one of the IVCurve measurements so that it uses the APLAC DC simulator and click OK


Simulation

• Press the lightening bolt (Analyze) button to see the results.

Using Tuning


Tune Setup

• Tune on the circuit by going back to the IV_Test schematic window and using the Tune Tool to select the W and NG parameters on the eHEMT.

• Once a parameter is selected for tuning it will turn blue

Use tune tool to select parametersfor tuning.

Equations Toolbar


Tuning

• Press the Tune button and use the sliders to vary W and NG and see the effect on the simulation results on the graph.

Note: The Aplac and standard HB results change simultaneously


Tuning

• Open the layout view of the “IV_Test” schematic• Also open a 3D layout view by clicking on the

View 3D Layout button

• Use your Tile Horizontal or Tile Vertical hotkeys to tile all four windows

• Now tune on W and NG to see all four windows update simultaneously

• Hold down the Ctrl key to see the layout views update real time


Tuning


Markers and Traces

• Makers can be added to graphs by right-clicking on the graph and choosing Add Marker

• The built-in hotkey for this is Ctrl+M• Add a marker at 4V VDS and 240 mA IDS• You can search for a specific point on a graph by right-clicking on the

marker text and choosing Marker Search


Markers and Traces

• If we select the trace where 4V, 240mA lies and hold down the mouse button, we can see the gate voltage on the bottom left of the screen

Building the Amplifier


Create a New Schematic

• Create a new schematic and name it “1Stage_Amp”• This schematic will need the following elements that can all be found under Libraries > *TQOR TQPED

– Capacitors > Lumped > TQPED_CAPA (x3)– PHEMT >TOM3> PHEMT_Instances > TQPED_EHSS_T3_Inst (x2)– Resistors > Lumped > TQPED_RESW (x6)– Spirals > TQPED_MRIND (x1)– Vias and Pads > TQPED_SVIA (x3)– Vias and Pads > TQPED_PAD (x3)

• These are standard elements– Ports > Port (x2) (Can also use Ctrl+P)– Ports > PORT_NAME (x1)


1Stage_Amp Schematic – Full View

TQPED_RESWID=R2R=100 OhmW=5 umL=10 umTYPE=NiCr

TQPED_RESWID=R6R=2760/4 OhmW=5 umTYPE=NiCr

TQPED_RESWID=R3R=1000 OhmW=50 umTYPE=HVR

TQPED_CAPAID=C1C=2.8 pFA=1W=66 umL=66 um


TQPED_CAPAID=C2C=2.8 pFA=1

1

2

3




TQPED_CAPAID=C3C=10 pFA=1W=125.5 umL=125.5 um

VG_CHIP

PORTP=1Z=50 OhmPIN_ID=RF_IN

PORTP=2Z=50 OhmPIN_ID=RF_OUT

TQPED_MRIND2ID=L1W=25 umS=20 umN=6L1=145 umL2=150 umUNDERWIDTH=40 umLVS_IND="5"LT=PlatedMSUB=SNAME="TQPED_MRIND"

1

TQPED_PADID=RF_IN

TQPED_SVIAID=V3W=90 umL=90 um



1

TQPED_PADID=RF_OUT

1

TQPED_PADID=VG

1

2

3


Note: The orientation of the capacitors is important. Look at the “\” on the symbol - that is pin 1.


1Stage_Amp Schematic – Resistor Bank







1

2

3





VG_CHIP




1

TQPED_PADID=RF_IN




1

TQPED_PADID=RF_OUT

1

TQPED_PADID=VG

1

2

3


Hint: Use your new hotkey “R” torotate the elements after placing them.

Also, use copy and paste for multiple elements that are the same.


1Stage_Amp Schematic – Active Bias







1

2

3





VG_CHIP




1

TQPED_PADID=RF_IN




1

TQPED_PADID=RF_OUT

1

TQPED_PADID=VG

1

2

3



1Stage_Amp Schematic – Active Bias







1

2

3





VG_CHIP




1

TQPED_PADID=RF_IN




1

TQPED_PADID=RF_OUT

1

TQPED_PADID=VG

1

2

3


See next slides for details onsetting inductor parameters


Secondary Parameters

• You will need to modify some of the secondary parameters of the inductor

• Right-click on the inductor symbol and choose Properties• Click on the Show Secondary button to expose all the

parameters

• You will need to add a PIN_ID parameter to Port 2 called “RF_OUT”


Secondary Parameters

• Make sure the parameters of your inductor match these:

Schematic Layout - Placement


Amplifier Layout

• We want to make the layout snap 0.1 um• Choose Options > Layout Options• Change the grid spacing to “0.1” um


Amplifier Layout

• Open the layout view of the “1Stage_Amp” schematic. It might look something like this (a mess)


Importing GDSII Libraries

• Import a GDSII library into AWRDE by switching to the Layout tab and right-clicking on Cell Libraries > Import GDSII Library

• Import Class_Lib.gds from your Training folder


Amplifier Layout

• With your schematic layout view open, click on the Layout tab and click on the Cell Library called Class_Lib• Toward the lower left corner, you will see a Layout Cell called Class_Lib• Drag this cell into the layout window

Then drag from here

Click here


Amplifier Layout

• The schematic layout should now look like this


Amplifier Layout

• Place all your components so they match the footprints given in the artwork cell (use Ctrl key while dragging to enable snap models)• This will be demonstrated• You will notice that you end up missing three “RF OUT” bondpads


Vector Instance

• Open the schematic view of the amplifier

• Right click on the TQPED_PAD called “RF_OUT” and choose Properties

• Click on the Vector tab and enter “[0:3]”


Vector Instance

• After creating a vector instance the schematic wire will default to be a “bus” instead of a wire. This is not what we want as all the bond pads should be shorted to each other, not connected to individual bus lines.

• Busses are denoted by thick wires• Double-click on the wire name to edit and change it from “B1[0:3]” to “B1”

B1

1

2

3


1

TQPED_PADID=RF_OUT[0:3]


B1[0:3]

1

2

3


1




Vector Instance

• Open the layout view of the schematic, and you will now see 4 instances of the “RF_OUT” bond pad• Place these appropriately• When finished, select the footprint artwork cell and delete it (Ctrl + Shift in conjunction with Left Mouse Click provides “cycle select” capability, which might be needed to select the artwork cell).• The layout should now look something like this:


Associating Artwork with Schematic Elements

• Open the schematic view of the amplifier• Open the properties dialog of Port 2• Click on the Layout tab and select RECT_PIN



• Open the layout view of the amplifier• Find the layout for Port 2, right-click on it and select Shape

Properties• Change the Line Type to “Metal2”



• Move and stretch the RECT_PIN so it encompasses all the RF_OUT pads• To stretch the RECT_PIN, double-click on it to bring up the drag handles• Use the Ctrl key to snap the corners of the RECT_PIN to the corners of

the pads



• Repeat the same steps for both the PORT 1 and VG_CHIP elements, this time using the RECT_PIN layout to “overlap” their corresponding individual TQPED_PAD layouts

• This time leave the Line Type at Metal0 in the Shape Properties dialog• Hold down Ctrl to snap to corners


Adding Text to Layout

• Open the schematic view of the amplifier• Click on the Elements tab• Browse for TQPED_TEXT under Libraries > *TQOR TQPED > Shortcuts > Text• Drag the TQPED_TEXT element into the schematic, and edit the parameters to match what is below:

TQOR TEXT

TQPED_TEXTID=T3TEXT="Example\nPED Amp"XSPACE=10 umYSPACE=10 umSIZE=Large


Adding Text to Layout

• Open the layout view of the amplifier

• Put the text wherever you like


Changing Layout Parameters

• It is possible to change some parameters of certain PDK elements that only affect their layout

• Right-click on the large cap on the bottom left of the amplifier and select Shape Properties

• Click on the Parameters tab and change M1Top from “0” to “1” . Notice how the layout changed.

• Do the same for the other two caps


Changing Layout Parameters

• We also want to change some of the shape properties of the larger eHEMT device.

• Change DFING_LT, SFING_LT, and DPAD_LT from “0” to “2”• Change GPAD_LT from “0” to “1”

Schematic Layout - Routing


iNet Routing

• iNets are intelligent paths that can be used to draw electrical connectivity in layout

• The linetype and default width of the iNet is controlled in the Routing Properties dialog

• Bring up this dialog by clicking on the Show Routing Properties button


iNet Routing

• Change the default width to “70” um and make sure the Line type is set to “Metal0”

• To activate the iNet routing mode, double-click on any red ratline


iNet Routing

• To start routing, left-click at the center of the RF_IN pad (the cursor will snap to the center of the pad)

• Move the mouse to the left and double-click on the center of the nearest capacitor


iNet Routing

• Notice when the route is complete, the ratline disappears• Repeat this procedure by connecting the two smaller capacitors with

a 70um net on Metal1• To change the line type mid-route, hit Ctrl+Shift and roll the mouse

wheel• Then connect the center capacitor to the larger capacitor with a 70um

net on Metal0.


iNet Routing

• Continue routing until you have a layout that looks something like this:


Shape iNets

• For the traces that connect the large eHEMT to the rest of the MMIC, instead of using standard iNets, we will use shape iNets

• Draw a rectangle on Metal1 that connects the gate of the device to the inductor and the HVR resistor

• To draw the rectangle, first click on the Layout tab and select the Metal1 draw layer.

• Next, click on the Draw Rectangle button and draw the rectangle.


Shape iNets

• The rectangle should look like this:


Shape iNets

• While holding down Shift, select the rectangle and one of the ratlines.• Then right-click and select Associate Net Routes• Notice that the ratlines disappear


Shape iNets

• Repeat the same procedure for the drain connection, but this time draw a 6-sided polygon using the Draw Polygon button

• This time use Metal2

Hint: Use the Ctrl key to snap to vertices.


Shape iNets

• This is what the completed layout should look like. There should be no ratlines.

Schematic Layout - Verification


Verification

• Run a quick DRC / LVS on this complete design• Choose Scripts > Global Scripts > Run_TQOR_ICED_v8


Verification - DRC

• Start by browsing to the paths of ICED and the TriQuint verification project (should be the same as shown below).

• Choose ICED DRC only (note that mailDRC is supported).• Press OK


Verification - DRC

• After the DRC is complete the errors will appear in the AWRDE DRC Error Viewer.

• Tile out the DRC error window and the Layout Window. • If desired, double-click on errors to zoom in on them.• When finished choose DRC > Clear DRC errors.


Verification - LVS

• Re-run the script, this time choosing ICED LVS only.• Note that all paths and options are remembered on subsequent runs

so browsing is not necessary.• Click OK


Verification - LVS

• After the LVS is complete the errors will appear in the AWRDE LVS Error Viewer, which cross probes between the schematic and layout.

• Tile out the LVS error window, the Layout Window and the Schematic Window.

• When finished chose DRC > Clear LVS errors.

Load Pull Analysis


Load Pull

• Create a new schematic called “Load_Pull”• We want to place an instance of “1Stage_Amp” into the Load_Pull

schematic. • To insert a subcircuit into a schematic, either press the “Subcircuit”

button or use Ctrl+K

1 RF_OUT

SUBCKTID=S1NET="1Stage_Amp"VG_CHIP=VG_CHIP


Changing Symbols

• We want to change the symbol for the 1Stage_Amp subcircuit to something more meaningful• Right-click on the 1Stage_Amp subcircuit, and choose Properties• Click on the Symbol tab• Change the number of nodes to “2” and click on [email protected] in the list of symbols



3:Bias

1 2

LTUNER2ID=TU1Mag=0.5Ang=0 DegZo=50 Ohm

DCVSID=V2V=VG V

DCVSID=V1V=VD V

PORT1P=1Z=50 OhmPwr=12 dBm

VG_CHIP

PORTP=2Z=50 Ohm

Load Pull

• Create the schematic shown below• Use Ctrl+L to find the elements by the element name

Hint: This element is an NCONN,and NCONN names are case-sensitive


Global Definitions

• VG and VD need to be defined, and since they will most likely be used in more that one place, it will be easiest to define them globally

• Double-click on Global Definitions in the Project browser.

• Click on the Equation button to enter values for VG and VD

• When entering equations, if you click Shift+Enter you can enter the next equation on a new line

Note: Variables are case-sensitive


Adding DC Annotations

• To make sure the active device is being biased properly, we need to add DC annotations

• With the “Load_Pull” schematic open, click on the Annotation button

• This will bring up the Add Annotation dialog which is very similar to the Add Measurement dialog

• Select DCIA and click Apply• Select DCVA_N and click OK• Don’t forget to change the

simulator to Aplac DC


DC Annotations

• Click on the Simulate button to make the DC annotations appear on the schematic

• Select the “1Stage_Amp” subcircuit and click on the Edit Subcircuit button to descend into the subcircuit

• Note that the annotations are also included in the subcircuit

B1[0:3]


1.24 V0.753 mA


1.76 V

0.753 mA


2.28 V0.753 mA


0.00403 mA

1

2

3


0.075 V0.749 mA

6.87e-6 mA

0.749 mA

1

2

3


0.717 V0.00403 mA

3.7 V253 mA

0.00278 V253 mA

TQPED_CAPAID=C3C=10 pFA=1

0.721 V

0 mA


1.65e-5 V0 mA


0 V0 mA

0.717 V

VG_CHIP


PORTP=1Z=50 Ohm

TQOR TEXT

TQPED_TEXTID=T1TEXT="Example\nPED Amp"XSPACE=10 umYSPACE=10 umSIZE=Large

1


#1: 0 V#2: 0 V#3: 0 V#0: 0 mA#1: 0 mA#2: 0 mA#3: 0 mA

1

TQPED_PADID=RF_IN

0 mA

1

TQPED_PADID=VG

2.8 V0 mA


127 mA


127 mA


0.749 mA

TQPED_MRIND2ID=L1W=25 umS=20 umN=6LVS_IND="5"

0 mA

TQPED_RESWID=R6R=100 OhmW=5 umTYPE=NiCr

0.749 mA


0.753 mA


Load Pull Wizard

• In order to conduct load pull, there must be a measurement for the parameter we are trying to optimize

• Add a rectangular graph called “LoadPull Pout” and add the following measurement to it. We are going to use APLAC.

Make sure this is PORT_2

Don’t forget to check dBm

Change simulator to Aplac HB


Load Pull Wizard

• To start the Load Pull Wizard, expand the Wizards node in the Project browser and double-click on AWR Load Pull Wizard

• You will get this dialog


Load Pull Wizard

• Click on the Add button to choose a measurement • We only have one measurement, so the choice is easy• Name the data file “Pout_Data”

• Change the Center Mag to “0.5”, the Center Ang to “180”, and the Radius to “0.4”

• Click on Coarse and click Set Center and Radius (very important)• The Smith Chart will update to show the points that will be swept


Load Pull Wizard

• Click Simulate to start the load pull sweep


Load Pull Wizard

• When the simulation is complete, you will see a Smith Chart with load pull contours

• To get rid of “extra” contours, right-click on the graph, choose Modify Measurement, select the LPCS measurement, and increase the Contour Min value to 23 or 24

• You may also want to change the Countour Step to 0.25


Load Pull Wizard

• Add a measurement to the Smith Chart called “LPCSMAX” and click Simulate to update the plot

• Add a marker to the LPCSMAX point


Re-Normalizing Graph

• To get a more meaningful impedance value from the Smith Chart, the graph needs to be re-normalized to 50 Ohms

• Open the graph properties dialog and click on the Markers tab• Change Z or Y display to be “Denormalized to 50.0 Ohms”


Re-Normalizing Graph

• Now click on the Traces tab and change the weight of the second trace to make the marker more bold


Load Pull Wizard

• The marker will look like this after de-normalization

Creating And Editing Schematics (Part 2)

Simple Output Match


Populating a New Schematic

• Create a new schematic called “Output_Match”.

CAPID=C2C=2 pF

CAPID=C1C=100 pF

VD_MODULE

PORTP=1Z=50 Ohm

INDID=L2L=1.7 nH

PORTP=2Z=50 Ohm

INDID=L1L=4 nH


Tuning the Output Match

• Add an S11 measurement of the Output_Match circuit to the “Load Pull Data Contour Graph”


Tuning the Output Match

• Simulate, and the graph should look like this

Nonlinear Simulation


Adding Subcircuits

• Create another new schematic called “Packaged_Amp” • Associate the new schematic with the AWR_Module LPF• Insert “1Stage_Amp” and “Output_Match” subcircuits into

the schematic

1 2

SUBCKTID=S2NET="Output_Match"VD_MODULE=VD_MODULE

1 RF_OUT



Approximating Bondwires

• Change the symbol for the 1Stage_Amp subcircuit like we did before

• Now we want to add equivalent bondwire models to the schematic using the SRL elements (Elements > Inductors > SRL)

• Change the R and L values of the SRL element to match what is below

• This element is called NCONN and is located under Interconnects

SRLID=LbondVCC1R=0.1 OhmL=0.7 nH

SRLID=LbondIn1R=0.1 OhmL=0.7 nH

SRLID=LbondOut1R=0.07 OhmL=0.3 nH

VG_CHIP

GND_MODULE

VD_MODULE

VG_MODULE

PORTP=2Z=50 Ohm

PORTP=1Z=50 Ohm


1 2

SUBCKTID=S2NET="Output_Match"VD_MODULE=VD_MODULE


Pin=12

DCVSID=V1V=VD V

Xo Xn. . .

SWPVARID=SWP1VarName="Pin"Values=stepped(0,12,1)UnitType=None

DCVSID=V2V=VG V

SUBCKTID=S1NET="Packaged_Amp"GND_MODULE=GND_MODULEVD_MODULE=VD_MODULEVG_MODULE=VG_MODULE

PORT1P=1Z=50 OhmPwr=Pin dBm

PORTP=2Z=50 Ohm

GND_MODULEVG_MODULEVD_MODULE

Nonlinear Test Bench

• Create a new Schematic named “Power_Sweep”

• Insert the “Packaged_Amp” subcircuit and change the symbol to look like a two-port amp

• Populate the schematic so it looks like this:

Pin must be explicitly defined.

Don’t forget quotation marks.


Nonlinear Test Bench

• Add DC voltage and current annotations to the Power_Sweep schematic

• Click on the “Packaged_Amp” subcircuit, and click the Edit Subcircuit button

• Click on the “1Stage_Amp” subcircuit, and click the Edit Subcircuit button again• Zoom in on the active device to make sure it is biased properly


Nonlinear Measurement

• We now want to create a plot of Pout vs Pin• Create a new rectangular graph called “Power Sweep”• Add the following measurement to the graph



• Click Simulate and your graph should look like this:

• Duplicate the Pcomp measurement using the “drag and drop” technique



• Modify the new measurement to measure power gain

These are NOT the default values



• Simulate, and your graph will look like this


Plotting One Measurement Vs Another

• To plot Gain vs. Output Power first make a new rectangular graph and then add the measurement shown below.

• The “PlotVs” Measurement makes it easy to plot any single measurement vs. another.

• In this case the plot uses the existing Output Power and Gain measurements.


Plotting One Measurement Vs Another

• The “PlotVs” plot is shown below.


Using MPROBE

• AWR has a unique measurement probe called MPROBE that allows the user to make virtually any kind of measurement on their circuit and have the results update real-time

• Open the 1Stage_Amp circuit and place an MPROBE at the gate of the output eHEMT

• To place an MPROBE, click on the Measurement Probe button

B1

1

2

3


M_PROBEID=VP1

1






Using MPROBE

• Add a new rectangular graph called “Waveforms”• Open the “Add Measurement” dialog and choose the Vtime measurement

under Nonlinear > Voltage• Choose Power_Sweep as the “Data Source Name”• Choose M_PROBE.VP1 as the “Measurement Component”• Choose Plot all traces for “Sweep Freq” and choose Pin=13 for

“SWPVAR.SWP1”

Note: Do NOT click OK before continuing to the next slide


Using MPROBE

• Click Apply, then add the equivalent measurement using Itime under Nonlinear > Current


Using MPROBE

• Your graph should look like this


Using MPROBE

• Open the Graph Properties and click on the Measurements tab

• Click the AutoStack button


Using MPROBE

• Your graph will now look like this


Using MPROBE

• Now with only the 1Stage_Amp schematic and the Waveforms graph tiled horizontally, start moving the MPROBE around in the schematic.

• Note: the MPROBE must be placed within 1 grid space of an element node for it to work


Using MPROBE

• MPROBE also has a dynamic mode• Right-click on the MRPOBE and select Dynamic Probe• Now you can click anywhere in the circuit and even ascend/descend hierarchy

• Disable the time-domain measurements when done

Nonlinear Noise Analysis


Nonlinear Noise Analysis – Duplicate Schematic

• Before running Noise Analysis, let’s create a noise analysis test bench

• Using the same “drag and drop” technique used to duplicate a measurement, duplicate the “Power_Sweep” schematic and rename it to “Noise_Sweep”


Nonlinear Noise Analysis – NLNOISE Block

• Open the Noise_Sweep schematic and delete the SWPVAR block• Using the Add Element button (or Ctrl + L), add an NLNOISE block

to the schematic

Pin=12.5

DCVSID=V2V=VG V

DCVSID=V1V=VD V

GND_ModuleVD_MODULE VG_MODULE

PORT1P=1Z=50 OhmPwr=Pin dBm

PORTP=2Z=50 Ohm


NLNOISEID=NS1PortTo=2PortFrom=1NFstart=0.1 GHzNFend=0.2 GHzNFsteps=5SwpType=LINEARLSTone={1}SSTone=2


Nonlinear Noise Analysis – NLNOISE Block

• Modify the NLNOISE block so the parameters match what is shown below

NLNOISEID=NS1PortTo=2PortFrom=1NFstart=0.01 GHzNFend=0.01 GHzNFsteps=1SwpType=LINEARLSTone=1SSTone=2


Nonlinear Noise Analysis – NOIS Parameter

• Open the 1Stage_Amp schematic and double-click on one of the eHEMT devices• Click on the Parameters tab and click Show Secondary• Change the NOIS parameter to “1”

• Repeat the same steps for the other eHEMT device


Nonlinear Noise Analysis - Measurement

• Create a new rectangular graph and name it “NL Noise”

• Right-click on the graph and choose Add New Measurement



• Choose NPo_NL_BW under Nonlinear > Noise• Select Noise_Sweep as the source• Change the Measurement Bandwidth to “30e3”, change the

Simulator to APLAC HB, and make sure to check the dBm box



• Click Simulate to see the results on the graph


Nonlinear Noise Analysis – Noise Contributors

• Click Scripts > Global Scripts > NL_Noise_APLAC (Main)

• Choose Noise Power and Both then click OK



• This will run the Nonlinear Noise Contributors script through the APLAC native noise simulator

• When the simulation is complete, click on the Info tab in the Status window and search for

• Click on the links to bring up lists of the nonlinear noise contributors



• Disable the Nonlinear Noise Measurement when done

Yield Analysis


Yield Analysis

• Before running Yield Analysis, we need to import a script with a special histogram function• Click on the Scripting Editor button to open the scripting editor

• Right-click where you see your project name in the scripting editor’s Project browser, and choose Import

• Browse to Equations.bas in C:\Training_Extra\Scripts• Close the scripting editor and save the project


Yield Analysis

• Before running Yield Analysis, let’s trim down the number of simulation points.

• Go to the Power_Sweep Schematic and change the step size on the “Pin” sweep to 5.

Xo Xn. . .



Pout = Power_Sweep:DB(|Pcomp(PORT_2,1)|)[X,3]Pout: Pout=Pout+30

Adding Equations For Histograms

• Add the following equations to Output Equations by double-clicking on Output Equations in the Project Browser

• Note that 30 is added to Pout to convert from dBW to dBm

Output Equation

Regular Equations

Note: See next slide for details on adding the “Pout” Output Equation



• When adding the Pout Measurement Equation note that the input power sweep is set to Pin = 10 dBm, not Plot all Values



• Add the following text and equation to Output Equations. • The YieldHist() function is used to plot yield histograms.

YieldHist(value, binStart, binStop, binStep, dataFileName)x=YieldHist( Pout, 20, 30, 0.25, "Pout_10dBm_In")


Adding Graph For Histograms

• Add a Graph called “Generate Histogram”• Add a measurement that plots the value of “x” from the Output Equation added on the previous slide. • Note that “x” by itself has no meaning, but this measurement causes the histogram to update during each Monte

Carlo Iteration.


TriQuint Process Yield Analysis

• For TriQuint libraries all yield analysis is controlled by the PROCESS block on the Global Definitions Page

• Double-click on it to see the different variables and their yield analysis setup.

MODEL

TQPED_PROCID=TQPEDKIS=1KVPD=0KVPE=0KEGCS=1KMIM=1KRNI=1KRSH=1.008KRHV=1KHSILK=0KHMILK=0KHSPLK=1KHMPLK=1


Standard Component Yield Analysis

• For all other components, yield setup is done in the “Element Options” dialog, Statistics tab for the individual components or substrates.

• For example, set up the series “L” in the Output_Match schematic as a 10% part with Gaussian distribution edit as follows.

INDID=L2L=1.905 nH


Running Yield Analysis

• Yield Goals are set up the same as Optimization Goals used previously, but are under the Yield Analysis node.

• They are not required to run yield and look at the performance variation.

• Choose Simulate > Yield Analysis to bring up the Yield Simulation control.

• Change the Maximum Iterations to “50” and press the Start button.


Viewing Monte Carlo Traces

• As the Yield Analysis runs (may take a bit on slow training machines and with a power sweep) the performance variation is displayed on the graphs.



• The Graph Properties (right-click on the graph and choose Properties) control this display on the Yield Data tab.

• Make the changes shown below.



• Now the Graph will only show the minimum and maximum performance.


Plotting Histograms

• Make a new Graph called “Pout Histogram”

• Add a PlotCol Measurement to this Graph as shown below.

• This measurement is plotting the histogram data from the YieldHist() equation that is now stored in the Pout_10dBm_In data file. Column 1 is the input power and column 2 is the output power.


Plotting Histograms

• Right-click on the graph, choose Properties, click on the Traces tab, and change the “Type” to Histogram

• The data is very coarse because only 50 simulations were run.


Plotting Histograms

• Disable all measurements on the “Pout Histogram” and “Generate Histogram” graphs by right-clicking on the graphs in the Project browser and choosing Disable All Measurements


Resetting Trace Properties

• Return to any Graph Properties that were adjusted and recheck “Show traces” and “All traces” on the Yield Data tab.

• Click on Clear in the Yield Analysis window


Yield Analysis

• Reset the Power_Sweep Schematic SWPVAR block to use 1 dB steps.

Xo Xn. . .


Automated Circuit Extraction (ACE)


The EXTRACT Block

• Open the schematic and layout views of the 1Stage_Amp schematic and tile them

• Insert an EXTRACT block using the element finder• Change the settings to match what is below

Name of the extracted EM structureName of the group of extracted elements

Simulator of choiceX and Y grid size

Which STACKUP to use (in Global Defs)

Should the extraction happen if this is in hierarchy?

EXTRACTID=EX1EM_Doc="EM_Extract_Nets"Name="EM_Extract"Simulator=ACEX_Cell_Size=1 umY_Cell_Size=1 umSTACKUP="TQPED_STACK"Override_Options=YesHierarchy=On


The STACKUP

• Open the Global Definitions• Double-click on the TQPED STACKUP element• The Material Defs. tab is where all the different materials used in the

stackup are defined


The STACKUP

• The Dielectric Layers tab defines the thickness of each layer and allows you to scale the way they are drawn so the 3D view of the EM structure is easier to see


The STACKUP

• The Materials tab defines the thickness of material (conductors, vias, etc)


The STACKUP

• The EM Layer Mapping tab defines which EM layer each drawing layer maps to, as well as which material it uses


The STACKUP

• Click on the Line Type tab to see how each line type is mapped into the EM structure


ACE Extraction – Selecting iNets

• Close the Global Definitions window and return to the layout view of 1Stage_Amp

• Select the blue iNet connecting the capacitors to the spiral inductor• Right-click and choose Element Properties



• Click on the “Model Options” tab and check the box next to “Enable”

• That means this net is now included in the extract group called “EM_Extract”

• Repeat the same procedure for all the other iNets we routed (not the shapes). NOTE: You can use Shift to multi-select nets



• Click once one the EXTRACT block to highlight the selected nets in both the schematic and layout views


ACE Extraction

• Click Simulate and a window will pop up showing a 2D view of the extracted traces

• Click on the “View EM 3D Layout” button to get a better view of the extracted nets


ACE Extraction

• 3D view of extracted nets


ACE Extraction – 3D Annotation

• Click on the EM Annotation button to bring up the Add Annotation dialog

• Choose ERC > EXT_CKT3D as the measurement• You can leave the symbol at its

default value of “10e-6”, or make it larger so the extracted elements are easier to view


ACE Extraction – 3D Annotation

• Click Simulate and your 3D view will now show the extracted components


ACE Extraction – Coupling

• We may want to include coupling effects in our simulation results• To “turn on” coupling, open the schematic view of 1Stage_Amp• Double-click on the EXTRACT block and click on the ACE tab• Change Max Coupled Dist to “20” um• Click Simulate, and note the change in the 3D EM view


ACE Extraction – Coupling


ACE Extraction

• You can enable and disable the EXTRACT block to compare the simulation results with and without the traces extracted• To see a netlist representation of what is being extracted, open the Status window and click on the link that looks like this:

• This will show you a netlist of every element that was used in the extracted document


EM Extraction – Verify Results

• The graphs now show the “merged” results that include the ACE simulations.

• Press Ctrl + F on the graph to freeze the traces, disable the EXTRACT block on the schematic, and re-simulate to compare the results with and without the extraction.

• RE-ENABLE THE EXTRACT BLOCK ON THE SCHEMATIC WHEN DONE.

Electromagnetic Extraction Using Axiem


The EXTRACT Block

• Use AXIEM to make a better model for the inductor

• Insert a new EXTRACT block in “1Stage_Amp” using the Element Finder

• Change the settings to match what is below

Name of the extracted EM structureName of the group of extracted elements

Simulator of choiceX and Y grid size

Which STACKUP to use (in Global Defs)

Should the extraction happen if this is in hierarchy

EXTRACTID=EX2EM_Doc="EM_Extract_Ind"Name="EM_Extract_Ind"Simulator=AXIEMX_Cell_Size=10 umY_Cell_Size=10 umSTACKUP="TQPED_STACK"Override_Options=YesHierarchy=On


EXTRACT Frequencies

• Double-click on the EXTRACT block and change the settings on each tab. For fast simulation on the training machines some simplified settings are used.

• Set the Frequencies to go from DC to 12.5 GHz (5 harmonics) as shown, and don’t forget the Apply button!


EXTRACT Mesh Settings

• Set the Mesh settings as shown


EXTRACT Axiem Settings

• Set the Axiem settings as shown


• Similar to adding the nets to the ACE Extract group the inductor needs to be added to an Extract group.

• Double-click on the inductor in the schematic, go to the Model Options tab, enable it for extraction and set the Group name to “EM_Extract_Ind”

Axiem Extraction – Selecting iNets


Double-click


Axiem Extraction – Selecting iNets

• Click once one the EXTRACT block to make sure that it is associated with the inductor.


EM Extraction - Axiem

• Now when you simulate, it will kick off an EM simulation of the inductor using Axiem

• This will obviously take longer than our ACE extraction because it is a full EM simulation

• When it is done simulating, open the 3D view of the extracted document• Add a mesh annotation by clicking on the EM Annotation button and

selecting Planar EM > EM_MESH_F. Change the Opacity to 0.5.


EM Extraction – Cut Planes

• With the 3D view of the EM structure open, click on the Use cut plane button

• Drag the cut plane to move it, and drag the arrows to rotate the plane

• Some of the hotkeys for manipulating the cut plane are– Change cut axis: X, Y, or Z– Flip cut axis: Shift + X, Y, or Z


EM Extraction – Verify Results

• The graphs now show the “merged” results that include the ACE and Axiem simulations.

• Press Ctrl + F on the graph to freeze the traces, disable the EXTRACT blocks on the schematic, and re-simulate to compare the results with and without the extraction.

• RE-ENABLE THE EXTRACT BLOCK ON THE SCHEMATIC WHEN DONE.

System Simulation

ACPR and EVM


Copying Schematics

• Copy the “Power_Sweep” schematic by dragging and dropping it on the “Circuit Schematics” node in the “Project” tab.

• Note the new schematic is named “Power_Sweep_1”


Renaming Schematics

• Rename “Power_Sweep_1” to “System_Test_Bench”


Making a System Test Bench

• On the System_Test_Bench delete the SWPVAR block • Replace the PORT1 element with a PORT_PS1• Set the port power sweep to go from -30 dBm to 10 dBm in

steps of 1 dB

PORTP=2Z=50 Ohm

DCVSID=V2V=VG V

DCVSID=V1V=VD V


VG_MODULEVD_MODULE

PORT_PS1P=1Z=50 OhmPStart=-30 dBmPStop=10 dBmPStep=1 dB

GND_MODULE


New System Diagrams

• Now go back to the “Project” tab and make a new System Diagram named “EDGE_Test_Bench” by right-clicking on System Diagrams and choosing New System Diagram


Instantiate Module in System

• On the Elements tab find System_Test_Bench under Subcircuits > NL_S and place it on the “EDGE_Test_Bench”.

• This instantiates the module circuit into the System Diagram.


Build Up System

• Build the remainder of the circuit as shown below.

TPID=INBUFSZ=

NL_SID=S1NET="System_Test_Bench"NOISE=Auto

MPSK_SRCID=A1MOD=8-PSKOUTLVL=PWROLVLTYP=Avg. Power (dBm)RATE=2.708e5CTRFRQ=2.5 GHzCDNG=GrayPLSTYP=GMSKALPHA=0.3PLSLN=

SRC MEAS

VSAID=M1VARNAME="PWR"VALUES=PWR_SWEEPSWPCNT=2.5e4

SRCMEAS

VSAID=M2VARNAME=""VALUES=0

PWR_SWEEP=stepped(-5,12,1)PWR=5

TPID=OUT


ACPR Graph

• Make a new graph named “ACPR” and add the two measurements shown.

• One measurement is high side (+250kHz) ACPR and one is low side (-250kHz)


EVM Graph

• Make a new graph named “EVM” and add the measurement shown.


Spectrum Graph

• Make a new graph named “Spectrum” and add the measurements shown

• Note that one measurement is input spectrum (TP.IN) and one is output spectrum (TP.OUT). Don’t forget to check dBm.


System Simulator

• Tile the system diagram and graphs as shown and press the Run/Stop System Simulators button to start a new power sweep


Conclusion

• We created a 2.5 GHz Amplifier and learned how to:– Set hotkeys and customize the AWRDE– Create and edit schematics and layouts– Use TQ DRC and LVS– Simulate and tune– Optimize and use statistics– Use nonlinear noise analysis and contributors– Route iNets– Use ACE and Axiem in the “extraction flow”– Use system analysis (VSS)

power amplifier design

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