POWER CONVERTER II LAB

LIST OF EXPERIMENTS

EXP NO NAME OF THE EXPERIMENT

SIMULATION

1 Buck Converter

2 Boost Converter

3 Buck Boost Converter

4 Sepic Converter

HARDWARE

5 PWM Controller Using SG35256 Driving a MOSFET with SG35257 Design and Implementation of Turn-Off Snubber8 Design and Implementation of Turn-On Snubber9 Design and Implementation of Buck Converter10 Design and Implementation of Boost Converter11 Design and Implementation of Buck-Boost

Converter

Experiment No: 1

Simulation of buck converter

AIM:

Design and simulate a Buck Converter and observe the output waveform for the given

specifications.

Frequency f = 20 KHz

Input voltage Vi = 28V

Duty cycle D = 0.1 to 0.5

L=2mH

C=100microF

R=100Ohm

THEORY:

A buck converter produces a lower average output voltage than the dc input voltage.

Output voltage Vo = Duty Ratio (D)*Input voltage Vi

Its main application is in regulated dc power supplies and dc motor speed control.

SIMULATION DIAGRAM:

FORMULAE:

Output voltage Vo = Duty Ratio (D)*Input voltage V

Inductor Value L = Vo(1-D)/diL*Fs

Capacitor Value C = Vo(1-D)/8*(dVo/Vo)*L*Fs^2

WAVEFORMS:

Duty Ratio = 0.5

Output voltage:

Inductor current:

Inductor voltage:

Diode voltage:

Switch current:

Switch voltage:

RESULT:

Thus a buck converter is designed and simulated for the given specifications and the outputwaveforms are observed.

Experiment No:2

Simulation of Boost ConverterAIM:

Design and simulate a boost converter and observe the output waveform for the given

specifications.

Frequency f = 25 KHz

Input voltage Vi = 20

Duty cycle D = 0.5

Inductor- 2mH.

Resistor-100Ω

Capacitor-4.7µF

THEORY:

A step-up converter produces a higher average output voltage than the dc input voltage. By varying the duty ratio Ton/T, the output voltage Vo can be controlled.

Output voltage,VO = Vin / (1-D) = 50V

SIMULATION DIAGRAM:

OUTPUT WAVEFORMS:

1)SWITCH VOLTAGE

2)SWITCH CURRENT

3)INDUCTOR CURRENT

4)CAPACITOR CURRENT

5)DIODE CURRENT

RESULT:

Boost converter is designed and simulated for the given specifications and the waveforms are observed.

Experiment No:3

Simulation of Buck Boost Converter

AIM:

1) Observe voltage across diode, inductor and output voltage waveform2) Average voltage wave across inductor in steady state3) Inductor current waveform and output waveform4) Tabulate the steady state input output voltage for various duty cycle5) From tabulation find relation between duty cycle, input and output voltage6) Tabulate steady state input output current for various duty cycle and find relation

between duty cycle input current and output current

THEORY:

The main application of a step-down/step-up or buck-boost converter is in regulated dc power supplies, where a negative-polarity output may be desired with respect to the common terminal of the input voltage, and the output voltage can be either higher or lower than the input voltage.

A buck-boost converter can be obtained by the cascade connection of the two basic converters: the step -down and the step-up converter.

Vo/Vd = D/ (1-D)

This allows the output voltage to be higher or lower than the input voltage, based on the duty ratio D.

The cascade connection of the step-down and the step-up converters can be combined into the single buck-boost converter. When the switch is closed, the input provides energy to the inductor and the diode is reverse biased. When the switch is open, the energy stored in the inductor is transferred to the output. No energy is supplied by the input during this interval.

SIMULATION DIAGRAM:

Continuous

powergui

v+-

v+-

v+-

g mD S

Mosfet

In Mean

Mean Value

0.0008271

-11.57

0.0508

-57.86

-0.8422

-58.71

ma

kDiode

i+

- i+

-i + -20µH

80µF

5Ω

WAVEFORMS:

1) Diode Voltage

2) Inductor voltage

24V

2) Output Voltage

4) Average inductor voltage

5) Inductor current

6) Output current

TABULATION:

Duty Cycle Steady stateInput Voltage

Steady stateOutput Voltage

Steady stateInput Current

Steady stateOutputCurrent

Steady stateInductorCurrent

75% 24 -56.8 50 -11.35 49.5

60% 24 -32.45 20 -6.487 19.5

50% 24 -22.13 12 -4.425 12

40% 24 -14.75 7.2 -2.951 7.2

20% 24 -5.131 2.5 -1.025 2.5

RESULT:

Waveforms for diode voltage, inductor voltage, output voltage, and average voltage across inductor, inductor current and output current were obtained.

Relation between steady state input voltages, output voltage, input current, output current and inductor current for various duty cycles were tabulated. The output voltage obtained has negative polarity. When duty cycle is greater than 50% output stepped up. When duty cycle is lessthan 50% output voltage is stepped down. Input current and inductor current increase with increasing duty cycle.

Experiment No:4Simulation of Sepic Converter

AIM:

Design and simulate a SEPIC Converter and observe the output waveform for the given

specifications.

Frequency f = 100 KHz

Input voltage Vi = 9V

Duty cycle D = 0.4

THEORY:

A Single Ended Primary Inductance Converter (SEPIC) can produce an output voltage that is

either greater or less than the input with no polarity reversal.

Output voltage Vo = (Vi*D)/ (1-D)

.

SIMULATION DIAGRAM:

FORMULAE:

Output voltage Vo = (Vi*D)/(1-D)

Inductor Value L = (Vs*DTs)/Δil

Capacitor Value C = (DTs)/(R*(ΔVc/Vo)

OUTPUT WAVEFORMS:

Duty Ratio = 0.4

1)Pulses For Switches

2) Inductor Current IL1

3) Inductor Current IL2

4) Capacitor Current IC1

5) Capacitor Current IC2

RESULT:

SEPIC converter is designed and simulated for the given specifications and the output

waveforms are observed.

Experiment no:5

PWM controller Using SG3525AIM:

To study pulse width modulation using IC SG3525

THEORY:

PWM is used in all sorts of power control and converter circuits. Some common examples include motor control, DC-DC converters, DC-AC inverters and lamp dimmers. There are numerous PWM controllers available that make the use and applications of PWM quite easy. One of the most popular of such controllers is the versatile and ubiquitous SG3525 produced by multiple manufactures –ST microelectronics, Fairchild Semiconductors, On Semiconductors, to name a few.

SG3525 is used extensively in DC-DC converters, DC-AC inverters, home UPS systems, solar inverters, power supplies, battery chargers and numerous other applications.

WORKING PRINCIPLES:

(i)Inverting and Non-inverting Terminals:

Inverting and Non Inverting Input are the inputs to the on-board error amplifier. It acts as a comparator that controls the increase or decrease of the duty cycle for the “feedback” that you associate with Pulse Width Modulation (PWM). This functions either to increase or decrease the duty cycle depending on the voltage levels on the Inverting or Non-inverting Inputs Pin1 & Pin2 respectively.

When voltage on the Inverting Input (pin 1) is greater than voltage on the Non-Inverting Input (pin 2), duty cycle is decreased.

When voltage on the Non-Inverting Input (pin 2) is greater than voltage on the Inverting Input (pin 1), duty cycle is increased.

(ii)Frequency:

The frequency of PWM is dependent on the timing capacitance and the timing resistance. The timing capacitor (CT) is connected between pin 5 and ground. The timing resistor (RT) is connected between pin 6 and ground. The resistance between pins 5 and 7 (RD) determines the dead time (and also slightly affects the frequency).

The frequency is related to RT,CT and RD by the relationship:

f = 1CT (0.7 RT+3 RD)

With RT and RD in Ω and CT in F,F is in Hz.

Typical values of RD 10Ω to 47Ω.The range of values usable (as specified by the manufacturers

of SG3525) are 0Ω to 500Ω.

RT must be within the range 2kΩ to 150kΩ.CT must be within the range 1nF (code 102)

to 0.2µF (code 224).The oscillator frequency must be in the range 100Hz to 400kHz.There is a

flip-flop before the driver stage, due to which your output signals will have frequencies half that

of the oscillator frequency that is calculated using above mentioned formula. So, if you have a

50Hz inverter, you require drive signals of 50Hz. So the oscillator frequency must be 100Hz.

(iii)Duty cycle:A capacitance connected between pin 8 and ground provides the soft-start functionality.

The larger the capacitance, the larger the soft-start time. This means that the time taken to go

from 0% duty cycle to desired duty cycle or maximum duty cycle is larger. So, the duty cycle

increases more slowly initially. Keep in mind that this only affects initial rate of increases of

duty cycle, i.e., the rate of increase of duty cycle after the SG3525 starts up.

Typical values of the soft-start capacitance lie within the range 1µF to 22µF depending

on the desired soft-start time.

(iv)Output Terminals:Pins 11 and 14 are the drive outputs from which the drive signals are to be taken. They

are the outputs of the SG3525 internal driver stage and can be used to directly drive MOSFETs

and IGBTs. They have a continuous current rating of 100mA and a peak rating of 500mA.

When greater current or better drive is required, a further drive stage using discrete transistors

or a dedicated driver stage should be used. Similarly a driver stage should be used when driving

the device causing excessive power dissipation and heating of SG3525. When driving

MOSFETs in a bridge configuration, high-low gate drivers or gate-drive transformers must be

used as the SG3525 is designed only for low-side drive.

Pin 16 is the output from the voltage reference section. SG3525 contains an internal

voltage reference module rated at +5.1V that is trimmed to provide ±1% accuracy. This

reference is often used to provide a reference voltage to the error amplifier for setting the

feedback reference voltage. It can be directly connected to one of the inputs or a voltage divider

can be used to further scale down the voltage.

(v)VCC Supply:Pin 15 VCC – the supply voltage to the SG3525 that makes it run. VCC must lie within

the range 8V to 35V. SG3525 has an under-voltage lockout circuit that prevents operation when

VCC is below 8V,thus preventing erroneous operation or malfunction.

(vi) Drive Stage:Pin 13 is VC – the supply voltage to the SG3525 driver stage. It is connected to the

collectors of the NPN transistors in the output totem-pole stage. Hence the VC. VC must lie

within therange 4.5V to 35V.The output drive voltage will be one transistor voltage drop below

VC.So when driving power MOSFETs,VC should be within the range 9V to 18V(as most

power MOSFETs require minimum 8V to be fully on and have a maximum VGS breakdown

voltage of 20V).For driving logic level MOSFETs,lower VC may be used.Care must be taken to

ensure that the maximum VGS breakdown voltage of the MOSFET is not crossed.Similarly

when the SG3525 outputs are fed to another driver or IGBT,VC must be selected

accordingly,keeping in mind the required voltage for the device being fed or driven.It is

common practice to tie VC to VCC when VCC is below 20V.

(vii)Ground:

Pin 12 is the Ground connection and should be connected to the circuit ground.It must share a common ground with the device it drives.

(viii)Capacitor Discharge:

Pin 10 is shut down.When this pin is low,PWM is enabled.When this pin is high,the PWM latch is immediately set this provides the fastest turn-off signal to the outputs.At the same time the soft-start capacitor is discharged with a 150µA current source.an alternative method of shutting down the SG3525 is to pull either pin 8 or pin 9 low.However,this is not as quick as using the shutdown pin.So,when quick shutdown is required, a high signal must be applied to pin 10.This pin should not be left floating as it could pick up noise and cause problems.So,this pin is usually held low with a pull-down resistor with s1 closed, shutdown and with s1 open no shutdown occur.

(ix)Compensation:

Pin 9 is compensation.It may be used in conjunction with pin 1 to provide feedback compensation.

PIN CONNECTIONS:

BLOCK DIAGRAM

CIRCUIT DIAGRAM:

PROCEDURE:

(i) Make the connection shown in circuit diagram and switch ON the power supply(+12V)

(ii) Vary the 10k pot.This varies voltage at pin2 and thereby duty cycle at output A and output B vary.

(iii) Vary RD and observe the blanking time between output A and output B.(R=47ohm to 100ohm).

(iv) Open S1 switch and observe output A and output B.

(v) Close S1 switch and observe output A and output B.

(vi) Change frequency and repeat above mention.

Experiment No:6

Driving a Mosfet With SG3525

AIM

To drive a MOSFET with IC SG3525 and observe

(i) the effect of RC protection in drain to source voltage

(ii) miller effect in gate to source voltage

COMPONENTS REQUIRED

PWM-IC SG3525

MOSFET –IRF540

DIODE-IRF 540, Zener Diode

Resistor –100Ω , 157Ω,10Ω

Wire wound resistor -10Ω, 10W

Capacitor -1µF, 63V

CIRCUIT DIAGRAM

THEORY WITH DESIGN:

The Power MOSFET:

Unlike the Bipolar Junction Transistor ( BJT),the MOSET belongs to the unipolar device

family, since it uses only the majority carriers in conduction.The development of the metal oxide

semiconductor technology for microelectronic circuits opened the way for developing the power

metal oxide semiconductor field effect transistor (MOSFET) device in 1975.

MOSFET Regions of Operation:

Most of the MOSFET devices use in power electronics applications are of the n-

channel,enhancement type. For the MOSFET to carry drain current, a channel between the drain

and the source must be created. This occurs when the gate- to-source voltage exceeds the device

threshold voltage, VTh. . For VGS > VTh ,the device can either be in triode region, which is also

called as “constant resistance region” ,or in the saturation region, depending on the value of VDS.

For VGS <VTh, the device turns off,with the drain current almost equals zero. Under both regions

of operation, the gate current is almost zero.

Fig:MOSFET region of operation

MOSFET Switching characteristics:

Since the MOSFET is a majority carrier transport device, it is inherently capable of a high

frequency operation . But still the mosfet has two limitations:

1.High input gate capacitances.

2.Transcient/delay to carrier transport through the drift region.

As stated earlier the input capacitance consists of two components the gate-to-source and

gate-to-drain capacitances.The input capacitances can be expressed in terms of the device

junction capacitances by applying Miller theorem to Fig.4.15a. using Miller theorem, the total

input capacitance,Cin, seen between the gate-to-source is given by,

Cin = Cgs + (1+gm RL)Cgd

The frequency response of the MOSFET circuit is limited by the charging and discharging

times of Cin. Miller effect is inherent in any feedback transistor circuit with resistive load that

exhibits a feedback capacitance from the input and output.The output capacitance between the

drain-to- source resistance.The output capacitance between the drain-to-source,Cds does not

affect the turn-on and turn-off MOSFET switching the characteristics.Figure shows how C gd and

Cgs vary under increased drain-source, vds, voltage.

Experiment No:7Design and Implementation of Turn-Off Snubber

AIM:

To design and implement of turn off snubber for MOSFET device

COMPONENTS REQUIRED:

1. PWM-IC SG3525

2. MOSFET IRF540

3. DIODE

4. Resistors -100Ω or 200Ω

5. Wire wound resistor -100Ω

6. Capacitors -1 µF,10 µF,2200pF

CIRCUIT DIAGRAM:

THEORY:

Snubber circuits reduce power losses in a transistor during switching (although not necessarily total switching losses) and protect the device from the switching stresses of high voltages and currents. A large part of the power loss in a transistor occurs during switching. Figure 3-a shows a model for a converter that has a large inductive load which can be approximated as a current source IL. The analysis of switching transitions for this circuit relies on Kirchhoff’s laws: the load current must divide between the transistor and the diode; and the source voltage must divide between the transistor and the load. In the transistor on state, the diode is off and the transistor carries the load current. As the transistor turns off, the diode remains reverse-biased until the

transistor voltage vQ increases to the source voltage Vs and the load voltage vL decreases to zero.

After the transistor voltage reaches Vs, the diode current increases to IL while the transistor current decreases to zero. As a result, there is a point during turnoff when the transistor voltage and current are high simultaneously (Fig.3-1 b), resulting in a triangularly shaped instantaneous power waveform pQe(t), as in Fig.3-1c.

In the transistor off state, the diode carries the entire load current. During turn-on, the transistor voltage cannot fall below Vs until the diode turns off, which is when the transistor carries the entire load current and the diode current is zero. Again, there is a point when the transistor voltage and current are high simultaneously.

A snubber circuit alters the transistor voltage and current waveforms to an advantage. A typical snubber circuit is shown in Fig. 3-2a. The snubber provides another path for load current during turnoff. As the transistor is turning off and the voltage across it is increasing, the snubber diode Ds becomes forward biased and the capacitor begins to charge. The rate of change of transistor voltage is reduced by the capacitor, delaying its voltage transition from low to high. The capacitor charges to the final off-state voltage across the transistor and remains charged while the transistor is off. When the transistor turns on, the capacitor discharges through the snubber resistor and transistor.

The size of the snubber capacitor determines the rate of voltage rise across the switch at turnoff. The transistor carries the load current prior to turnoff, and during turnoff the transistor current decreases approximately linearly until it reaches zero. The load diode remains off until the capacitor voltage reaches Vs. The snubber capacitor carries the remainder of the load current until the load diode turns on. The transistor and snubber-capacitor currents during turnoff are expressed as

where tx is the time at which the capacitor voltage reaches its final value, which is determined by the source voltage of the circuit. The capacitor (and transistor) voltage is shown for different

values of C in Fig.3-2 b to d. A small snubber capacitor results in the voltage reaching Vs before the transistor current reaches zero, whereas larger capacitance results in longer times for the voltage to reach Vs. The energy absorbed by the transistor (the area under the instantaneous

If the switch current reaches zero before the capacitor fully charges, the capacitor voltage is determined from the first part of the above equation. Letting vc(tf) ≤ Vf ,

Solving for C

whereVf is the desired capacitor voltage when the transistor current reaches zero. The capacitor is sometimes selected such that the switch voltage reaches the final value at the same time that the current reaches zero, in which case

where Vs is the final voltage across the switch while it is open. Note that the final voltage across the transistor may be different from the dc supply voltage in some topologies. The forward and flyback converters for example, have off-state switch voltages of twice the dc input. The power absorbed by the transistor is reduced by the snubber circuit. The power absorbed by the

transistorbefore the snubber is added is determined from the waveform of Fig. 3-1c. Turnoff power losses

are determined from

The integral is evaluated by determining the area under the triangle for turnoff, resulting in an expression for turnoff power loss without a snubber

wherets ≤ tf is the turnoff switching time and f ≤ 1/T is the switching frequency. Power absorbed by the transistor during turnoff after the snubber is added is determined from

The above equation is valid for the case when tf ≤ tx, as in Fig. 3-2 c or d. The resistor is chosen such that the capacitor is discharged before the next time the transistor turns off. A time interval of three to five time constants is necessary for capacitor discharge. Assuming five time constants for complete discharge, the on time for the transistor is

The capacitor discharges through the resistor and the transistor when the transistor turns on. The energy stored in the capacitor is

This energy is transferred mostly to the resistor during the on time of the transistor. The power absorbed by the resistor is energy divided by time, with time equal to the switching period:

where f is the switching frequency.

Power dissipation in the snubber resistor is proportional to the size of the snubber capacitor. A large capacitor reduces the power loss in the transistor, but at the expense of power loss in the snubber resistor. Note that the power in the snubber resistor is independent of its value. The resistor value determines the discharge rate of the capacitor when the transistor turns on.

The power absorbed by the transistor is lowest for large capacitance, but the power absorbed by the snubber resistor is largest for this case. The total power for transistor turnoff is the sum of the transistor and snubber powers. Figure 3-3,shows the relationship among transistor, snubber, and total losses. The use of the snubber can reduce the total switching losses, but perhaps more importantly, the snubber reduces the power loss in the transistor and reduces the cooling requirements for the device. The transistor is more prone to failure and is harder to cool than the resistor, so the snubber makes the design more reliable.

DESIGN:

Switching frequency, f =10kHz

Let,

turn-off time, Tf = 50ns

diode current , ID=3A

Now, Capacitor, 𝐶 =

ID×Ts

2×𝑉Take Ton(min) of MOSFET =3µs (from data sheet)

Ton = 5RC = 20µs

R= 50Ω

C=2500pF

R and C values are for diode snubber

PROCEDURE:

1. Connections are made as per the circuit diagram

2. The pulses which are obtained from PWM Controller using ICSG3525 are given to gate

of MOSFET.

3. The ground of PWM controller circuit is given to the source of MOSFET.

4. Drive the MOSFET using 30V DC supply across drain and source.

5. Observe the voltage across drain and source of MOSFET i.e, Vds.

6. Repeat the same without using snubber circuit.

OBSERVATIONS:

VDS (spike magnitude) =

VDS =

Experiment No: 8Design and Implementation of Turn-On Snubber

AIM:

To design and implementation of turn on snubber for MOSFET device

COMPONENTS REQUIRED:

1. PWM-IC SG35252. MOSFET IRF5403. DIODE4. RESISTORS – 2Ω 5. WIRE WOUND RESISTOR -100Ω,10W6. CAPACITOR -10mF,1Mf7. INDUCTOR-1mH

CIRCUIT DIAGRAM:

THEORY:

A turn-on snubber is used to reduce voltage across the BJT while the current builds up. The reduction in the voltage across the transistor during turn on is due to the voltage drop across the snubber inductance LS. When the transistor turn off, the energy stored in the snubber inductance, will be dissipated in the snubber resistance RS.

Turn-on Snubber Circuit

Circuit topology

Circuit reduces Vsw as switch Sw turns on. Voltage drop provides the voltage reduction.

Turn-on Snubber Operating Waveforms

Small values of snubber inductance (Ls< Ls1)LS1=Vdtri/Io

Irr reduced when Ls> Ls1 because Irr proportional to disw/dt

Large values of snubber inductance (Ls> Ls1)

Irr reduced when Ls> Ls1 because Irr proportional to √disw/dt

Turn On Snubber Recovery at Switch Turn-off

Assume switch current fall time tri = 0 Inductor current must discharge thru DLs- RLs series segment

Switch waveforms at turn-off with turn-on snubber in circuit. Over voltage smaller if tfi smaller. Time of 2.3 Ls/RLs required for inductor current to decay to 0.1 Io Off-time of switch must be > 2.3 Ls/RLs

Turn-on Snubber Design Trade-offs

Selection of inductor Ls Larger Ls decreases energy dissipation in switch at turn-on Ls> Ls1 Wsw = 0 Larger Ls increases energy dissipation in RLs Ls> Ls1 reduces magnitude of reverse recovery current Irr

Inductor must carry current Io when switch is on – makes inductor expensive and hence turn-on snubber seldom used

Selection of resistor RLs Smaller values of RLs reduce switch overvoltage Io RLs at turn-off Limiting overvoltage to 0.1Vd yields RLs = 0.1 Vd/Io Larger values of RLs shortens minimum switch off-time of 2.3 Ls/RLs

DESIGN:

When MOSFET turns on capacitor discharges current,

ic(peak) < 0.2 Id ,

Let id = 3A, Vd = 30 V

Tf= 50 * 10-6 S

R < 30 / (0.2 * 0.3) = 50 Ω

Selecting 100 Ω or 200 Ω resistor

C = id * Tf / 2Vd = 3 * 50 * 10 -9 / (2 * 50) = 2500 pf

So selecting C = 2000 pf

PROCEDURE:

1. Connections are made as per the circuit diagram2. The pulses which are obtained from PWM Controller using ICSG3525 are given to gate

of MOSFET.3. The ground of PWM controller circuit is given to the source of MOSFET.4. Drive the MOSFET using 30V DC supply across drain and source.5. Observe the voltage across drain and source of MOSFET i.e, Vds.6. Repeat the same without using snubber circuit.

OBSERVATIONS:VDS (spike magnitude) =

VDS =

Experiment No: 9Design and Implementation of Buck Converter

AIM:

Design and implementation of Buck converter

COMPONENTS REQUIRED:

PWM-IC SG3525

MOSFET

Diode - FRD IN5408

Inductor - 2mH

Wire wound resistor -10Ω, 25W

Capacitor - 47uH , 0.1uH

Power supply - 0-30V

CIRCUIT DIAGRAM:

THEORY:

A step down converter produces a lower average output voltage than the dc input voltage. By varying the duty ratio Ton/T, the output voltage Vo can be controlled.

DESIGN:

Switching frequency, f =25kHz

Let,

input voltage, Vin = 20V

duty ratio, D = 0.3

load resistor, R = 10Ώ

Now, VO = Vin * D = 6V

inductor voltage, VL = VS-VO = Ldi/dt

IO = VO/R = 0.6A

takeΔiL= 10% of IO, ΔiL= 0.06A

ΔiL/DT= (Vin – VO)/L

L = 2.8mH, (assumed L= 2mH)

Assume voltage ripple, ΔVO/VO = 1%

ΔVO/VO = (1-D)/8LCf2

C = 50µf, (assumed C = 47 µf)

Snubber design

C = ILtf/2V

C = 0.00075 µf, assumed C = 0.001µf

5RC = 3 µs

R = 600Ώ

Experiment No: 10Design and Implementation of Boost Converter

AIM:

Design and implementation of boost converter.

COMPONENTS REQUIRED:

PWM: IC SG3525.

MOSFET.

Diode- FRD IN5408.

Inductor- 2mH.

Wirewound Resistor-10Ω,25W.

Capacitor-47µH,0.1µH.

Power Supply: 0-30V.

CIRCUIT DIAGRAM:

THEORY:

A step-up converter produces a higher average output voltage than the dc input voltage. By varying the duty ratio Ton/T, the output voltage Vo can be controlled.

DESIGN:

Switching frequency, f =25kHz

Let, Input voltage, Vin = 20VDuty ratio, D = 0.6Load resistor, R = 100Ώ

Now, VO = Vin / (1-D) = 50VInductor voltage, VL = VS-V= Ldi/dtIO= V/R = 0.6A

Take ΔiOL = 10% of IO, Δi= 0.06AΔiL/(DT) = (Vin – VOL )/LL = 2.8mH, (assumed L= 2mH)

Assume voltage ripple, ΔVO /V= 1%* (ΔVO/VO) = D/(R*C*f)

C = 50µf, (assumed C = 47 µf)Snubber designC = ILtfO /2VC = 0.00075 µf, assumed C = 0.001µf5RC = 3 µsR = 600Ώ

Experiment No: 11Design and Implementation of Buck Boost Converter

AIM:

To design and implement a Buck-boost converter and to observe the output voltage, inductor

current, switch voltage.

COMPONENTS REQUIRED:

PWM-IC SG3525

MOSFET

Diode - FRD IN5408 (3 Nos.)

Inductor – 1mH

Wire wound resistor – 22Ω/47Ω, 25W

Resistors-22 Ω,470 Ω

Capacitor – 4.7uF , 2000pF

Power supply - 0-30V

PNP Transistor- BC177

CIRCUIT DIAGRAM:

Fig 1: Circuit for generation of gate pulses

Fig 2: Circuit for Buck-Boost Converter

THEORY:

The output voltage of the buck-boost converter can be either higher or lower than the

input voltage, depending on the duty ratio of the switch. If D>0.5, the output voltage is larger

than the input; and if D<0.5, the output is smaller than the input. Therefore, this circuit combines

the capabilities of the buck and boost converters.

The source is never connected directly to the load in the buck-boost converter. Energy is

stored in the inductor when the switch is closed and transferred to the load when the switch is

open. Hence, the buck-boost converter is also referred to as an indirect converter. Polarity

reversal on the output may be a disadvantage in some applications.

The output voltage is given by: V0= -VS(D/1-D)

DESIGN:

Switching frequency, f =25kHz

Let,

input voltage, VS = 24V

duty ratio, D = 0.3

load resistor, R = 22Ώ

Inductor , L = 1mH

Now, V0= -VS(D/1-D) = 10.3V

Inductor voltage, VL = VS = Ldi/dt

I0 = V0/R = 0.468 A

IL = VSD/R(1-D)2 =0.66 A

ΔiL = VSDT/L ;ΔiL = 0.288 A

Assume voltage ripple, ΔV0/V0 = 1%

ΔV0/V0 =D/RCf

C = 5.4 µf , (assumed C = 4.7 µf)