power developer: may, 2014

May 2014

Dr. Dennis FloodNatcore Technology

Pushing the SwitchingFrequency Boundary

Power SensorCompatibility

and Natcore can lead the way.

SOLAR IS READY TO CHANGE THE WORLD,

MOVING SOLAR FORWARD:

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Power Developer CONTENTS

4 TECH ARTICLECompact Modeling Concerns for Silicon-based MOSFETs

3

To read the previous installment, click the image above.

Alex LidowCEO of Efficient Power Conversion (EPC)

In a previous column, a push to higher frequencies beyond the practical limits of silicon technology was made to showcase eGaN FET’s hard-switching performance capability and their potential implementation in applications such as envelope tracking. We gave some initial data on the higher on-resistance EPC8000 series devices. In this installment, we will discuss the device, packaging and layout changes that have been made with the EPC8000 series to improve hard-switching performance. Lastly we will discuss the in-circuit performance and the future circuit requirements to push the hard-switching frequency boundary even further.

Figure 3. The EPC8000 series WLCSP die showing bump side with pin-out locations.

Figure 2. Synchronous buck converter with parasitic inductances and their relative impact on device losses for a 12 VIN, 1.2 VOUT, 1 MHz, 20 A buck converter.

Figure 1. Synchronous buck converter with parasitic inductances and their relative impact on device.

DEVICE REQUIREMENTS FOR HARD-SWITCHING AT HIGH FREQUENCY

Driving down hard-switching losses requires not only a reduction in the device charge components, but also a minimization of circuit parasitics. Since the EPC8000 series parts are aimed at hard-switching applications, their performance can be compared using a hard-switching figure of merit (FOMHS) [1] given by:

( ) )(2 onDSGSGDHS RQQFOM ⋅+=

where QGD is the gate-to-drain Miller charge which controls the voltage rising and falling transition times, QGS2 is the gate charge between threshold and plateau voltage which controls the current rising and falling transition time, and RDS(on) is the device on-resistance.

For example, a 65 V rated EPC8005 is compared to the existing lower on-resistance 100 V EPC2007 eGaN FET, as well as state-of-the-art 30 V MOSFETS with similar on-resistances in Figure 1. The 30 V MOSFETs were used for comparison purposes only because higher voltage and comparable MOSFET device are not available. From Figure 1 it can be seen that the new EPC8005 has about half of the FOMHS of MOSFETs, while more than doubling their voltage capability. Compared to the 100V eGaN FET, the EPC8005 shows a significant (3x) reduction in QGD, thus resulting in a much improved FOMHS.

Another important hard-switching requirement is dv/dt turn-on immunity, as determined by the Miller ratio, which is an indicator of how susceptible gates are to turning back on at high dv/dt [5]. The Miller ratio (QGD/QGS1) has been reduced to below 0.4, well below the theoretical requirement of one. This means that even during extreme dv/dt transient conditions, the EPC8000 series devices are immune to false turn-on.

IMPORTANT CIRCUIT PARASITICS FOR HARD-SWITCHING AT HIGH FREQUENCY

For hard-switching half-bridge applications there are two major parasitic inductances that have a significant impact on converter performance as shown in Figure. 2. The common source inductance, LS, has been shown to be critical to performance because it directly impacts the driving speed of the devices [2], [3]. As common source inductance increases, the effective

gate drive voltage and gate drive current are significantly reduced, slowing switching speeds and increasing switching losses. Additionally, the high frequency loop inductance, LLoop, while not as penalizing to switching speeds, still negatively impacts switching performance [4]. The loop inductance is also proportional to the peak voltage overshoot and related switching losses. The relative impact of these two parasitic inductances is shown in Figure 2.

for Silicon-based Power MOSFETsPower electronics, at first brush, does not have the glamorous appeal of slick and quick digital electronics—microprocessors, microcontrollers, etc.—that we’ve come to associate with the nanotechnology revolution in the past two to three decades. Evaluated solely on the basis of process nodes and manufacturing technology, power transistors lag their digital counterparts by several years. And while cutting-edge processors allow you to talk, text, and play “Flappy Bird” all at the same time, most power electronics are still thought to fulfill one function only—a glorified ON/OFF switch!

All of that holds water only at the first brush. Dig a little deeper, and it becomes immediately apparent why power semiconductors have been attracting so much attention recently. To put things in perspective, the market size for microprocessors in 2012 was roughly $90 billion. This figure includes the revenue from chip sales across all segments—PC, embedded, servers, etc. Impressive, right? On the other hand, the estimated market size for power electronics is, yes, $90 billion! In fact, both technologists and policy-makers have identified power electronics as an investment that could enable a functioning low-carbon economy. Thus, newer applications, such as inverters in solar panel installation that convert DC to AC or battery-charge management in electric vehicles, are supplementing steady demand from traditional sources such as aeronautical and consumer applications. This has ensured that the market size for power electronics remains substantial.

Power Transiators

Power electronics are employed in broadly two engineering applications: power distribution and power conversion. While the former is still a bastion of mechanical relays and circuit breakers, it is the latter where semiconductors have made the largest dent. Power transistors in commercial manufacturing today can service demands for applications beyond 1000V! The market is wide open, with various process technologies like Silicon (Si), Gallium Nitride (GaN) and Silicon Carbide (SiC) battling it out to establish supremacy and gain market share. Figure 1 outlines the relative costs of these technologies as well as the broad voltage ranges of their usability. Out of all these contenders, only silicon technologies are mature enough to be reliably mass-produced at a very low cost. GaN and SiC, both wider band-gap materials that possess better breakdown and high-frequency characteristics than Si, are very expensive substrates to fabricate with a much lesser yield-per-wafer than Si. Thus, Si-based power devices (FETs) that are compatible with standard CMOS manufacturing are driving the power electronics

industry single-handedly, with cost, yield and reliability advantages. A majority of Si-based power electronics rely on two types of transistors that function as its workhorse: the Drain Extended MOSFET (DEMOS) and the Lateral Double-Diffused MOSFET (LDMOS). Mask reuse within standard CMOS manufacturing ensures DEMOS and LDMOS transistors can be fabricated “on the side” without additional costly processing steps. In a particular process node, while the scaled CMOS components are used in digital and high-performance analog circuit design (products in critical timing or signal paths, etc.), DEMOS and LDMOS transistors find extensive usage in switching power converter applications. These applications include switched DC-DC converters that convert sources of direct current from one voltage level to another, where the key benchmarks are maximizing power conversion efficiency and minimizing switching losses.

For comparison, highly simplified cross-sections of n-channel CMOS, DEMOS and LDMOS transistors are shown in Figure 2. At their simplest, power FETs such as DEMOS and LDMOS can be thought of as a conventional MOSFET (both n- or p-channel) with an extended drain region under the polysilicon gate. In DEMOS devices, the NWELL creates the lightly doped drain extension region, which allows for greater depletion on the NWELL side and a shorter channel length. The DEMOS channel region looks exactly like a CMOS channel, but is usually longer for greater process tolerances and punch-through resistance due to the higher operating voltages. In LDMOS devices, the body (p+) and source (n+) are shorted together via a process known as double-diffusion (hence the name!). LDMOS devices, which really are types of specialized DEMOS devices, are optimized for a shorter channel region to give them superb linear resistance and higher gains compared to DEMOS. While DEMOS usage tends toward high-voltage, low-current applications, LDMOS can be used in high-voltage, high-current applications. Both transistors, however, do not make good high-speed analog and digital circuit components due to extended geometry features.

COMPACT MODELING CONCERNS

Silicon Carbide• Highest performance

advantage (breakdown/temp)

• Most expensive

Silicon• Low cost• Best yield• Reliable

Gallium Nitride• Expensive epitaxial manufacturing

• Better DC/RF performance than Si

200 V 800 V

Voltage

Co

st

P Well

N WellP Well

GateSource Drain

GateSource Drain

N+ N+

N+ N+

LEFF

LOVLEFF

LG

P+ Sub

P+ Sub

(a) Regular CMOS

(b) DEMOS

(c) LDMOSN Well

P Well

GateSourceBody +

Axis ofsymmetry

Drain

N+N+P+LOV

LEFF

P+ Sub

Figure 1: Cost of manufacturing vs. usable voltage ranges for contending semiconductor materials vying for the power electronics market share.

Figure 2: Comparison of the simplified cross-sections of CMOS, DEMOS5 and LDMOS6 transistors

Transient EMI arises when the source emits a short duration pulse of energy rather than a continuous signal. Sources include switching electrical circuitry, e.g., inductive loads such as relays, solenoids and electric motors. Other sources are electrostatic discharge (ESD), lightning, nuclear and nonnuclear electromagnetic pulse weapons, and power line surges. Repetitive transient EMI can be caused by electric motors, gasoline engine ignition systems and continuous digital circuit switching.

EMI COUPLINGCoupling can occur through conduction via an unwanted path (a so-called “sneak circuit”), through induction (as in a transformer), and radiated or through-the-air coupling.

Conductive coupling occurs when the coupling path between the source and the receptor is formed by direct contact. Direct contact may be caused by a transmission line, wire, cable, PCB trace or metal enclosure. Conducted noise can appear in a common or differential mode on two conductors.

Differential mode noise results from a differential mode current in a two wire pair. The differential mode current is the expected current on the two wire pair, i.e., current leaves at the source end of the line and comes back on the return side of the line. The noise is measured on each line with respect to a designated reference point. The resultant measurement would be the difference in the noise on the two lines. Differential mode currents flow between the switching supply and its source or load via the power leads and

these currents are independent of ground. Consequently no differential mode current flows through ground.

Common mode noise is caused by a common mode current. In this case noise current flows along both the outgoing lines in the same direction and returns by some parasitic path through system ground that is not part of the design, the so-called “sneak circuit” discussed earlier. In many cases, common mode noise is conducted through parasitic capacitance in the circuit. Common mode currents flow in the same direction in or out of the switching supply via the power leads and return to their source through ground. Common mode currents will also flow through the capacitance formed between the case and ground.

Conducted EMI emissions are measured up to 30 MHz. Currents at frequencies below 5 MHz are mostly differential mode, while those above 5 MHz are usually common mode.

Inductive coupling occurs where the source and receptor are separated by a short distance. Inductive coupling can be due to electrical induction or magnetic induction. Electrical induction results from capacitive coupling while magnetic induction is caused by inductive coupling. Capacitive coupling occurs when a varying electric field exists between two adjacent conductors, inducing a change in voltage across the gap. Magnetic coupling occurs when a varying magnetic field exists between two parallel conductors, inducing a change in voltage along the receiving conductor. Inductive coupling is rare relative to conductive or radiated coupling.

Radiated coupling occurs when source and receptor (victim) act as radio antennas. The source radiates an electromagnetic wave which propagates across the open space between the source and the victim and is received by the victim.

Characterization of the EMI problem requires understanding the interference source and signal, the coupling path to the victim and the nature of the victim, both electrically and in terms of the significance of the malfunction. The risk posed by the threat is usually statistical in nature; so much of the work in threat characterization and standards setting is based on reducing the probability of disruptive EMI to an acceptable level rather than its assured elimination.

EMI requirements, both radiated and conductive, apply to an overall electronic system. Power modules are one of many components within a system. Since the EMI requirements apply to the overall system, significant effort must be expended on system design to limit noise. Most electronic equipment has only one interface with the power source, which is through the power supply. If adequate EMI filters are inserted between the power supply and the power source, conducted emissions from the power module can be sufficiently suppressed to meet the FCC or CISPR limits without any of the power modules meeting the EMC standard as a standalone component. However, it should be noted that switching power supplies in standalone applications, typically in the form of external power adapters, are required to operate below the conducted EMI limits.

“With external power supplies, the entire system needs to be tested, even if the

power adapter is in compliance with the

regulations.”

Figure 3: Definition of differential and common mode current http://www.cui.com/

10 TECH COLUMNHow to GaN: Pushing the Hard-Switching Frequency

Boundary with EPC8000 series eGaN® FETs

16 TECH ARTICLEElectromagnetic Compatibility Considerations

for Switching Power Supplies, Part 1

24 COVER ARTICLENatcore’s Groundbreaking New Process Boosts

Solar Efficiency, at a Significantly Lower Cost

3. Handheld RF Signal Analyzer/Cableand Antenna Tester Connecting a USB power sensor to a handheld RF signal analyzer or a cable and antenna tester gives the instrument power meter functionalities. Just like any other power meter, the USB power sensor can perform zeroing or configure the measurement setup such as frequency and averaging. Users can even change the measurement display from default meter mode to chart format.

5. Vector Network Analyzer (ENA)The ENA vector network analyzer has a frequency offset mode (FOM) option used to measure the frequency converter device accurately. The “offset” of source and receiver port frequency can be defined precisely. The receiver port can detect the down-converter or up-converter signal. There are limitations to using FOM to measure the frequency converter device. First, the local oscillator (LO) signal of the device under test (DUT) has to be known and locked to the source or receiver port frequency of a

Figure 8. The UI of a handheld RF signal analyzer when operating in power meter mode

Figure 11. USB power sensor as a “broadband power detector” versus LO frequency drifts

Figure 10. IFBW versus LO frequency drift in FOM mode

Figure 9. Source power calibration connection diagram for a vector network analyzer with 1) a power meter and power sensor, and 2) a USB power sensor

network analyzer. Otherwise, the difference between the predicted intermediate frequency (IF) signal and actual IF signal is directly converted to a magnitude error because of the intermediate frequency bandwidth (IFBW) filter shape implemented in these network analyzers.

IFBW is set to 1 kHz, and the 3 dB bandwidth of the IFBW filter is approximately 1 kHz. If the actual output frequency of the DUT has an offset of 500 Hz (=BW/2) from target frequency, the magnitude result has a 3 dB error. When the output signal drifts, the measurement results change at the same time.

You can overcome the limitation of FOM by using the USB power sensor (with network analyzer VBA) as a “broadband power detector” (see figure 11). The USB power sensor is used to measure all power in its bandwidth, and the measurement result is stable and unaffected by output signal offset or drift (see Figure 10).

USB power sensors are compact and portable, easy

to use and cost effective.

When a USB power sensor is connected

directly to these instruments, it

can be powered up to perform

the instrument’s specific application.

4. Vector Network Analyzer(PNA/PNA-X/PNA-L)With source power calibration, the power at a certain point is calibrated to be within the range of the uncertainty of the power meter and power sensor. Traditionally, the source power calibration is performed through GPIB connectivity and supported by a power meter and a power sensor (see Figure 9). This solution requires a big space for storing the power meter and sensor in the production test, along with considerable expenses to acquire a power meter and power sensor just for source power calibration purposes.Today, USB power sensors offer a solution that is integrated with the vector network analyzer. The USB power sensor is used to replace both the power meter and power sensor (see Figure 8) in the source power calibration process. It provides a direct connection into the vector network analyzer’s USB port via USB plug-and-play connectivity. Throughout the source power calibration process, the vector network analyzer can be configured to detect the power meter (via GPIB) or USB power sensor (via USB) from the power meter setting of the vector network analyzer.

32 TECH ARTICLECompatibility of USB Power Sensors with

Other Electronic Measurement Instruments

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Power Transiators







• Most expensive




200 V 800 V

Voltage

Co

st

P Well

N WellP Well

GateSource Drain

GateSource Drain

N+ N+

N+ N+

LEFF

LOVLEFF

LG

P+ Sub

P+ Sub

(a) Regular CMOS

(b) DEMOS

(c) LDMOSN Well

P Well

GateSourceBody +

Axis ofsymmetry

Drain

N+N+P+LOV

LEFF

P+ Sub



5

TECH ARTICLE

555



Power Transiators







• Most expensive




200 V 800 V

Voltage

Co

st

P Well

N WellP Well

GateSource Drain

GateSource Drain

N+ N+

N+ N+

LEFF

LOVLEFF

LG

P+ Sub

P+ Sub

(a) Regular CMOS

(b) DEMOS

(c) LDMOSN Well

P Well

GateSourceBody +

Axis ofsymmetry

Drain

N+N+P+LOV

LEFF

P+ Sub



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Compact Modeling Concerns

Before a design can be committed to silicon, circuit and system designers use compact models to simulate, iterate, and re-simulate their designs in EDA tools till they achieve the desired level of specifications. These models are empirical or semi-numerical representations of various active and passive devices like transistors, resistors, diodes, capacitors, etc. Compact models accurately describe the electrical characteristics (e.g. dc, ac, cv across temperature) of a particular process technology, thereby providing an essential link between circuit and systems design on one hand and foundries on the other hand.

Table 1 lists the device performance metrics, as well as the specific compact modeling foci, for both high-speed CMOS and power transistors. As illustrated, power FETs have some unique physical and modeling-related benchmarks not shared with high-speed CMOS devices. Generally, power devices employ a “subcircuit-based compact model” approach, which employs the classic BSIM3 or BSIM4 CMOS compact model at its core with additional components wrapped around it to model electrical characteristics, as shown in Figure 3. The external drain and source resistor models enable modeling the unique device physics of the extended drain/source for asymmetric/symmetric power transistors. Additional components may be utilized to capture electrical effects crucial only to power technologies, as described.

Since power FETs are primarily used in power conversion circuits such as buck-boost converters where transistors switch inductive loads, it becomes essential for designers to see the compact model “in action” to evaluate conversion losses with a high degree of accuracy. Charging of the gate and drain and the switching losses related to the FET channel resistance, two very important metrics to evaluate the losses, are described next. Figure 4 is a typical switching circuit that also describes the setup to measure and model gate-charge in power FETs. At a fixed VDD, an independent constant current source IG is applied to the gate, which starts charging the gate capacitances. The current equation in the setup is described by: where CGG is the total gate capacitance. Figure 5 shows a typical gate-charge curve. Initially in region

R1, no current flows from drain to source since VGS < Vth (FET threshold voltage); hence the drain to source voltage VDS is clamped at VDD, which makes the second term negligible in the above expression. Thus, IG charges CGG (primarily CGS) and VGS increases linearly in region R1 till it equals Vth. At this point, the channel is inverted and a constant current IDS starts to flow. VDS drops quickly causing VGS to be fixed and thereby making the first term in the expression above negligible. In region R2, IG charges CGD primarily. CGD is a highly nonlinear function of VDS, i.e. CGD increases with decreasing VDS. Hence, dVDS/dt increases to keep IG constant in region R2 as per above expression. In region R3, VDS settles to a small, constant value of RON*IDS, and again the second term of the expression becomes negligible. In region R3, IG continues

Device Design Performance Metrics

Digital (high-speed scaled) CMOS Power (DEMOS, LDMOS) FETs

Key Compact Modeling Metrics

Best Compact Models

• Maximizing switching speed• Minimizing off-state leakage• Minimizing device-to-device mismatch• Minimizing dynamic power dissipation

• Low channel resistance (On-state)• High source-to-drain breakdown voltage• Low stored gate charge (Qg)

• I/O capacitances• IGate + ISubstrate• Mismatch modeling• Short channel effects

• Gate + Drain charging• Modeling extended drift region resistance• Diode reverse recovery charges• High voltage parasitics modeling

• BSIM3/4/6• PSP

• BSIM3/4 with external subcircuits• HiSIMHV• PSP-HV• MM20

Table 1: Comparison of device performance metrics and compact modeling metrics for digital and power transistors.

Source

Drain

Gate

External DrainResistor

External SourceResistor

Source DrainDiode with QRRControl Circuit

Core BSIM3

Figure 3: Simplified subcircuit-based compact model for power transistors.

Figure 4: An inductive-load switching circuit used to measure and simulate gate and drain charging in power FETs

iDS DZL

RG

CDS

CGS

CGD

IG

ID

VDD

7

TECH ARTICLE

777

Compact Modeling Concerns

Before a design can be committed to silicon, circuit and system designers use compact models to simulate, iterate, and re-simulate their designs in EDA tools till they achieve the desired level of specifications. These models are empirical or semi-numerical representations of various active and passive devices like transistors, resistors, diodes, capacitors, etc. Compact models accurately describe the electrical characteristics (e.g. dc, ac, cv across temperature) of a particular process technology, thereby providing an essential link between circuit and systems design on one hand and foundries on the other hand.

Table 1 lists the device performance metrics, as well as the specific compact modeling foci, for both high-speed CMOS and power transistors. As illustrated, power FETs have some unique physical and modeling-related benchmarks not shared with high-speed CMOS devices. Generally, power devices employ a “subcircuit-based compact model” approach, which employs the classic BSIM3 or BSIM4 CMOS compact model at its core with additional components wrapped around it to model electrical characteristics, as shown in Figure 3. The external drain and source resistor models enable modeling the unique device physics of the extended drain/source for asymmetric/symmetric power transistors. Additional components may be utilized to capture electrical effects crucial only to power technologies, as described.

Since power FETs are primarily used in power conversion circuits such as buck-boost converters where transistors switch inductive loads, it becomes essential for designers to see the compact model “in action” to evaluate conversion losses with a high degree of accuracy. Charging of the gate and drain and the switching losses related to the FET channel resistance, two very important metrics to evaluate the losses, are described next. Figure 4 is a typical switching circuit that also describes the setup to measure and model gate-charge in power FETs. At a fixed VDD, an independent constant current source IG is applied to the gate, which starts charging the gate capacitances. The current equation in the setup is described by: where CGG is the total gate capacitance. Figure 5 shows a typical gate-charge curve. Initially in region

R1, no current flows from drain to source since VGS < Vth (FET threshold voltage); hence the drain to source voltage VDS is clamped at VDD, which makes the second term negligible in the above expression. Thus, IG charges CGG (primarily CGS) and VGS increases linearly in region R1 till it equals Vth. At this point, the channel is inverted and a constant current IDS starts to flow. VDS drops quickly causing VGS to be fixed and thereby making the first term in the expression above negligible. In region R2, IG charges CGD primarily. CGD is a highly nonlinear function of VDS, i.e. CGD increases with decreasing VDS. Hence, dVDS/dt increases to keep IG constant in region R2 as per above expression. In region R3, VDS settles to a small, constant value of RON*IDS, and again the second term of the expression becomes negligible. In region R3, IG continues

Device Design Performance Metrics

Digital (high-speed scaled) CMOS Power (DEMOS, LDMOS) FETs

Key Compact Modeling Metrics

Best Compact Models

• Maximizing switching speed• Minimizing off-state leakage• Minimizing device-to-device mismatch• Minimizing dynamic power dissipation

• Low channel resistance (On-state)• High source-to-drain breakdown voltage• Low stored gate charge (Qg)

• I/O capacitances• IGate + ISubstrate• Mismatch modeling• Short channel effects

• Gate + Drain charging• Modeling extended drift region resistance• Diode reverse recovery charges• High voltage parasitics modeling

• BSIM3/4/6• PSP

• BSIM3/4 with external subcircuits• HiSIMHV• PSP-HV• MM20

Table 1: Comparison of device performance metrics and compact modeling metrics for digital and power transistors.

Source

Drain

Gate

External DrainResistor

External SourceResistor

Source DrainDiode with QRRControl Circuit

Core BSIM3

Figure 3: Simplified subcircuit-based compact model for power transistors.

Figure 4: An inductive-load switching circuit used to measure and simulate gate and drain charging in power FETs

iDS DZL

RG

CDS

CGS

CGD

IG

ID

VDD

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to charge CGS (although at a much slower rate than R1) until a maximum compliance voltage of VGSmax is reached in the measurement setup. Thus, a model capturing gate and drain charging with high fidelity in power FETs is absolutely essential for designing power circuits! To enable such a compact model, it is necessary to not only model the internal capacitances perfectly, but also the internal channel resistance as well as associated interconnect parasitics. In fact, the product of gate charge and On-state resistance (QG*RDS(ON)) is a key figure of merit for power FETs performance.

Next, modeling the channel resistance as well as the extended-drain resistance in power FETs is very crucial, since these resistances determine FET switching losses. Usually, a two-terminal (2T) resistance model with only Ohm’s Law as its underlying physics is used in the subcircuit-based compact model for power FETs, as was shown in Figure 3. However, such a simplistic resistor representation is unable to capture higher-order I-V effects, particularly in a diffused resistor as implemented in power FETs. To remedy the modeling limitations of a 2T model, many three-terminal, (3T) and four-terminal (4T) resistor (or historically, JFET) models have been proposed in literature. These multi-terminal resistor models vitally improve the electrical modeling of the extended drain in DEMOS and LDMOS transistors by incorporating various complex forms of bias dependence. These include the depletion pinching of the conduction-channel of the resistor from velocity saturation, and also from self-heating effects. A type of 3T model, as shown in Figure 6, is the R3 model supported by the Compact Modeling Council, which has seen immense buy-in from multiple foundries. Since the formulations within the R3 model also capture resistor scalability in length and width, bias between resistor terminals and terminal-to-substrate, as well as temperature effects and noise modeling, it is a perfect substitute for 2T resistor models in power FETs.

Another key compact modeling metric unique to power FETs is the drain-to-body (D-B) diode reverse-recovery, or QRR, since it is pertinent to high-efficiency power converter design,. The diode QRR allows designers to estimate not

Meas.Sim.

Vth

Meas.Sim.

VG

SV

DS

VON

IDS

VDD

Time(s)

Time(s)

R2 R3R1

Figure 5: A Typical power FET gate-charge curve with various regions (R1, R2, R3) of operation.

Figure 6: Recent power FET compact models have made the transition from a 2-terminal to a 3-terminal resistor model equivalent network.

Figure 7: The D-B diode (red) that conducts when the LS-LDMOS turns off in a power converter.

Figure 8: Modeling of Drain-Body diode reverse recovery in LDMOS FETs.

n1 n2

n1 n2

nc

Cp1 Cp2

i2n

Ip1 Ip2

Re1 Re2i1 i2

only its switching losses but also its maximum switching frequency. As shown in Figure 7, the D-B diode conducts when the low-side LDMOS in a power-switching circuit driving inductive loads turns off. Since a conducting diode stores minority carrier charges, they need to be dissipated completely before the diode can be turned off. This diode recovers only when the high-side LDMOS (not shown) in the power-conversion circuit turns on again, and in this process, up to 2-3 percent loss in power conversion efficiency can be suffered. This can be the difference between a market-leading chip and another also-ran! To account for these “hidden” recovery losses, compact models must be able to accurately capture QRR in power FETs. In Figure 8, a measured D-B diode QRR trace overlaid with a compact model simulation is shown. The D-B diode does not shut off instantaneously (like an ideal switch in the figure) when the high-side LDMOS turns ON in a converter circuit15. To recover, it

dissipates charges by conducting current in the opposite direction for a considerable time (up to many tens of nanoseconds) to return to a non-conducting state. Modeling the diode recovery accurately in power FETs is the best means to predict switching losses (grey area under the recovery curve in Figure 8) in power converters and is crucial to a first-pass circuit design success. Thus, while the process engineer strives to successfully scale D-B diodes in power FETs with process nodes shrinking, the compact modeling engineer ensures that the QRR artifact, unique to power FETs, is captured in a simulation environment.

The compact modeling criteria discussed thus far are unique to power FETs. In addition, since power FETs operate at high drain-source voltages and high currents, modeling of transistor reliability, ageing, and hot carrier degradation become major concerns. Other physical effects not unique to power FETs, but

Drain

Gate

Source/Body

p+n+ n+

BODY +SOURCE

GATE

DRAIN

Low-side LDMOS

crucial nonetheless from a compact modeling perspective, are transistor self-heating and parasitic BJT effects caused by the substrate. In summary, modeling a silicon-based power FET is no less resource-intensive and technically challenging than its faster, small cousin the digital FET! Conclusion

Understanding the underlying physics behind silicon-based power FETs and capturing this physics in analytical compact models used in circuit design is critical to enable first-pass circuit design success in power electronics, which is almost a $90 billion market. Thus, for a rapid Release-To-Manufacturing and reduced product cycle times, high quality SPICE compact models accurately representing the electrical characteristics of power FETs must be used. In this article, we explored some of the unique and interesting challenges encountered specifically while making compact models for silicon-based power FETs. With increasing demands on power converter efficiency, semiconductor device scaling, and novel applications that demand ever-increasing operating voltages, it becomes an ever evolving art to create compact models for these devices.

Power Loss

Ideal Switch

OFFON

Meas.Sim.

Time(s)

Dio

de

Cur

rent

9

TECH ARTICLE

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to charge CGS (although at a much slower rate than R1) until a maximum compliance voltage of VGSmax is reached in the measurement setup. Thus, a model capturing gate and drain charging with high fidelity in power FETs is absolutely essential for designing power circuits! To enable such a compact model, it is necessary to not only model the internal capacitances perfectly, but also the internal channel resistance as well as associated interconnect parasitics. In fact, the product of gate charge and On-state resistance (QG*RDS(ON)) is a key figure of merit for power FETs performance.

Next, modeling the channel resistance as well as the extended-drain resistance in power FETs is very crucial, since these resistances determine FET switching losses. Usually, a two-terminal (2T) resistance model with only Ohm’s Law as its underlying physics is used in the subcircuit-based compact model for power FETs, as was shown in Figure 3. However, such a simplistic resistor representation is unable to capture higher-order I-V effects, particularly in a diffused resistor as implemented in power FETs. To remedy the modeling limitations of a 2T model, many three-terminal, (3T) and four-terminal (4T) resistor (or historically, JFET) models have been proposed in literature. These multi-terminal resistor models vitally improve the electrical modeling of the extended drain in DEMOS and LDMOS transistors by incorporating various complex forms of bias dependence. These include the depletion pinching of the conduction-channel of the resistor from velocity saturation, and also from self-heating effects. A type of 3T model, as shown in Figure 6, is the R3 model supported by the Compact Modeling Council, which has seen immense buy-in from multiple foundries. Since the formulations within the R3 model also capture resistor scalability in length and width, bias between resistor terminals and terminal-to-substrate, as well as temperature effects and noise modeling, it is a perfect substitute for 2T resistor models in power FETs.

Another key compact modeling metric unique to power FETs is the drain-to-body (D-B) diode reverse-recovery, or QRR, since it is pertinent to high-efficiency power converter design,. The diode QRR allows designers to estimate not

Meas.Sim.

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Figure 5: A Typical power FET gate-charge curve with various regions (R1, R2, R3) of operation.

Figure 6: Recent power FET compact models have made the transition from a 2-terminal to a 3-terminal resistor model equivalent network.

Figure 7: The D-B diode (red) that conducts when the LS-LDMOS turns off in a power converter.

Figure 8: Modeling of Drain-Body diode reverse recovery in LDMOS FETs.

n1 n2

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nc

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only its switching losses but also its maximum switching frequency. As shown in Figure 7, the D-B diode conducts when the low-side LDMOS in a power-switching circuit driving inductive loads turns off. Since a conducting diode stores minority carrier charges, they need to be dissipated completely before the diode can be turned off. This diode recovers only when the high-side LDMOS (not shown) in the power-conversion circuit turns on again, and in this process, up to 2-3 percent loss in power conversion efficiency can be suffered. This can be the difference between a market-leading chip and another also-ran! To account for these “hidden” recovery losses, compact models must be able to accurately capture QRR in power FETs. In Figure 8, a measured D-B diode QRR trace overlaid with a compact model simulation is shown. The D-B diode does not shut off instantaneously (like an ideal switch in the figure) when the high-side LDMOS turns ON in a converter circuit15. To recover, it

dissipates charges by conducting current in the opposite direction for a considerable time (up to many tens of nanoseconds) to return to a non-conducting state. Modeling the diode recovery accurately in power FETs is the best means to predict switching losses (grey area under the recovery curve in Figure 8) in power converters and is crucial to a first-pass circuit design success. Thus, while the process engineer strives to successfully scale D-B diodes in power FETs with process nodes shrinking, the compact modeling engineer ensures that the QRR artifact, unique to power FETs, is captured in a simulation environment.

The compact modeling criteria discussed thus far are unique to power FETs. In addition, since power FETs operate at high drain-source voltages and high currents, modeling of transistor reliability, ageing, and hot carrier degradation become major concerns. Other physical effects not unique to power FETs, but

Drain

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p+n+ n+

BODY +SOURCE

GATE

DRAIN

Low-side LDMOS

crucial nonetheless from a compact modeling perspective, are transistor self-heating and parasitic BJT effects caused by the substrate. In summary, modeling a silicon-based power FET is no less resource-intensive and technically challenging than its faster, small cousin the digital FET! Conclusion

Understanding the underlying physics behind silicon-based power FETs and capturing this physics in analytical compact models used in circuit design is critical to enable first-pass circuit design success in power electronics, which is almost a $90 billion market. Thus, for a rapid Release-To-Manufacturing and reduced product cycle times, high quality SPICE compact models accurately representing the electrical characteristics of power FETs must be used. In this article, we explored some of the unique and interesting challenges encountered specifically while making compact models for silicon-based power FETs. With increasing demands on power converter efficiency, semiconductor device scaling, and novel applications that demand ever-increasing operating voltages, it becomes an ever evolving art to create compact models for these devices.

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http://issuu.com/eeweb/docs/power_developer_-_intersil/19?e=7607911/7484233

http://epc-co.com/epc/documents/briefs/eGaN%20FET%20Product%20Brief_MultMegahertz%20Switching.pdf

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Apart from having significant improvements in device characteristics, the EPC8000 FETs also have a number of layout and device pin-out improvements to minimize the above mentioned parasitic inductances. Referring to Figure 3, these can be summarized as follows:

» The separate source connection for the gate drive circuit limits the common source inductance to inside the device itself. This reduction in common source inductance is critical to high frequency switching performance as it reduces the impact of QGS2 on overall switching losses.

» The wider connections for the gate circuit connection significantly reduce the inductance of the connection to the gate circuit. Furthermore, by placing the gate and separate gate return terminals parallel to each other allow for low inductance PCB interconnection to the driver by routing

both through wide conductors on adjacent PCB layers as shown in Figure 4, following an optimum loop inductance layout as developed for the power loop inductance [4].

» As with the gate drive connections above, parallel connection pads allow wide interconnection traces for improved PCB layout with minimized power loop inductance. The orthogonal layout of these two loops also reduces the inter-action of the gate circuit current with the drain circuit current.

The suggested half-bridge layout in Figure 4 shows both gate loop and power loop currents (arrows) flow in opposite directions on adjacent layers to help reduce the overall loop inductances through flux cancellation [4]. Furthermore, these traces are kept as wide as possible while the interlayer distance between these layers is minimized, both of which will further reduce loop inductance.

eGaN is a registered trademark of Efficient Power Conversion Corporation.

[1] D. Reusch, J. Strydom, and A. Lidow, “Improving System Performance with eGaN® FETs in DC-DC Applications,” International Microelectronics Assembly and Packaging Society (IMAPS), pp.764-769, 2013.

[2] B. Yang, J. Zhang, “Effect and utilization of common source inductance in synchronous rectification,” Applied Power Electronics Conference and Exposition (APEC), pp. 1407–1411, 2005.

[3] M. Pavier, A. Woodworth, A. Sawle, R. Monteiro, C. Blake, and J. Chiu, “Understanding the effect of power MOSFET package parasitic on VRM circuit efficiency at frequencies above 1 MHz,” PCIM Europe, pp. 279–284, 2003

[4] D. Reusch, J. Strydom, “Understanding the Effect of PCB Layout on Circuit Performance in a High Frequency Gallium Nitride Based Point of Load Converter,” Applied Power Electronics Conference (APEC), pp.649-655, 2013.

[5] T. Wu, “Cdv/dt induced turn-on in synchronous buck regulators,” white paper, International Rectifier Corporation, 2007.

[6] J. Strydom, D. Reusch, “Design and Evaluation of a 10 MHz Gallium Nitride Based 42 V DC-DC Converter,” Applied Power Electronics Conference (APEC), pp.1510-1516, 2014.

EXPERIMENTAL RESULTS

The initial experimental results were good, showing a peak efficiency of about 89% for a 42 VIN to 20 VOUT, 10 MHz, 2 A converter. However, subsequent loss analyses [6] show that a significant portion of the overall circuit losses can be attributed to the parasitics of the gate driver, most notably the bootstrap diode reverse recovery and the internal driver (well) capacitance. Improvements in the silicon driver would allow for even higher efficiencies, as shown in Figure 5.

SUMMARY

The introduction of a new family of high performance enhancement mode eGaN FETs offers the potential to switch at higher frequencies with higher efficiency than possible with traditional Si MOSFET technology. Combined with an improved switching figure of merit and low parasitic packaging the new devices also have an optimized device pin-out to minimize parasitic PCB layout inductance. This allows designer to more fully utilize the device’s capabilities.

Analysis of the overall circuit losses have shown the silicon gate driver to be responsible for about half of the overall light-load converter losses, and is effectively reducing the light load efficiency by more than 10 percentage points. To fully utilize the capability of the high frequency, reduced size eGaN FETs will require a significant improvement in the gate driver structure. This will enable a significant increase in efficiency and switching frequency capability.

a. Top (component) layer

b. First inner layer

Figure 4. Optimal layout design for a half-bridge topology using an EPC8000 series device. (a) top (component) layer and (b) first inner layer.

Figure 5. Loss break-down on a 42 VIN to 20 VOUT, 10 MHz, 2 A buck converter (top) and efficiency (bottom, dashed lines) and calculated values based on improvements in driver capacitance, bootstrap diode recovery (bottom, solid lines).

http://www.eeweb.com/blog/alex_lidow/how-to-gan-driving-egan-fets-and-layout-considerations

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Apart from having significant improvements in device characteristics, the EPC8000 FETs also have a number of layout and device pin-out improvements to minimize the above mentioned parasitic inductances. Referring to Figure 3, these can be summarized as follows:

» The separate source connection for the gate drive circuit limits the common source inductance to inside the device itself. This reduction in common source inductance is critical to high frequency switching performance as it reduces the impact of QGS2 on overall switching losses.

» The wider connections for the gate circuit connection significantly reduce the inductance of the connection to the gate circuit. Furthermore, by placing the gate and separate gate return terminals parallel to each other allow for low inductance PCB interconnection to the driver by routing

both through wide conductors on adjacent PCB layers as shown in Figure 4, following an optimum loop inductance layout as developed for the power loop inductance [4].

» As with the gate drive connections above, parallel connection pads allow wide interconnection traces for improved PCB layout with minimized power loop inductance. The orthogonal layout of these two loops also reduces the inter-action of the gate circuit current with the drain circuit current.

The suggested half-bridge layout in Figure 4 shows both gate loop and power loop currents (arrows) flow in opposite directions on adjacent layers to help reduce the overall loop inductances through flux cancellation [4]. Furthermore, these traces are kept as wide as possible while the interlayer distance between these layers is minimized, both of which will further reduce loop inductance.

eGaN is a registered trademark of Efficient Power Conversion Corporation.

[1] D. Reusch, J. Strydom, and A. Lidow, “Improving System Performance with eGaN® FETs in DC-DC Applications,” International Microelectronics Assembly and Packaging Society (IMAPS), pp.764-769, 2013.

[2] B. Yang, J. Zhang, “Effect and utilization of common source inductance in synchronous rectification,” Applied Power Electronics Conference and Exposition (APEC), pp. 1407–1411, 2005.

[3] M. Pavier, A. Woodworth, A. Sawle, R. Monteiro, C. Blake, and J. Chiu, “Understanding the effect of power MOSFET package parasitic on VRM circuit efficiency at frequencies above 1 MHz,” PCIM Europe, pp. 279–284, 2003

[4] D. Reusch, J. Strydom, “Understanding the Effect of PCB Layout on Circuit Performance in a High Frequency Gallium Nitride Based Point of Load Converter,” Applied Power Electronics Conference (APEC), pp.649-655, 2013.

[5] T. Wu, “Cdv/dt induced turn-on in synchronous buck regulators,” white paper, International Rectifier Corporation, 2007.

[6] J. Strydom, D. Reusch, “Design and Evaluation of a 10 MHz Gallium Nitride Based 42 V DC-DC Converter,” Applied Power Electronics Conference (APEC), pp.1510-1516, 2014.

EXPERIMENTAL RESULTS

The initial experimental results were good, showing a peak efficiency of about 89% for a 42 VIN to 20 VOUT, 10 MHz, 2 A converter. However, subsequent loss analyses [6] show that a significant portion of the overall circuit losses can be attributed to the parasitics of the gate driver, most notably the bootstrap diode reverse recovery and the internal driver (well) capacitance. Improvements in the silicon driver would allow for even higher efficiencies, as shown in Figure 5.

SUMMARY

The introduction of a new family of high performance enhancement mode eGaN FETs offers the potential to switch at higher frequencies with higher efficiency than possible with traditional Si MOSFET technology. Combined with an improved switching figure of merit and low parasitic packaging the new devices also have an optimized device pin-out to minimize parasitic PCB layout inductance. This allows designer to more fully utilize the device’s capabilities.

Analysis of the overall circuit losses have shown the silicon gate driver to be responsible for about half of the overall light-load converter losses, and is effectively reducing the light load efficiency by more than 10 percentage points. To fully utilize the capability of the high frequency, reduced size eGaN FETs will require a significant improvement in the gate driver structure. This will enable a significant increase in efficiency and switching frequency capability.

a. Top (component) layer

b. First inner layer

Figure 4. Optimal layout design for a half-bridge topology using an EPC8000 series device. (a) top (component) layer and (b) first inner layer.

Figure 5. Loss break-down on a 42 VIN to 20 VOUT, 10 MHz, 2 A buck converter (top) and efficiency (bottom, dashed lines) and calculated values based on improvements in driver capacitance, bootstrap diode recovery (bottom, solid lines).

http://www.eeweb.com/blog/alex_lidow/how-to-gan-egan-fets-for-high-frequency-switching

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Switching Power SuppliesCharacterization of the EMI problem requires understanding the interference source

Switching power supplies generate Electromagnetic Interference (EMI) by virtue of their inherent design characteristics. Internal

switching power supply circuits that generate undesirable emissions that are rich in harmonics can cause electrical interference both internally to the circuit in which the power supply is installed and to other electronic equipment in the vicinity of the emission source.

Considerations for

Part 1

Electromagnetic Compatibility

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Switching Power SuppliesCharacterization of the EMI problem requires understanding the interference source

Switching power supplies generate Electromagnetic Interference (EMI) by virtue of their inherent design characteristics. Internal

switching power supply circuits that generate undesirable emissions that are rich in harmonics can cause electrical interference both internally to the circuit in which the power supply is installed and to other electronic equipment in the vicinity of the emission source.

Considerations for

Part 1

Electromagnetic Compatibility

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The FCC further categorizes digital electronic equipment into Class A (designated for use in a commercial, industrial, or business environment excluding residential use or use by the general public) and Class B (designated for use in a residential environment notwithstanding use in commercial, business and industrial environments). Examples of Class B devices are personal computers, calculators, and similar devices for use by the general public. Emission standards are more restrictive for Class B devices since they are more likely to be located close to other electronic devices used in the home.

INTERNATIONAL STANDARDSA standard widely used in the European Community is the Third Edition of the International Special Committee on Radio Interference (CISPR), Pub. 22, “Information Technology Equipment—Radio Disturbance Characteristics—Limits and Methods of Measurement,” issued in 1997. This standard is better known as simply CISPR 22. Unlike the FCC which regulates electromagnetic interference in the United States, CISPR is a standards organization without regulatory authority. However, CISPR standards have been adopted for use by most members of the European Community.

CISPR 22 also differentiates between Class A and Class B devices and establishes conducted and radiated emissions for each class. In addition, CISPR 22 requires certification over the frequency range of 0.15 MHz to 30 MHz for conducted emissions (Recall that the FCC range starts at 0.45 MHz).

STANDARDS HARMONIZATIONThe FCC Part 15 rules and the requirements of CISPR 22 have been harmonized and either standard, with minor exceptions, can be used to certify digital electronic equipment. Harmonization requires that the same standard be used for both conducted and

INTRODUCTIONThis application note examines the rules and regulations governing control of EMI, discusses types of noise generated by switching power supplies, and provides basic guidance for EMI mitigation, whether the power supply is installed in other equipment as part of a larger system or designed for stand-alone applications.

LAWS, REGULATION, AND INTERNATIONAL COOPERATIONThe electromagnetic spectrum has been widely used for broadcasting, telecom and data communications through intentional emissions of electromagnetic fields. There have also been unintentional emissions from many electrical and electronic equipment, such as arc welding machines, household appliances and computer equipment. In order to protect the electromagnetic spectrum and to ensure compatibility of collocated electrical and electronic systems from trouble free operations, regulatory bodies both within the United States and throughout the world community have established standards to control conducted and radiated electromagnetic interference in electronic equipment. This discussion mainly focuses on unintentional electromagnetic compatibility in systems that utilize switching power supplies.

UNITED STATES STANDARDSIn the United States the government agency responsible for regulating communications is the Federal Communications Commission (FCC). Control of electromagnetic interference is outlined in Part 15 of the FCC rules and

regulations. FCC rules decree that any spurious signal greater than 10 KHz be subject to these regulations. The FCC further specifies the frequency bands in which these spurious emissions must be controlled according to the type of emission. Radiated emissions, i.e., those radiated and coupled through the air, must be controlled between 30 MHz and 1000 MHz. Conducted emissions, i.e., those RF signals contained within the ac power bus, must be controlled in the frequency band between 0.45 MHz and 30 MHz.

Figure 2: CISPR fi strength limits for conducted and radiated emissions.*Decreases with the logarithm of the frequency

Figure 1: FCC field strength limits for conducted and radiated emissions.

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The FCC further categorizes digital electronic equipment into Class A (designated for use in a commercial, industrial, or business environment excluding residential use or use by the general public) and Class B (designated for use in a residential environment notwithstanding use in commercial, business and industrial environments). Examples of Class B devices are personal computers, calculators, and similar devices for use by the general public. Emission standards are more restrictive for Class B devices since they are more likely to be located close to other electronic devices used in the home.

INTERNATIONAL STANDARDSA standard widely used in the European Community is the Third Edition of the International Special Committee on Radio Interference (CISPR), Pub. 22, “Information Technology Equipment—Radio Disturbance Characteristics—Limits and Methods of Measurement,” issued in 1997. This standard is better known as simply CISPR 22. Unlike the FCC which regulates electromagnetic interference in the United States, CISPR is a standards organization without regulatory authority. However, CISPR standards have been adopted for use by most members of the European Community.

CISPR 22 also differentiates between Class A and Class B devices and establishes conducted and radiated emissions for each class. In addition, CISPR 22 requires certification over the frequency range of 0.15 MHz to 30 MHz for conducted emissions (Recall that the FCC range starts at 0.45 MHz).

STANDARDS HARMONIZATIONThe FCC Part 15 rules and the requirements of CISPR 22 have been harmonized and either standard, with minor exceptions, can be used to certify digital electronic equipment. Harmonization requires that the same standard be used for both conducted and

INTRODUCTIONThis application note examines the rules and regulations governing control of EMI, discusses types of noise generated by switching power supplies, and provides basic guidance for EMI mitigation, whether the power supply is installed in other equipment as part of a larger system or designed for stand-alone applications.

LAWS, REGULATION, AND INTERNATIONAL COOPERATIONThe electromagnetic spectrum has been widely used for broadcasting, telecom and data communications through intentional emissions of electromagnetic fields. There have also been unintentional emissions from many electrical and electronic equipment, such as arc welding machines, household appliances and computer equipment. In order to protect the electromagnetic spectrum and to ensure compatibility of collocated electrical and electronic systems from trouble free operations, regulatory bodies both within the United States and throughout the world community have established standards to control conducted and radiated electromagnetic interference in electronic equipment. This discussion mainly focuses on unintentional electromagnetic compatibility in systems that utilize switching power supplies.

UNITED STATES STANDARDSIn the United States the government agency responsible for regulating communications is the Federal Communications Commission (FCC). Control of electromagnetic interference is outlined in Part 15 of the FCC rules and

regulations. FCC rules decree that any spurious signal greater than 10 KHz be subject to these regulations. The FCC further specifies the frequency bands in which these spurious emissions must be controlled according to the type of emission. Radiated emissions, i.e., those radiated and coupled through the air, must be controlled between 30 MHz and 1000 MHz. Conducted emissions, i.e., those RF signals contained within the ac power bus, must be controlled in the frequency band between 0.45 MHz and 30 MHz.

Figure 2: CISPR fi strength limits for conducted and radiated emissions.*Decreases with the logarithm of the frequency

Figure 1: FCC field strength limits for conducted and radiated emissions.

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radiated emissions. Measurements made above 1000 MHz must be made in accordance with FCC rules and limits since CISPR 22 has no specified limits for frequencies above 1000 MHz. Conducted and radiated emission limits specified in FCC Part 15 and CISPR 22 are within a few dB of each other over the prescribed frequencies, so using either set of limits does not compromise accuracy of the measurement and certification process. FCC limits are given in μV and CISPR limits are given in dBμV, so conversion of the units for one set of limits is necessary for direct comparison.

SWITCHING POWER SUPPLIESAND EMC STANDARDS“Switching power supply” is a generic term that describes a power source that uses a circuit to convert a dc voltage to an ac voltage that can be further processed to become another dc voltage. Switching power supplies can be further categorized as ac-dc power supplies (ac input) and dc-dc converters (dc input) since both incorporate dc to ac conversion for voltage change. By virtue of their inherent design characteristics, switching power supplies generate electromagnetic interference composed of signals of multiple frequencies. The dc-dc converter converts the input dc voltage to an ac voltage that can be stepped up or down via a transformer. Ac-dc power supplies also utilize high frequency circuits for voltage conversion.

However, the internal ac voltage in either case is not a pure sine wave but frequently a square wave which can be represented by a Fourier series that consists of the algebraic sum of

many sine waves with harmonically-related frequencies. These multiple- frequency signals are the source of conducted and radiated emissions which can cause interference to both the equipment in which the switching power supply is installed and to nearby equipment which may be susceptible to these frequencies.

Switching power supplies generate EMI which is subject to FCC and CISPR regulations. Since Class A electronic equipment is marketed for use in a commercial, industrial, or business environment, and Class B electronic equipment is marketed for use in a residential environment, emission limits for Class B equipment, which is likely to be located in close proximity to radio and television receivers, are therefore more restrictive than Class A. In general Class B limits are more restrictive than Class A by a factor of 3 (~10 dB). FCC conducted emission limits are specified for frequency ranges of 0.45-1.6 MHz and 1.6-30 MHz. FCC radiated emission limits are specified for frequency ranges of 30-88 MHz, 88- 216 MHz, and 216-1000 MHz at a fixed measuring distance of 3 meters. These limits apply to both systems with embedded power supplies installed and in stand-alone applications where switching power supplies are utilized.

EMC TESTING AND COMPLIANCEEMC testing and compliance is performed according to the test procedure defined in ANSI C63.4-2009 “Methods of Measurement of Radio-Noise Emissions from Low-Voltage Electrical and Electronic Equipment in the Range of 9 kHz to 40 GHz”. This ANSI Standard

does not include either generic or specific product-related limits on conducted and radiated emissions. These limits are specified in the FCC and CISPR documents discussed above. It is worth noting that testing is done with the entire system, not just the power module, especially with embedded power modules. With external power supplies (as in standalone power adapters), the entire system needs to be tested, even if the power adapter is in compliance with the regulations.

EMI/EMC FUNDAMENTALS, SOURCES AND ASSOCIATED FREQUENCIESEMI cases generally include a source of interference, a path that couples the EMI to other circuits, and a target referred to as the “victim” whose performance is degraded by the source EMI. The damaging effects of EMI pose unacceptable risks in many different

technologies, thus making it necessary to control EMI at its source or reduce the risk of exposure to EMI to acceptable levels at the victim.

EMI can first be categorized as continuous interference as opposed to transient interference. Continuous interference occurs when the source emits an uninterrupted signal composed of the source’s fundamental frequency and associated harmonics. Continuous interference can be further subdivided by frequency band. Frequencies from a few Hz up to 20 KHz are classified as audio. Sources of audio interference include power supply hum and associated wiring, transmission lines and substations, audio processing equipment such as audio power amplifiers and loudspeakers, and demodulation of high frequency carrier waves such as those seen in FM radio transmission.

Radio Frequency Interference (RFI) occurs in a frequency band from 20 kHz to a constantly increasing limit defined by advancing technology. Sources of RFI include wireless and radio frequency transmissions, television and radio receivers, industrial, scientific and medical equipment, and high frequency circuit signals such as those in microprocessors, microcontrollers, and other high speed digital equipment.

Broadband noise, consisting of signals of multiple frequencies, may be spread across parts of both frequency ranges. Sources of broadband noise include solar activity, continuously operating spark gaps such as arc welders, and CDMA mobile telephony.

“By virtue of their inherent design characteristics,

switching power supplies generate electromagnetic

interference composed of signals of multiple

frequencies.”

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radiated emissions. Measurements made above 1000 MHz must be made in accordance with FCC rules and limits since CISPR 22 has no specified limits for frequencies above 1000 MHz. Conducted and radiated emission limits specified in FCC Part 15 and CISPR 22 are within a few dB of each other over the prescribed frequencies, so using either set of limits does not compromise accuracy of the measurement and certification process. FCC limits are given in μV and CISPR limits are given in dBμV, so conversion of the units for one set of limits is necessary for direct comparison.

SWITCHING POWER SUPPLIESAND EMC STANDARDS“Switching power supply” is a generic term that describes a power source that uses a circuit to convert a dc voltage to an ac voltage that can be further processed to become another dc voltage. Switching power supplies can be further categorized as ac-dc power supplies (ac input) and dc-dc converters (dc input) since both incorporate dc to ac conversion for voltage change. By virtue of their inherent design characteristics, switching power supplies generate electromagnetic interference composed of signals of multiple frequencies. The dc-dc converter converts the input dc voltage to an ac voltage that can be stepped up or down via a transformer. Ac-dc power supplies also utilize high frequency circuits for voltage conversion.

However, the internal ac voltage in either case is not a pure sine wave but frequently a square wave which can be represented by a Fourier series that consists of the algebraic sum of

many sine waves with harmonically-related frequencies. These multiple- frequency signals are the source of conducted and radiated emissions which can cause interference to both the equipment in which the switching power supply is installed and to nearby equipment which may be susceptible to these frequencies.

Switching power supplies generate EMI which is subject to FCC and CISPR regulations. Since Class A electronic equipment is marketed for use in a commercial, industrial, or business environment, and Class B electronic equipment is marketed for use in a residential environment, emission limits for Class B equipment, which is likely to be located in close proximity to radio and television receivers, are therefore more restrictive than Class A. In general Class B limits are more restrictive than Class A by a factor of 3 (~10 dB). FCC conducted emission limits are specified for frequency ranges of 0.45-1.6 MHz and 1.6-30 MHz. FCC radiated emission limits are specified for frequency ranges of 30-88 MHz, 88- 216 MHz, and 216-1000 MHz at a fixed measuring distance of 3 meters. These limits apply to both systems with embedded power supplies installed and in stand-alone applications where switching power supplies are utilized.

EMC TESTING AND COMPLIANCEEMC testing and compliance is performed according to the test procedure defined in ANSI C63.4-2009 “Methods of Measurement of Radio-Noise Emissions from Low-Voltage Electrical and Electronic Equipment in the Range of 9 kHz to 40 GHz”. This ANSI Standard

does not include either generic or specific product-related limits on conducted and radiated emissions. These limits are specified in the FCC and CISPR documents discussed above. It is worth noting that testing is done with the entire system, not just the power module, especially with embedded power modules. With external power supplies (as in standalone power adapters), the entire system needs to be tested, even if the power adapter is in compliance with the regulations.

EMI/EMC FUNDAMENTALS, SOURCES AND ASSOCIATED FREQUENCIESEMI cases generally include a source of interference, a path that couples the EMI to other circuits, and a target referred to as the “victim” whose performance is degraded by the source EMI. The damaging effects of EMI pose unacceptable risks in many different

technologies, thus making it necessary to control EMI at its source or reduce the risk of exposure to EMI to acceptable levels at the victim.

EMI can first be categorized as continuous interference as opposed to transient interference. Continuous interference occurs when the source emits an uninterrupted signal composed of the source’s fundamental frequency and associated harmonics. Continuous interference can be further subdivided by frequency band. Frequencies from a few Hz up to 20 KHz are classified as audio. Sources of audio interference include power supply hum and associated wiring, transmission lines and substations, audio processing equipment such as audio power amplifiers and loudspeakers, and demodulation of high frequency carrier waves such as those seen in FM radio transmission.

Radio Frequency Interference (RFI) occurs in a frequency band from 20 kHz to a constantly increasing limit defined by advancing technology. Sources of RFI include wireless and radio frequency transmissions, television and radio receivers, industrial, scientific and medical equipment, and high frequency circuit signals such as those in microprocessors, microcontrollers, and other high speed digital equipment.

Broadband noise, consisting of signals of multiple frequencies, may be spread across parts of both frequency ranges. Sources of broadband noise include solar activity, continuously operating spark gaps such as arc welders, and CDMA mobile telephony.

“By virtue of their inherent design characteristics,

switching power supplies generate electromagnetic

interference composed of signals of multiple

frequencies.”

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FWA3 3W DIP $10FWA5 5W DIP $14FQ6 6W DIP $18

FWA10 10W DIP $24FWA15 15W 1” x 2” $32

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READY TO LAUNCH

For the launch of the Tiva C Series Connected LaunchPad, TI has partnered with Exosite, mentioned briefly above, to provide easy access to the LaunchPad from the Internet. The LaunchPad takes about 10 minutes to set up and you can immediately interact with it across the Internet and do things like turn an LED on and off remotely from the website and see the reported temperature as well. It can also display approximate geographic location based on the assigned IP address and display a map of all other connected LaunchPad owners if they are active and plugged-in to Exosite. “In addition, it supports a basic game by enabling someone to interface to the Connected LaunchPad through a serial port from a terminal while someone else is playing with them through their browser. It is basically showing how you can interact remotely with this product and a user even if you are across the globe,” Folkens explained.

START DEVELOPING

The Tiva C Series Connected LaunchPad is shipping now and the price is right; at $19.99 USD, it is less than half the price of other Ethernet-ready kits. The LaunchPad comes complete with quick start and user guides, and ample online support to ensure developers of all backgrounds are well equipped to begin creating cloud-based applications. “We have assembled an online support team to monitor the Engineering-to-Engineering (or E2E) Community,” Folkens said. “Along with this, you also got a free Code Composer Studio Integrated Development Environment, which allows developers to use the full capability. We also support other tool chains like Keil, IAR and Mentor Embedded.

Affordable, versatile, and easy to use, the Tiva Series Connected LaunchPad is well suited for a broad audience and promises to facilitate the expansion of ingenious IoT applications in the cloud. As Folkens concluded, “The target audiences actually are the hobbyists, students and professional engineers. A better way of looking at it is that we are targeting people with innovative ideas and trying to help them get those ideas launched into the cloud.”

http://www.beta-dyne.com

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TECH ARTICLE

31intersil.com

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3232

Power Developer

Compatibility of

with Other Electronic Measurement InstrumentsBy Chin Aik Lee, Agilent Technologies, Inc.

Traditional power measurement methodologies use a power meter and power sensor setup, and often require other instruments such as a

spectrum wanalyzer, vector network analyzer, or signal generator. This situation increases the cost of a test system significantly. USB power sensors can be used as an accessory for other electronic measurement instruments, allowing these instruments to perform specific power measurement applications without needing to connect to a PC or laptop. This article explains how a USB power sensor, together with a vector network analyzer, is able to perform the source power calibration scalar analysis of a frequency converter. The USB power sensors are compatible with the Agilent FieldFox handheld RF and microwave analyzers, handheld signal analyzer and signal generator, giving them power meter functionalities; they also allow the signal generator to perform user flatness correction with external leveling.

USB Power Sensors

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TECH ARTICLE

33

Compatibility of

with Other Electronic Measurement InstrumentsBy Chin Aik Lee, Agilent Technologies, Inc.

Traditional power measurement methodologies use a power meter and power sensor setup, and often require other instruments such as a

spectrum wanalyzer, vector network analyzer, or signal generator. This situation increases the cost of a test system significantly. USB power sensors can be used as an accessory for other electronic measurement instruments, allowing these instruments to perform specific power measurement applications without needing to connect to a PC or laptop. This article explains how a USB power sensor, together with a vector network analyzer, is able to perform the source power calibration scalar analysis of a frequency converter. The USB power sensors are compatible with the Agilent FieldFox handheld RF and microwave analyzers, handheld signal analyzer and signal generator, giving them power meter functionalities; they also allow the signal generator to perform user flatness correction with external leveling.

USB Power Sensors

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Power Developer

USB POWER SENSORS SOLUTION

Making accurate power measurements require both a power meter and a power sensor. The power sensor converts the RF signal and microwave signal into analog signals. Subsequently, the power meter performs the statistical processing and displays the results in decimal/trace format. USB power sensors are standalone instruments that combine power meter and power sensor functionalities, making them an affordable solution for power measurement. Using a USB cable, power measurement results can be displayed and analyzed through a power measurement Windows-based software application on a PC or laptop. The power measurement readings are retrieved using standard SCPI commands or IVI-COM/IVI-C drivers. The SCPI-based command set provides a user-friendly programming environment and allows users to program test software to retrieve the power measurement.

USB POWER SENSOR’S COMPATIBILITY WITH OTHER INSTRUMENTS

USB power sensors are compatible with other instruments such as the vector network analyzer, signal analyzer, signal generator, cable and antenna tester and FieldFox handheld RF and microwave analyzers (Figure 1). When a USB power sensor is connected directly to these instruments, it can be powered up to perform the instrument’s specific application. Each compatible instrument has built-in firmware to support the USB power sensor, unless it specifically requires a Windows-based software application or Visual Basic Assistant (VBA) application.

Following is a list of the compatible instruments, with descriptions of their functions when used with a USB power sensor:

Vector Network Analyzer (PNA/PNA-X/PNA-L)• Performs source power calibration and

provides the output power to measure gain compression, intermodulation distortion, and other device parameters accurately

Vector Network Analyzer (ENA)• Performs scalar analysis of a frequency

converter, which requires the VBA application

Signal Generator (EXG/MXG) • Performs user flatness correction with

external leveling • Turns the instrument into a power meter • Displays power measurement with

its built-in user interface (UI), which integrates the display of USB power sensor measurements

• Supports and displays two USB power sensor measurements on the signal generator display

Handheld RF Signal Analyzer/Cable and Antenna Tester• Turns the instrument into a power meter • Displays power measurements with its

built-in UI, which integrates the display of USB power sensor measurements

FieldFox Handheld RF and Microwave Analyzers• Turns the instrument into a power meter • Displays power measurement with its

built-in UI • Supports average and peak power

measurements under free run mode, as well as pulse measurement under continuous mode

Signal Analyzer (EXA/MXA/PXA)• Displays the power measurement on

the signal analyzer with Windows-based software application

Figure 1. Instruments that are compatible with USB power sensors

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TECH ARTICLE

35

USB POWER SENSORS SOLUTION

Making accurate power measurements require both a power meter and a power sensor. The power sensor converts the RF signal and microwave signal into analog signals. Subsequently, the power meter performs the statistical processing and displays the results in decimal/trace format. USB power sensors are standalone instruments that combine power meter and power sensor functionalities, making them an affordable solution for power measurement. Using a USB cable, power measurement results can be displayed and analyzed through a power measurement Windows-based software application on a PC or laptop. The power measurement readings are retrieved using standard SCPI commands or IVI-COM/IVI-C drivers. The SCPI-based command set provides a user-friendly programming environment and allows users to program test software to retrieve the power measurement.

USB POWER SENSOR’S COMPATIBILITY WITH OTHER INSTRUMENTS

USB power sensors are compatible with other instruments such as the vector network analyzer, signal analyzer, signal generator, cable and antenna tester and FieldFox handheld RF and microwave analyzers (Figure 1). When a USB power sensor is connected directly to these instruments, it can be powered up to perform the instrument’s specific application. Each compatible instrument has built-in firmware to support the USB power sensor, unless it specifically requires a Windows-based software application or Visual Basic Assistant (VBA) application.

Following is a list of the compatible instruments, with descriptions of their functions when used with a USB power sensor:

Vector Network Analyzer (PNA/PNA-X/PNA-L)• Performs source power calibration and

provides the output power to measure gain compression, intermodulation distortion, and other device parameters accurately

Vector Network Analyzer (ENA)• Performs scalar analysis of a frequency

converter, which requires the VBA application

Signal Generator (EXG/MXG) • Performs user flatness correction with

external leveling • Turns the instrument into a power meter • Displays power measurement with

its built-in user interface (UI), which integrates the display of USB power sensor measurements

• Supports and displays two USB power sensor measurements on the signal generator display

Handheld RF Signal Analyzer/Cable and Antenna Tester• Turns the instrument into a power meter • Displays power measurements with its

built-in UI, which integrates the display of USB power sensor measurements

FieldFox Handheld RF and Microwave Analyzers• Turns the instrument into a power meter • Displays power measurement with its

built-in UI • Supports average and peak power

measurements under free run mode, as well as pulse measurement under continuous mode

Signal Analyzer (EXA/MXA/PXA)• Displays the power measurement on

the signal analyzer with Windows-based software application

Figure 1. Instruments that are compatible with USB power sensors

3636

Power Developer

start and stop frequency and the number of frequency points to be corrected. The setup function thus will observe the difference between measured power and calibrated power. The correction factors of the UFC process are shown in Figure 5.

The dual power meter display function can be used to display the current frequency and average power of either one or two USB power sensors (See Figure 6 & Figure 7). For each channel, users can control the settings for On/Off, channel frequency, channel offset, averaging and measurement units, and the dual power meter display feature.

HOW DOES IT WORK?

1. FieldFox Handheld RFand Microwave Analyzers FieldFox handheld RF and microwave analyzers come with a built-in UI to support

USB power sensors. Once the USB power sensor is connected to the RF analyzer, users can switch the

instrument to power meter mode and display power readings on its screen. Users are able to provide the minimum configuration of power measurements such as frequency, averaging, single/

continuous measurement, detection mode, zeroing, and display units measurement through

the UI. FieldFox handheld RF and microwave analyzers can also perform average and peak power measurements with specific USB power sensor models.

2. Signal Generator (EXG/MXG)User flatness correction (UFC) with external leveling provides the ability to have extremely flat output power at the testing interface beyond the signal generator RF output connector. If an external device (such as amplifier, attenuator, coupler, detector, divider or long cable) is placed between the RF output connector and the testing interface, it will introduce additional gain or loss as well as frequency response mismatch to the whole system. Therefore it is necessary to perform the UFC with external leveling to remove this type of influence. In this case, the USB power sensor offers a solution integrated with the signal generator. The USB power sensor is directly connected to the signal generator’s front panel USB port (see Figure 4). Power measurements can then be received through SCPI commands, providing remote programing functions. The signal generator’s built-in UFC features allow users to configure the calibration array, the

Figure 2. The FieldFox handheld RF and microwave analyzer’s power meter measurement UI

Figure 3. Pulse measurement mode display, using a USB peak and average power sensor to measure the RF pulse signal

Figure 4. Connection diagram of a USB power sensor and a signal generator for UFC external leveling

Figure 6. Connection diagram of two USB power sensors and a signal generator

Figure 5. Correction factors are automatically performed and displayed on the signal generator

Figure 7. Dual power meter display function on a signal generator

USB power sensors are standalone

instruments that combine

power meter and power sensor

functionalities, making them an affordable

solution for power measurement.

37

TECH ARTICLE

37

start and stop frequency and the number of frequency points to be corrected. The setup function thus will observe the difference between measured power and calibrated power. The correction factors of the UFC process are shown in Figure 5.

The dual power meter display function can be used to display the current frequency and average power of either one or two USB power sensors (See Figure 6 & Figure 7). For each channel, users can control the settings for On/Off, channel frequency, channel offset, averaging and measurement units, and the dual power meter display feature.

HOW DOES IT WORK?

1. FieldFox Handheld RFand Microwave Analyzers FieldFox handheld RF and microwave analyzers come with a built-in UI to support

USB power sensors. Once the USB power sensor is connected to the RF analyzer, users can switch the

instrument to power meter mode and display power readings on its screen. Users are able to provide the minimum configuration of power measurements such as frequency, averaging, single/

continuous measurement, detection mode, zeroing, and display units measurement through

the UI. FieldFox handheld RF and microwave analyzers can also perform average and peak power measurements with specific USB power sensor models.

2. Signal Generator (EXG/MXG)User flatness correction (UFC) with external leveling provides the ability to have extremely flat output power at the testing interface beyond the signal generator RF output connector. If an external device (such as amplifier, attenuator, coupler, detector, divider or long cable) is placed between the RF output connector and the testing interface, it will introduce additional gain or loss as well as frequency response mismatch to the whole system. Therefore it is necessary to perform the UFC with external leveling to remove this type of influence. In this case, the USB power sensor offers a solution integrated with the signal generator. The USB power sensor is directly connected to the signal generator’s front panel USB port (see Figure 4). Power measurements can then be received through SCPI commands, providing remote programing functions. The signal generator’s built-in UFC features allow users to configure the calibration array, the

Figure 2. The FieldFox handheld RF and microwave analyzer’s power meter measurement UI

Figure 3. Pulse measurement mode display, using a USB peak and average power sensor to measure the RF pulse signal

Figure 4. Connection diagram of a USB power sensor and a signal generator for UFC external leveling

Figure 6. Connection diagram of two USB power sensors and a signal generator

Figure 5. Correction factors are automatically performed and displayed on the signal generator

Figure 7. Dual power meter display function on a signal generator

USB power sensors are standalone

instruments that combine

power meter and power sensor

functionalities, making them an affordable

solution for power measurement.

3838

Power Developer

















39

TECH ARTICLE

39

















4040

Power Developer

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Figure 12 and Figure 13 show the measurement result of “locked” and “drifted” LO signal by FOM mode (see the blue trace) and USB power sensor (see the red trace) respectively. The measurement result of the USB power sensor shows that it has good correlation with the FOM result at “locked” signal, and is stable with the “drifted” LO signal.

CONCLUSION

USB power sensors are compact and portable, easy to use and cost effective. They provide the following benefits: • Compatibility with other instruments

such as vector network analyzer, signal analyzer, signal generator, cable and antenna tester, and FieldFox handheld RF and microwave analyzers.

• Portability for field application: the smaller size and light weight of the USB power sensors allows users to carry them to the site for field applications.

• Simplified measurement setup with USB power: plug-and-play connectivity, and built-in triggering circuit.

• Lower cost without compromising on performance/quality: standalone USB power sensors do not need a power meter to provide accurate power measurement.

Figure 12. Measurement results with “Locked” LO (RF power versus IF power)

Figure 13. Measurement results with “Drifted” LO (RF power sensor IF power)

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Development, Cree, Inc.

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