power forward initiative: cadence product support status...
TRANSCRIPT
INV
EN
TIV
E
Cadence Low Power Solution Overview
Koorosh NazifiEngineering Group DirectorJune 8, 2008
June 17, 20082
Agenda
• Cadence low power solution overview
• User-driven and production ready
• Broad industry support
June 17, 20083
Cadence Low Power Solution
• Enables power exploration and architecture selection early-on
• Entire design flow understands and preserves the power-intent
• Production proven CPF enabled low power solution with broad industry support
June 17, 20084
Cadence CPF Enabled Power-Aware Flow
including PSO patterns.
Synthesis + Pwr Est.
Design for Test
IR drop/power Sign-Off
RTLTest
benchMSMV, PSO,SRPG, MMMC,DVFS, AON,
gate(1)
gate(2)
LEC
& C
LP C
heck
s
CPF
CPF Quality Checker
Logic Simulation
Implementationgate(3)
Timing/ SI Sign-Off
Plan & Metrics
RTL SimulationICE & DUV
Timing-driven Sim
FV
June 17, 20085
Low-power methodology kit makes MSV/PSO adoption easier
• Covers all aspects of digital implementation• Well documented requirements, checklists, and best practices• Supported by low power design experts
Des
ign
Envi
ronm
ent
Infra
stru
ctur
e, P
roce
ss s
elec
tion,
Libr
ary
Qua
lific
atio
n
PhysicalImplementation
Prototyping, parasitics,
floorplanning, timing, and SI closure
VerificationFunctional,
implementation,power grid
signoff Man
agem
ent
Plan
ning
, met
rics,
EC
O
Low-Power TechniquesMultiple voltage thresholds, low power clocking
multiple supply voltages, power shut-off
DesignCreation
Architecture, RTL, CPF,synthesis, DFT
INV
EN
TIV
E
Quick Glimpse of the Cadence LP Solution
June 17, 20087
Incisive vManager
Complete Low Power Solution
Incisive SimulationEncounter RTL CompilerSoC EncounterEncounter TestVoltageStormConformal Low Power
June 17, 20088
Hierarchical CPF for soft IP
Hierarchical CPF for hard IP Mapping child
domains intoparent domains
Advanced Power Intent described by CPF
Nested power domains
June 17, 20089
Test bench: Powering up and down a
block
Verification Test Bench
June 17, 200810
Verification Plan
Verification plan includes power
verification
June 17, 200811
Incisive vManager
Reports power failure
June 17, 200812
Power down control
sequence
Clock Stops
Internal signals go to “x”
Power Down Simulation
External signals are isolated
June 17, 200813
Power Up Simulation
Power up control
sequenceClock is restored
Internal signals are restored
Isolation is removed
June 17, 200814
Power down control
sequence
Clock is still running
Assertion Failure
Failed Power Down Simulation
June 17, 200815
Failed Power Down Simulation
Power up control
sequence
Internal registers are NOT restored
Assertion failure for the outputs
June 17, 200816
Simvision Power Browser
Light bulbsindicate domain
status
Rapid debugging
of domains andstate retention
June 17, 200817
Incisive Low Power Verification
No Changes to RTL
No Changes to Testbench
No Custom Libraries
No Custom PLI
June 17, 200818
Automatic Isolation Insertion
Encounter RTL Compiler
June 17, 200819
AutomaticLevel Shifter
Insertion
Encounter RTL Compiler
June 17, 200820
RTL does not have retention registers
Retention cell synthesized by RCas defined in CPF
Encounter RTL Compiler
June 17, 200821
True top down simultaneousmulti-mode, multi-library multi-domain
synthesis
RAM at 0.72v
Domain Aware SynthesisMode Aware Synthesis
DTFM_INST in PDdefault
RAM in PDram
DTFM_INST at 0.72vDTFM_INST at 0.81v
Encounter RTL Compiler
June 17, 200822
Domains are highlighted
Power connections and LS/Isolation rules are automatically generated
SoC Encounter
June 17, 200823
Level shifters and isolation cells are automatically placed
SoC Encounter
June 17, 200824
CTS is Power Domain Aware
Single entry point for clock
June 17, 200825
All The Routes Are Within A Power Domain
June 17, 200826
Encounter TestCPF Data file is
read intoEncounter Test
Test Modes arebuilt for eachPower Mode
PMdvfs1_off
PMdvfs1
June 17, 200827
Encounter Test
Power domainscan be tested in
a powered up stateor in a powered
down state
June 17, 200828
Encounter Test
write_toggle_gramdoes analysis ontest sequences to
determine the levelof activity
and averages activityacross the window
Averages activityacross the scan chain
June 17, 200829
Conformal Low Power
Signal from high to low voltage is missing level shifter
The netlist was modifiedto insert errors
June 17, 200830
Missing Isolation Cells Traced to RTL…
The netlist was modifiedto insert errors
June 17, 200831
And to Schematics
The netlist was modifiedto insert errors
June 17, 200832
Complete Low Power Solution
3 Minutes
7 Products
1 CPF Specification
June 17, 200833
Agenda
• Cadence low power solution overview
• User-driven and production ready
• Broad industry support
June 17, 200834
Power Forward Initiative 28 companies across the design chain
June 17, 200835
User Driven and Production Validated Through Technical Collaborations
2H20072Q2007 1Q200745nm Reference Flow 8.0
65nm Common Platform Flow
65nm EII test chip tape-out
PRIDE Flow
EnergyPro Technology
GPG chip tape-out
90nm 1176 IEM test chip TO
ASIC RDF & 65nm flow validation
ASIC RDF & 90nm test chip tape-out
65nm LPS flow validation
1H2008 PSO/retention 65nm Flow validation
RF for ARM 11 MPCore & 1176 JZF-S processors
65nm Library certified
65nm test chip TO
45nm test chip TO
Anonymous45nm test chip TOAnonymous
Anonymous
40nm ReferenceFlow 9.0
45nm Common Platform Flow
2H2008
June 17, 200836
NEC – Productivity Improvements• NECEL Mobile Platform production design• Incisive Design Team Simulator (IDTS) + CPF :
– NECEL can reduce testbench up to 1/60 (2400 lines vs. 40 lines)
Source: NECEL presentation at EDSF 2008
Test bench
2360 LineReduction
June 17, 200837
Power Forward low-power platform SoC results
• CPF-based functional verification (using IUS) catches system level power issues early in the flow
• Using virtual power domains have demonstrated 2X productivity improvement
• SoC consists of 11 islands • 3 major power consumers -RISC
CPU, VLIW DSP & L2 System Cache are controlled using DVFS
• High bandwidth expansion ports enable extension, with graphics or cellular modem subsystems
June 17, 200838
Low Power Project
• Graphic chip design– Adopted a CPF-enabled low
power solution for their next generation graphics chip
• Key benefits1. RTL + CPF is the golden
reference for low power intent 2. Conformal Low Power as
golden verification tool throughout the design flow
3. Top-down hierarchical CPF generation automatically created block level CPF files for a 22 power domain design
‘CPF/RTL’
DFT
Formal Verification
CDS Tools Signoff Analysis
(Timing/SI/PI)
Netlist
Netlist
FloorplanPowerplanNetlist
Placement TimingOpt
Netlist
Clock TreeNetlist
TimingOptNetlist
RoutingNetlist
TimingOptSI Opt
Netlist
RTL Compiler & 3rd party
3rd party
First Encounter
PhysOpt3rd party
FE-CTS
PhysOpt3rd party
NanoRoute
PhysOpt3rd party
3rd party
Conformal LP/EC
Synthesis
3rd party, IUS (LP)SimulationAnonymous
June 17, 200839
Low Power Solution Customer Success
MYSOURCECOMMUNICATIONS
InnovativeSystems
80+ advanced LP tapeouts completed
June 17, 200840
Sample CPF Tapeouts
ApplicationProcess
nodeLow power Techniques
65nm PSO, DVFS
PSO, DVFS
MSV, PSO
PSO
MSV, PSO, DVFS
MSV, PSO
PSO
MSV, PSO
MSV, PSO
MSV, PSO
PSO
PSO
PSO
MSV, PSO
PSO, DVFS
PSO, DVFS
PSO
MSV
MSV, PSO
MSV, PSO
90nm
90nm
130nm
90nm
90nm
90nm
65nm
90nm
65nm
90nm
45nm
90nm
90nm
65nm
65nm
90nm
90nm
90nm
90nm
Tools in the FlowMobile Platform IUS/RC/CLP/SOCE
Mobile Platform IUS/RC/ CLP
GPS IES/ DC/ SOCE
RFID application SOCE
Transportation SOCE
Application specific SOCE
Application specific SOCE
Application specific IUS/RC/CLP/SOCE
Mobile GPS RC/ SOCE/ CLP
Platform specific SOCE
Processor platform IUS/RC/CLP/SOCE
Reference design flow IUS/RC/CLP/SOCE
Application specific IUS/RC/CLP/SOCE
Mobile IUS/RC/CLP/SOCE
Multi-CPU chip IUS/RC/CLP/SOCE
Processor core IUS/RC/CLP/SOCE
GPS chip SOCE/ CLP
Application specific SOCE/ CLP
Transportation chip SOCE
WiFi design platform IUS/RC/CLP/SOCE
June 17, 200841
Agenda
• Cadence low power solution overview
• User-driven and production ready
• Broad industry support
June 17, 200842
Broad Ecosystem for CPF enabled LP Solution
ASIC / Design
Services
IP VendorSupport
EDAIntegration
FoundryReference
Flows
Early Adopters
SMTSMC Reference Flow 9.0
Reference Flow 9.0 -Cadence Low Power - CPF Track
CPF Integration & Quality CheckConformal Low Power
CPF Integration & Quality CheckConformal Low Power
Gate-Level LP Simulation & LP Auto Assertion Generation / Checks
Incisive Enterprise Simulator
Gate-Level LP Simulation & LP Auto Assertion Generation / Checks
Incisive Enterprise Simulator
RTL LP Simulation & LP Auto Assertion Generation / Checks
Incisive Enterprise Simulator
RTL LP Simulation & LP Auto Assertion Generation / Checks
Incisive Enterprise Simulator
Timing & SI signoffEncounter Timing SystemTiming & SI signoff
Encounter Timing System
PD-Aware Physical ImplementationSoC Encounter
PD-Aware Physical ImplementationSoC Encounter
IR drop & Power signoffVoltageStorm-PE & DG
IR drop & Power signoffVoltageStorm-PE & DG
PD-Aware Logic Synthesis & DFTEncounter RTL Compiler
PD-Aware Logic Synthesis & DFTEncounter RTL Compiler LEC
+ Power C
hecksC
onformal Low
Pow
erLEC
+ Power C
hecksC
onformal Low
Pow
erPower-Aware ATPGEncounter Test
Power-Aware ATPGEncounter Test
DVFS Timing-Driven LP SimulationIncisive Enterprise Simulator
DVFS Timing-Driven LP SimulationIncisive Enterprise Simulator
CPF
CPF
CPF enabled bottom-up hierarchical flow for IP reusePower shutoff with support for both balloon style and master/slave retention logicsAutomated always-on feedthrough supportSwitchable memory macro with and without retentionSelective IO pad shutoff supportDVFS support
June 17, 200844
Cadence Low Power Solution
• Entire flow understands and preserves the power intent– delivering efficiency and increased productivity
• Closed loop system – LP intent verified throughout flow with Conformal Low Power (CLP)
• Silicon Proven• Flexible & open – full flow adoption not required