power management techniques for socs andrew byrne linh dinh ece260c may 29, 2014
TRANSCRIPT
Overview
Need for Power Management on SoCs Circuit Level Power Management Techniques
Multi-Threshold Power Gating Clock Gating Voltage Scaling
Hardware/Software Power Management Co-Design Drawbacks of Hardware-only Solutions Hardware/Software Power Management Module
Commercial Application
Need for Power Management
Mobile Demand Battery life a key performance specification which can provide a
competitive edge Allows for reduction in battery size, which results in a decrease in
overall system size Operating Costs
Power consumption is still a factor for non-mobile systems Thermal Requirements
Power management helps with system cooling requirements
Source: Cisco VNI Mobile, 2014
Need for Power Management
As CMOS technology improves for faster performance, power consumption increases Speed-power trade-off between technology nodes
Source: A, Anand, Managing Leakage – A Challenge for Designers at Lower Technology Nodes, Elite Quill Technology
Multi-Threshold
Sub-threshold leakage increases exponentially with decreasing threshold voltage
Use higher threshold cells on non-critical paths Decrease overall chip
leakage while maintaining slack on critical path
Requires additional masks during fabrication to adjust the dopant density Source: Shi, Cheng and Kapur, Rohit, How Power-Aware
Test Improves Reliability and Yield, EE Times
Power Gating
Source: Apache RedHawk-ALP Power Integrity Tool Description
Disconnect portions of circuit in standby mode to eliminate leakage current
Header/Footer Switch Configurations
Drawbacks Area overhead Voltage droop Output isolation Routing resources
Clock Gating
Combinational Disables the clock on registers when the output is not
changing
Sequential Targets unused computation and don’t care cycles for
further power optimization
Source: Dale, Mitch, The Power of RTL Clock-Gating, Chip Design Magazine
Source: Texas Instruments, Clock Gating for Power Optimization in ASIC Design Cycle
Voltage Scaling
Dynamic Voltage Frequency Scaling (DVFS) Implements a voltage-frequency lookup table to allow the chip to
run at the minimum voltage required by processing demands Open-loop control based on statistical measurements and often
requires large margins Adaptive Voltage Scaling (AVS)
Actual operating speed dependent upon PVT Implements replica of IC critical path to compare delay and allow
the voltage to be adaptively scaled to achieve optimal operating speed
Source: Khan, Neyaz, Dynamic Power Management – Closed Loop Voltage Scaling, Cadence
Relative Power Reduction
Example Power Savings: Baseband Processing Circuit
Source: Bergman, Eyal and Snir, Ran, Power Optimization for Low Power SoCs Targeting Mobile Devices, New Electronics
HW-SW Co-design PMT: HW mod exploits available
SW resources in microprocessor to achieve joint improvement in power, energy
Hardware-Software Co-design of Embedded PM Module (1)
Drawbacks of Vt and Freq scaling: Requires many power converters Leads to bulky architecture that
introduces serious noise and large power switches
Ultimately increases silicon cost
HW
SWHW
Solution
Hardware-Software Co-design of Embedded PM Module (2)
Technique overview: ( Dr. Rajdeep Bondade and Dr. Dongsheng Ma @ University of Arizona)
Use Single-Inductor Multi-Output Converter Use Multiple Software-defined control schemes to design the Converter These schemes work jointly with power stage to ensure power/energy
optimizationStart-up
Steady Output Loads
Power is delivered simultaneously to o/p
SW Power
Controller
Process Sensed Power Info
Power Sensor
Estimator and Allocator
Hardware-Software Co-design of Embedded PM Module (3)
Technique implementation: Adaptive Global/Local Power Allocation Control
Power Source
Global Power Estimate
Load 1
Load 3
Load 2
Load 4
Power Demand for each Load
Sensor sends power info to
Estimator
Request
Hardware-Software Co-design of Embedded PM Module (4)
Case
Power Demand/ Load
Description
Result
A
• Low
• Inductor charged once with energy of total load demand
• Energy is then distributed equivalent to all Loads
• Less frequent switching actions => less noise and power
B
• Heavy
• Inductor charged/ discharged based on individual load demand
• Higher demand load will have higher priority
• Reduce power/ noise for each switching action
C
• Mixed
• Group of power demands
• Focuses on delivering to high power demand group
• Skip low power demand group
• Reduce switching power loss and noise on LPD group
• Improve response times to HPD group
Hardware-Software Co-design of Embedded PM Module (5)
Reference: Hardware-Software Co-Design of an Embedded Power Management Module with Adaptive On-Chip Power Processing Schemes, Rajdeep Bondade and Dongsheng Ma
Figure shows output voltage and inductance in the steady state
Technique Performance Verification:
Figure shows 3 output Voltage regulated at 3.0, 1.8, 0.9
Each output can independently adjusted from 0.9 to 3.0 based on power need
Result: Peak to peak ripple voltage
are controlled below 10mV Inductor waveform verifies
the proposed software defined controller
Silicon Labs Energy Micro MCUs
Microcontroller family focused on low-power and energy sensitive applications Extreme Low Leakage Process Firmware-controlled Power and
Clock Gating
Source: Silicon Labs, EFM32 Microcontroller Selector Guide
Conclusion & Future Works
Power Management is a challenging subject PM is not an automatic process, must be designed analyzed
in every step of designed flow 2 separate ideas regarding software defined power
controller: More embedded sensors for real-time power management There are several topics on using statistical learning software
defined module, local/ global power predictor. These techniques don’t use sensors to collect absolute power info, but “predict” the loading power. Pros: save area. Cons: different systems/ technology changes => develop different
statistical model