ppc to intel arch migration

8/4/2019 PPC to Intel Arch Migration

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PowerPC* toIntelArchitectureMigration

January 2009

White Paper

Lori M. Matassa

Software TechnicalMarketing Engineer

Intel Corporation

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Po w e r P C* t o I n t e l A rch i tectu re M i g ra t i on

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Executive Summary

Completing a successful PowerPC* to Intel

architecture software migration requires

an awareness of architecture differences and its impact to the software. This white

paper outlines the information that should be considered when planning a software

product port from PowerPC to Intel architecture-based platforms. A thorough review

of the architecture differences, operating system considerations, system initialization,

migration tools, and software development products must be completed. The first thing

to understand is that every situation is different. Therefore, the scope of work and

effort required for the port will vary between situations. The information outlined in this

paper will identify items that need to be considered when investigating the migration

and resources that can assist during the implementation.


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P ow e r P C* t o I n t e l A rch i tectu re M i g ra t i on

Conten ts

Executive Summary ...............................................................................2Introduction ..........................................................................................4

Intel Embedded Design Center........................................................4

Reasons to Migrate to Intel Architecture .............................................4

Migration Considerations .......................................................................5

Hardware Architecture Differences ..................................................... 5

Operating Systems ..........................................................................7

System Initialization Firmware .......................................................... 8

Architecture Migration Tools............................................................ 11

Software Development Tools........................................................... 13

Multi-core Solutions ....................................................................... 15

Training and Design I nformation ......................................................... 18

Intel Software College.................................................................. 18

Intel Software Network ................................................................ 18

Migration Design Guide (Putting It All Together) .................................18

Step 1 Port PowerPC* Code to Target Operating System.................. 19

Step 2 Execute Code Correctly on OneIntel Architecture Core................................................................. 19

Step 3 Optimize the Code for Performance onOne Intel Architecture Core .......................................................... 20

Step 4 Apply Multi-core Software Design Updates ........................... 21

Step 5 Optimize the Software Design for Multi-coreIntel Architecture Performance...................................................... 21

Conclusion ........................................................................................... 22


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Introduction

Porting software to platforms of different processor architecture can be simple orrequire additional effort depending on the design (portability) of the original software.

Software that is specifically written to run on one hardware architecture will need to beupdated to support the architecture differences. For software implementations thatabstract away the hardware and operating system specific information, the port could

be as simple as a recompile. One of the main migration hurdles is the Endiannessdifference between PowerPC* (PPC) and Intel architecture. Other considerationsinclude variations between the current and target operating systems and developmenttools. Completing a successful port involves assessing and understanding the currentsituation and requirements before the migration begins.

Intel Embedded Design Center

Intel provides the Intel

Embedded Design Center (EDC) to help designers get startedwith designing on Intel architecture. The EDC provides embedded hardware andsoftware design information, as well as step-by-step guidance to design informationand decisions. The EDC simplifies information searches by providing everything you

need to know about designing for embedded Intel architecture systems all in onelocation. Whether the information needed is hardware schematics or firmware anddevice drivers, the EDC is the one-stop shop for embedded Intel architecturehardware and software design information such as downloads, white papers, and casestudies at your fingertips. Visit the EDC at http://www.intel.com/embedded/edc.

Reasons to Migrate to Intel

Architecture

Intel architecture has established itself as a proven leader in performanceand innovation over its entire history. Intel continues to offer a strongroadmap with products that are optimized for performance, power and value.Also, Intel's involvement in developing and driving standards based platformshas dramatically altered the computer industry. Today most customersdemand standards based open architecture and compatibility with legacyapplications.

Architecture migration is faced with software development as a key opportunity inmeeting time-to-market constraints, and the availability of good software development

tools is a main influencer when making decisions for any software system. Intelprovides a full line of Intel development products (see page 13) that help implement,debug, and tune software for performance and correctness, as well as reducing thetime-to-market. Open source initiatives such as Linux* and the strong support fordevelopment tools from major independent software vendors (ISVs) and operatingsystem vendors (OSVs) are considerations that are too important to pass up. Inaddition, Intel's initiatives in driving a strong ecosystem of independent hardwarevendors (IHVs) and standards to address various form factors, helps customers tofocus on their unique solution and enhance their intellectual property.
http://www.intel.com/embedded/edchttp://www.intel.com/embedded/edc


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Migration Considerations

Architecture migration includes consideration of multiple software design areasincluding several hardware architectural differences, operating system, system

initialization, and migration and development tools. Another architecture aspect to beconsidered when migrating from PPC to Intel architecture is moving from a uni-processor serial code to a multi-core software system. This paper discusses each of

these areas along with various design choices. Understanding that every migrationsituation is different, the migration design guide will step system designers throughsituational decisions and solutions, which will guide their overall migration plan.

Hardware Architecture Differences

The hardware architecture differences between PPC and Intel architecture spaninstruction-set, register, and memory categories. The beauty of developing code in a

high level programming language, such as C-language, is that the source code, for themost part, is portable between hardware architectures. This is because high levellanguages use compilers, which handle instruction-set and register differences (theygenerate the machine code for the target processor architecture). Architectural

differences to be aware of include the following items listed in Table 1. DifferencesBetween PPC and Intel Hardware Architecture:

Tab le 1. Di fferences Between PPC and Intel Hardware Architecture1

Instruction set

Instructions

PPC and Intel architecture instructions are very different. For someinstructions there is no one to one (PPC to Intel architecture)

equivalent. Refer to the Intel Software Developer Manuals andinstruction set information and tools that may assist the assemblycode migration.

Alignment

PPC instructions are all 4 bytes in size and must be aligned on 4byte boundaries. Intel architecture instructions vary in size and

therefore do not require alignment.

On PPC a bool is 4 bytes. On Intel architecture, a bool is 1 byte.Make the code portable by changing the PPC boolean data to anunsigned 32-bit integer.

Vector orientedinstructions

PPC uses Altivec* instructions. Intel architecture uses StreamingSIMD Extensions (SSE). Refer to the Vector Oriented Code sectionfor details about migrating Altivec to SSE instructions.

Operations

Divide-by-zero

For Integer divide-by-zero, PPC simply returns zero. On Intelarchitecture, executing this operation is fatal. Code should alwayscheck the denominator for zero before executing the divide

operation. There is no difference in operation between PPC andIntel architecture floating point divide-by-zero.


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Endianness

Endianness describes how multi-byte data is represented by a computer system and isdictated by the CPU architecture of the system. Unfortunately not all computer systemsare designed with the same Endian-architecture.

Big endian is an order in which the big end (most significant value in the sequence) isstored first, at the lowest storage address. The most significant byte is stored in theleftmost position. PPC systems use the big endian model, where the most significantbyte is at the lowest address in memory. Little endian is an order in which the littleend (least significant value in the sequence) is stored first. The most significant byte isstored in the rightmost position. Intel architecture systems use the little endianmodel, where the least significant byte is at the lowest address in memory. In Table 2,

the 32-bit hex value 0x12345678 is stored in memory as follows for each Endian-architecture. The lowest memory address is represented in the leftmost position. Youcan break up your copy into three levels of headings if desired, but no more.

Hardware Devices

Drivers andLibraries

If a PPC driver or library comes from a third party vendor, checkwith the vendor for equivalent Intel architecture products.

If any device drivers or libraries are developed in-house, they willneed to be re-written for Intel architecture.

Refer to the Device Drivers section of this paper for chipset andgraphics driver information.

Registers

Callingconventions

Specified by theapplication

binary interface(ABI)

Arguments are passed in registers for PPC. For Intel architecture,arguments are passed on the stack.

Intel architecture has fewer registers than PPC and therefore local

variables may be stored on the stack as well.

Memory

Byte order

(Endianness)

Endianness describes how multi-byte data is represented by a

computer system and is dictated by the CPU architecture of thesystem. Intel architecture uses little endian and PPC uses bigendian format to store multi-byte data. The difference in Endian-architecture is an issue when software or data is shared betweencomputer systems. Refer to the Endianness section of this paper formore information.

Bit fieldsThe order of bit fields in memory can be reversed betweenarchitectures. Refer to the Bit Fields and Bit Masks section of theEndianness white paper for more details.

1. "Architectural Differences." Universal Binary Programming Guidelines. 26 Feb 2007. Apple.com. 18 Dec2008. http://developer.apple.com/documentation/MacOSX/Conceptual/universal_binary/universal_binary_intro/chapter_1_section_1.html

Table 1 . Di fferences Between PPC and Inte l Hardware Architecture1
http://developer.apple.com/documentation/MacOSX/Conceptual/universal_binary/universal_binary_intro/chapter_1_section_1.htmlhttp://developer.apple.com/documentation/MacOSX/Conceptual/universal_binary/universal_binary_intro/chapter_1_section_1.htmlhttp://developer.apple.com/documentation/MacOSX/Conceptual/universal_binary/universal_binary_intro/chapter_1_section_1.htmlhttp://developer.apple.com/documentation/MacOSX/Conceptual/universal_binary/universal_binary_intro/chapter_1_section_1.html


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The difference in Endian-architecture is an issue when software or data is sharedbetween computer systems; between files or passed through a network connection. Ifthe code is not endian-neutral it must be updated to account for little endianarchitecture because difference in byte ordering can produce incorrect results. Forcomplete details that describe software considerations related to microprocessorEndian architecture and guidelines for developing Endian-neutral code see the EndianWhite Paper at:http://www.intel.com/design/intarch/papers/endian.htm.

Operating Systems

If the architecture migration includes a port to a new OS, check with the target OSdistributor to see if there is an OS migration guide available that supports the current

and target OS pair used in the migration.

Considerations for porting source code to a new OS not only includes updating the OScalls, but also includes locating the correct version of all necessary third-party utilitiesand libraries needed to build the application. Common examples are:

Source control system

Developer tools

Build utilities

Licensing, graphics, or other third-party libraries

If the situation allows, make sure to port to the OS version that will be used for thetarget multi-core solution. Meaning, if SMP will be used as the target OS solution, portto the SMP version of the target OS.

Real-time Requirements and P ower Management

Some embedded applications depend on predictable response times and therefore runon operating systems (OSs) offering real-time support. In a real-time environment, it iscritical for an OS to be able to guarantee certain time slices. Additionally, it is importantthat time slice measurements remain consistent. This should be taken into

consideration when ever power management is enabled. For example: If a high endplatform response should happen within a certain number of microseconds, with powermanagement is enabled it could require some of that time for the processor to wakeup, which affects the amount of time left for the response. Furthermore, Speculativepre-fetch memory accesses can also cause real-time operating (RTOS) issues in tightloops. For requirements of system RTOS guaranteed response times, Intelarchitecture power management and speculative pre-fetch features should be disabled.

Tab le 2. Hex va lues for Endian-archi tecture

EndianOrder

Byte00

Byte01

Byte02

Byte03

BigEndian

12 34 56 78

LittleEndian

78 (LSB) 56 34 12
http://www.intel.com/design/intarch/papers/endian.htmhttp://www.intel.com/design/intarch/papers/endian.htm


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Device Drivers

If the PPC driver is developed in-house, the low level initialization will need to beupdated for Intel architecture. Open source versions of the driver may help guide thechanges that are required.

Intel Embedded and Communications Chipset Drivers

The Intel architecture chipset data sheets contain information about registers thatneed to be programmed. Technical information about the Intel embedded andcommunications chipsets can be found at http://www.intel.com/products/embedded/chipsets.htm?iid=embed_body+chip.

Depending on the OS, Intel architecture device drivers are available from variousproviders. The RTOS board support packages (BSPs) for Intel embedded chipsetdrivers are available from the RTOS vendors. The standard desktop, mobile, serverdrivers for Microsoft Windows* (XP or Vista*) and Linux* can be download from http://downloadcenter.intel.com/. BSPs for Microsoft Windows CE* can be downloaded fromthese third party vendor sites:

Adeneo Corporation*

BSQUARE*

Wipro Technologies*

Intel Embedded Graphics Drivers

If a graphics driver is required, the IEGD driver is implemented specifically to addressembedded usage models. IEGD is also developed to be supported on MicrosoftWindows XP*, Microsoft Windows XP Embedded*, Microsoft Windows CE*, and various

Linux* distributions. The IEGD driver is not included with packaged chipset drivers orboard support packages, and must download separately at http://www.intel.com/go/iegd.

System Initialization Firmware

Every embedded Intel architecture design must include a firmware stack whichinitializes the processor, memory, IO, peripherals, and may include diagnostic routines.Firmware initializes the system to a point where the operating system can load and

take control. PPC systems use home-grown boot loaders, but achieving systeminitialization on Intel architecture is just as easy for closed box and open box designs.

Boot Loaders for Closed Box Designs

Some embedded systems use minimized specialized firmware stacks created for fastspeed, small size and specific system requirements. These boot loaders perform static

hardware configurations; only initialize critical hardware features prior to hand off to anoperating system. They are tuned to a targeted OS, specific application or function set,and support minimal upgrade and expansion capabilities.
http://www.intel.com/products/embedded/chipsets.htm?iid=embed_body+chiphttp://www.intel.com/products/embedded/chipsets.htm?iid=embed_body+chiphttp://www.adeneo-embedded.com/srt/en/document/show?location.id:=1360http://www.adeneo-embedded.com/srt/en/document/show?location.id:=1360http://www.bsquare.com/partners/siliconvendors/intel.asphttp://www.bsquare.com/partners/siliconvendors/intel.asphttp://www.wipro.com/pes/alliances/ica/wincebsp.htmhttp://www.wipro.com/pes/alliances/ica/wincebsp.htmhttp://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdfhttp://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdfhttps://support.windriver.com/selfservicewebapp/register.actionhttps://support.windriver.com/selfservicewebapp/register.actionhttps://support.windriver.com/selfservicewebapp/register.actionhttps://support.windriver.com/selfservicewebapp/register.actionhttp://www.intel.com/go/iegdhttp://www.intel.com/go/iegdhttp://www.intel.com/go/iegdhttp://www.intel.com/go/iegdhttps://support.windriver.com/selfservicewebapp/register.actionhttps://support.windriver.com/selfservicewebapp/register.actionhttps://support.windriver.com/selfservicewebapp/register.actionhttp://www.intel.com/products/embedded/chipsets.htm?iid=embed_body+chiphttp://www.intel.com/products/embedded/chipsets.htm?iid=embed_body+chiphttp://www.wipro.com/pes/alliances/ica/wincebsp.htmhttp://www.bsquare.com/partners/siliconvendors/intel.asphttp://www.adeneo-embedded.com/srt/en/document/show?location.id:=1360http://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdfhttp://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdf


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QNX* Fastboot Technology for Intel Atom Processors

QNX* Fastboot technology integrates system initialization into the QNX Neutrino RTOS,eliminating the need for BIOS or other boot loader. It was developed specifically for usein the QNX Neutrino RTOS, for Intel AtomTM processor Z5xx series platforms.

Customers using QNX Fastboot can achieve boot times of milliseconds while eliminatingthe BIOS royalty from their bill of materials.

Intel Architecture System BIOS for Open Box Designs

A common requirement for open, expandable system designs is to provide the broadestpossible system initialization solution, allowing the flexibility to load a wide range of off-

the-shelf operating systems and methodical, dynamic hardware configurations. Thesedesigns will support multiple standard interfaces and expansion slots, and hostmainstream operating systems with a broad set of pre-OS features and are ready torun multiple applications. On IA designs that require the flexibility, developers canchoose from vendor provided firmware.

Legacy Basic Input/ Output System (BIOS)The BIOS initializes the hardware and boots it to a point where the operating systemcan load, and it also abstracts the hardware from the operating system through various

industry standard tables (ACPI, SMBIOS, IRQ Routing, Memory maps, etc). Access tothe hardware is directly made through silicon specific BIOS commands or industrystandards interfaces. Intel architecture has commonly used BIOS for 20+ years tosupport designs with multiple use cases, customizable services, multiple boot paths,native OSs, or are feature rich.

Major BIOS vendors include:

American Megatrends Inc.*

Insyde Software Corp.*

Phoenix Technologies, Ltd.*

Nanjing Byosoft Co.,Ltd.*

Unified Extensible Firmware Interface (UEFI)

The Unified EFI Forum, Inc., formed in 2005, is a Washington non-profit corporationwhose goal is to forward the technical advancement of the IT industry through the

development and promotion of a set of UEFI standard specifications. Intel developedthe original Extensible Firmware Interface (EFI) and donated it to the UEFI forum as astarting point for the creation of the industry specifications, including UEFI andPlatform Interface (PI). The forum is governed by a board of directors from elevenpromoter companies including AMD*, AMI*, Apple*, Dell*, HP*, IBM*, Insyde*, Intel,Lenovo*, Microsoft* and Phoenix*. In addition there are over 120 contributor and

adopter member companies.
http://www.qnx.com/news/pr_3024_1.htmlhttp://www.ami.com/http://www.ami.com/http://www.insydesw.com/http://www.insydesw.com/http://www.phoenix.com/en/Home/default.htmhttp://www.phoenix.com/en/Home/default.htmhttp://byosoft.com.cn/en_about.asphttp://byosoft.com.cn/en_about.asphttp://www.uefi.org/homehttp://www.intel.com/technology/efi/http://byosoft.com.cn/en_about.asphttp://www.intel.com/technology/efi/http://www.uefi.org/homehttp://www.phoenix.com/en/Home/default.htmhttp://www.insydesw.com/http://www.ami.com/http://www.qnx.com/news/pr_3024_1.html


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The UEFI Forum is responsible for two specifications:

1. The Unified Extensible Firmware Interface (UEFI) specification - Defines interfacesbetween OS, add-in firmware drivers and system firmware where the OS and otherhigh-level software should ONLY interact with exposed interfaces and services

defined by the UEFI specification: Includes the EFI Byte Code (EBC) specification which defines an interpretive

layer for portable component drivers.

2. Platform Initialization Interface (PI) specifications The core code and servicesthat are required for an implementation of the Platform Initialization (PI)specifications (hereafter referred to as the PI Architecture).

Interoperability standards between firmware phases and pre-OS componentsfrom different providers.

The UEFI specifications define a model for the interface between operating systems andplatform firmware. The interface consists of data tables that contain platform-relatedinformation, plus boot and runtime service calls that are available to the operating

system and its loader. Together, these provide a standard environment for booting anoperating system and running pre-boot applications.

For more details about the UEFI specifications, writing UEFI drivers, and how to use the

UEFI Sample Implementation and UEFI Application Toolkit, see the UEFI web site athttp://www.uefi.org/.

Figure 1. UEFI Block Diagram

text

text

text

Platform Drivers

Silicon ComponentModules

PI Specification

UEFI Specification

OSPre-boot

Tools

Hardware
http://www.uefi.org/homehttp://www.uefi.org/home


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Intel Platform Innovation Framework for EFI

The Intel Platform Innovation Framework for EFI (referred to as "the Framework" andpreviously called Tiano) is an implementation of UEFI and PI specifications. TheFramework is a set of architectural interfaces that has been designed to enable the

BIOS industry and our customers to accelerate the evolution of innovative,differentiated, platform designs. The Framework is Intel's recommended

implementation of the PI and UEFI Specifications for platforms based on all members ofthe Intel architecture family. BIOS vendors provide a compatibility support module(CSM), which is used to connect operating systems to the Framework that requirelegacy BIOS interfaces.

The Framework is a reference code base developed by Intel. The Framework firmwareimplementation includes support for UEFI without the CSM, but does provide interfacesthat support adding a CSM supplied by a BIOS vendor. The EFI Developer Kit (EDKII) isthe open source portion of the Framework code base, referred to as the Foundation,and is available from the TianoCore project at http://www.tianocore.org/.

A complete Framework implementation is not generally available directly from Intel,

but is offered by participating vendors as products and services based on theFramework for both Intel and non-Intel silicon.

Framework Vendors:

Aptio* by American Megatrends Inc*

InsydeH2O* by Insyde Software Corp*

SecureCore Tiano* by Phoenix Technologies, Ltd*

Nanjing Byosoft Co.,Ltd*

For information on the Framework and specification, as well as participating vendorinformation see: http://www.intel.com/technology/framework/. More informationabout the genesis of the Intel Platform Innovation Framework and its implementation

and adoption can be found at wikipedia http://en.wikipedia.org/wiki/Tiano. For moreinformation on implementing Intel Embedded Intel architecture firmware see thewhite paper at the EDC site titled Implementing Firmware on Embedded IA Designs.

Architecture Migration Tools

For the most part, migration will need to be done manually. However, there are a fewmigration tools that can provide some help. These tools are described below.

Intel Architecture and Instruction Set

We must consider that there will always be a portion of assembly code either containedin assembly source files or inline assembly used within C source files. Assembly code is

not portable and will need to be updated to target Intel

architecture processorinstructions. If the code was originally written in assembly for performance reasons,hardware and compiler improvements may now permit it to be rewritten in C or C++.
https://www.tianocore.org/http://www.ami.com/products/product.cfm?ProdID=127&CatID=6&SubID=14http://www.ami.com/products/product.cfm?ProdID=127&CatID=6&SubID=14http://www.insydesw.com/products/products-efi-h2o.htmhttp://www.insydesw.com/products/products-efi-h2o.htmhttp://www.phoenix.com/en/OEM-ODM/products/browse+by+products/phoenix+securecore+tiano/default.htmhttp://www.phoenix.com/en/OEM-ODM/products/browse+by+products/phoenix+securecore+tiano/default.htmhttp://byosoft.com.cn/en_about.asphttp://byosoft.com.cn/en_about.asphttp://www.intel.com/technology/framework/http://en.wikipedia.org/wiki/Tianohttp://download.intel.com/design/intarch/papers/321072.pdfhttp://download.intel.com/design/intarch/papers/321072.pdfhttps://www.tianocore.org/http://en.wikipedia.org/wiki/Tianohttp://www.intel.com/technology/framework/http://byosoft.com.cn/en_about.asphttp://www.phoenix.com/en/OEM-ODM/products/browse+by+products/phoenix+securecore+tiano/default.htmhttp://www.insydesw.com/products/products-efi-h2o.htmhttp://www.ami.com/products/product.cfm?ProdID=127&CatID=6&SubID=14


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Intel 64 and I A-32 Architectures Software Developer'sManuals

The Intel 64 and IA-32 Architectures Software Developers Manuals contain thedetails for each Intel architecture instruction, including the Intel Streaming SIMD

Extensions 4 (Intel SSE4) instructions. Use this set of manuals as a reference forconverting (re-writing) PPC assembly code instructions to equivalent functionality with

Intel architecture instructions.

Vector Oriented Code

SIMD (single instruction, multiple data) is a technology used for vector oriented code.AltiVec* and SSE (Streaming SIMD Extensions) are extensions to the fundamentalprocessor architecture instruction set. PPC uses AltiVec and Intel architecture usesSSE. If the PPC software uses vector oriented code the AltiVec instructions must beported to SSE instructions and optimized for Intel architecture.

Manual Vector Oriented Code Migration

For information on translating AltiVec to SSE instructions see the AltiVec/SSE MigrationGuide.

N.A. Software* Vector Oriented Code Conversion Tools

Converting existing highly optimized AltiVec* software to Intel architecture SSE canbe a daunting task. Intel is working with N.A. Software* Vector Oriented CodeConversion Tools to bring three tools to market for Linux* and Wind River* VxWorks*operating systems, which will reduce the Digital Signal Processing (DSP) softwareconversion effort.

1. Vector Signal Image Processing Library (VSIPL) - Highly efficient computationalmiddleware for signal and image processing applications. VSIPL is an Openstandard for embedded signal and image processing software and hardwarevendors. It abstracts hardware implementation details; applications are portableacross processor types and generations without rewriting the software. This toolwill be available as the VSIPL library, or as C-VSIPL, the plain C equivalent for inhouse libraries that need to be converted. N.A.Software will also port custom in-house DSP libraries to Intel architecture.

2. Altivec.h include file for Intel Architecture Same as the PPC altivec.h, buttargets the Intel SSE instruction set instead of Altivec. Applications DSP coderemains unchanged.

3. Altivec Assembler to Intel Assembler-Compiler Converts small(ish) blocks ofPPC Altivec assembler into C code, which can then be compiled into IA SSEassembler code. This tool is currently under a feasibility design study by Intel andthe prototype should be available by the end of 2008. If successful, the productcould be released in mid 2009.
http://developer.intel.com/products/processor/manuals/index.htm?iid=technology_virtualizationengage+body_intel64manualhttp://developer.intel.com/products/processor/manuals/index.htm?iid=technology_virtualizationengage+body_intel64manualhttp://developer.intel.com/products/processor/manuals/index.htm?iid=technology_virtualizationengage+body_intel64manualhttp://developer.apple.com/documentation/Performance/Conceptual/Accelerate_sse_migration/Accelerate_sse_migration.pdfhttp://developer.apple.com/documentation/Performance/Conceptual/Accelerate_sse_migration/Accelerate_sse_migration.pdfhttp://www.nasoftware.co.uk/products/conversiontools.htmlhttp://www.vsipl.org/http://www.vsipl.org/http://developer.apple.com/documentation/Performance/Conceptual/Accelerate_sse_migration/Accelerate_sse_migration.pdfhttp://developer.apple.com/documentation/Performance/Conceptual/Accelerate_sse_migration/Accelerate_sse_migration.pdfhttp://www.nasoftware.co.uk/products/conversiontools.htmlhttp://developer.intel.com/products/processor/manuals/index.htm?iid=technology_virtualizationengage+body_intel64manual


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Software Development Tools

Software tools are important for any platform migration. Understanding the needs andavailability of tools for the new platform is important when investigating therequirements of the port. Keep in mind that software development tools have system

requirements, as with all software applications. This means that the tool must supportthe target processor and operating system. Thus, a tool that is used on the current pre-port system may not be available for the target system. This may affect the OS andtools choice for your migration plan. Check with the OS and tools provider to determinetheir tools product availability for the target Intel processor.

Intel Software Development P roducts

Intel supports a wide variety ofsoftware development products, which help developersunleash the performance of their software on Intel platforms. The Intel softwaretools product line includes compilers and debuggers, performance analyzers,

performance libraries, and threading tools. These tools are extremely helpful whenimplementing threads and even more important when tuning the performance of the

application and optimizing the software for multi-core platforms. For more details abouteach product and OS support, visit the products web sites.

Intel Compilers

Intel Compilers are compatible with other tools you might use, integrate into populardevelopment environments and are source and binary compatibility with other widely-used compilers. The Intel compilers offer the support for creating multi-threaded

applications and includes features for advanced optimization, automatic processordispatch, vectorization, auto-parallelization, multithreading, OpenMP*, dataprefetching, and loop unrolling, along with highly optimized libraries. Visit the product

web site at: http://www.intel.com/cd/software/products/asmo-na/eng/compilers/284132.htm.

OpenMP* is a standard for compiler based multiprocessing features. To learn moreabout OpenMP and the specification visit the web site: http://www.openmp.org.

Intel VTune Performance Analyzer

The Intel VTune Performance Analyzer provides application performance tuning witha graphical user interface and no recompiles required. It is compiler and languageindependent so it works with C, C++, Fortran, C#, Java, .NET and more. Unlike someproducts that offer only call graph analysis or only a limited set of sampling events,Intel VTune analyzer offers both with an extensive set of tuning events for all thelatest Intel processors. This performance analyzer can locate hotspots in the code,identifying the lines of code where the hotspot exists. Visit the product web site at:http://www.intel.com/cd/software/products/asmo-na/eng/vtune/239144.htm.

Intel Performance Libraries

Intel Performance Libraries are foundation level building blocks for high-performancethreading, math and multimedia applications, and provide consistent performanceacross all Intel microprocessors. Use the performance libraries to get the most out oftodays new multi-core and multi-processor systems.
http://www3.intel.com/cd/software/products/asmo-na/eng/index.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/compilers/284132.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/compilers/284132.htmhttp://www.openmp.org/http://www.intel.com/cd/software/products/asmo-na/eng/vtune/239144.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/vtune/239144.htmhttp://www.openmp.org/http://www.intel.com/cd/software/products/asmo-na/eng/compilers/284132.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/compilers/284132.htmhttp://www3.intel.com/cd/software/products/asmo-na/eng/index.htm


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Intel Integrated Performance Primitives

This highly optimized Intel software library contains audio, video, imaging,

cryptography, speech recognition, and signal processing functions and codeccomponent functions for digital media and data-processing applications.

The Intel Math Kernel Library

This library contains highly optimized, extensively threaded, mathematical functions forengineering, scientific, and financial applications that require maximum performance.

Visit the Intel performance library products web site at: http://www.intel.com/cd/software/products/asmo-na/eng/perflib/219780.htm.

Intel Threading Analysis Tools

There is a better way to develop threaded software. Intel Thread Checker, IntelThread Profiler and Intel Threading Building Blocks (Intel TBB) help to thread yourapplication correctly and unleash its true performance on Intel multi-core processor

systems.

Intel Thread Checker

The Intel Thread Checker facilitates debugging of multithreaded programs byautomatically finding common errors such as storage conflicts, deadlock, API violations,inconsistent variable scope, thread stack overflows, etc. The non-deterministic natureof concurrency errors makes them particularly difficult to find with traditionaldebuggers. The Intel Thread Checker pinpoints error locations down to the sourcelines involved and provides stack traces showing the paths taken by the threads toreach the error. It also identifies the variables involved.

Intel Thread Profiler

The Intel Thread Profiler facilitates analysis of applications written using Windows*API threading API, POSIX Threading API or OpenMP pragmas. The OpenMP ThreadProfiler provides details on the time spent in serial regions, parallel regions, and criticalsections and graphically displays performance bottlenecks due to load imbalance, lockcontention, and parallel overhead in OpenMP applications. Performance data can bedisplayed for the whole program, by region, and even down to individual threads. TheWindows API or POSIX Threads API Thread Profiler facilitates understanding the

threading patterns in multithreaded software by visual depiction of thread hierarchiesand their interactions. It will also help identify and compare the performance impact ofdifferent synchronization methods, different numbers of threads, or different

algorithms. Since the Intel Thread Profiler plugs in to the Intel VTune PerformanceAnalyzer, multiple runs across different number of processors can be compared todetermine the scalability profile. It also helps locate synchronization constructs thatdirectly impact execution time and correlates to the corresponding source line in the

application.
http://www.intel.com/cd/software/products/asmo-na/eng/perflib/219780.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/perflib/219780.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/perflib/219780.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/perflib/219780.htm


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Intel Threading Building Blocks (TBB)

Intel TBB is a C++ runtime library that abstracts the low-level threading details

necessary for optimal multi-core performance. It uses common C++ templates andcoding style to eliminate tedious threading implementation work. Intel TBB requires

fewer lines of code to achieve parallelism than other threading models. Applicationswritten with Intel TBB are portable across platforms. Since the library is alsoinherently scalable, no code maintenance is required as more processor cores becomeavailable.

An open source version of Intel Threading Building Blocks is also available.

There is also a book available for Intel Threading Building Blocks titled: IntelThreading Building Blocks: Outfitting C++ for Multi-core Processor Parallelism. See theIntel Threading Building Blocks product web site for directions on ordering the book.

Visit the threading tools products web site at: http://www.intel.com/cd/software/products/asmo-na/eng/threading/219785.htm.

On Chip Debugging Tools

Joint Test Action Group (JTAG) is a transport system used for in-circuit emulators,which are useful for debugging embedded systems. JTAG vendors that support Intelarchitecture include American Arium*, and as of February 2009 Macraigor SystemsLLC* will also provide support for Intel architecture.

Multi-core Solutions

There are several factors that will guide the plan for the multi-core migration. Factors

include the starting point (design) of the original source code, as well as migrationgoals and constraints. Each method has its own strengths.

More operating systems are now providing Symmetric Multiprocessing (SMP), includingembedded RTOSs, but SMP requires code to be architected to take advantage ofmultiple CPUs (parallelized). For situations where the application(s) is not well suitedfor parallelization, Asymmetric Multiprocessing (AMP) and Virtualization could be amore viable solution for leveraging the extra processing capabilities of multi-corehardware.

Employing virtualization and partitioning in the embedded system will enable some

benefit to be derived from multi-core processors independent of explicit OS support.However, the ideal situation is to have symmetric multiprocessing and asymmetricmultiprocessing, including virtualization, at your disposal.

Asymmetric Multiprocessing

AMP has started to show up in product descriptions for embedded processors. The termis used to refer to a case where multiple OS images are supported on a single CPUconsisting of multiple cores. The term is used to distinguish from the SMP case wherethere is a single OS image on the CPU.
http://www.threadingbuildingblocks.org/http://www.intel.com/cd/software/products/asmo-na/eng/threading/219785.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/threading/219785.htmhttp://www.arium.com/http://www.macraigor.com/http://www.macraigor.com/http://www.macraigor.com/http://www.macraigor.com/http://www.arium.com/http://www.intel.com/cd/software/products/asmo-na/eng/threading/219785.htmhttp://www.intel.com/cd/software/products/asmo-na/eng/threading/219785.htmhttp://www.threadingbuildingblocks.org/


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AMP requires no application changes to leverage the benefits of multiple cores. It canleverage multiple cores by running multiple instances of the OS and application inseparate partitions that are dedicated to specific cores, PCI devices, and systemmemory areas. AMP requires a boot loader that supports AMP (can partition thehardware resources and make OS/application assignments to the partitions). The OS

must also meet requirements to support AMP such as: The OS must be relocate-able,must be able to restrict its memory region, and the OS must only operate on it

assigned PCI devices.

Wind River* VxWorks* AMP Support for IntelArchitecture

Wind River* will release a VxWorks* AMP solution for Intel architecture in January of2009. The first product will allow versions of VxWorks 5.5 (uniprocessor) and VxWorks6.7 (SMP) to reside side-by-side on the same system. This OS is the first embeddedAMP product for Intel architecture. This AMP solution allows legacy serial PPC/VxWorks designs to take advantage of Intel architecture multi-core hardware,keeping the legacy software unmodified while running new/future code (parallelized),

in a VxWorks SMP partition.

Symmetric Multiprocessing

SMP operating systems treat all cores as equals and distribute the workload/processingto the available cores. An SMP design is probably the more efficient way to take

advantage of multi-core hardware. It can be written to scale performance automaticallyas the number of processing cores increase. The tradeoff for the SMP performance andscalability benefit is that writing software for parallel processing can be tricky becausethe software design must decompose the problem into sub problems that can safelyexecute simultaneously (threads are used to execute the concurrent processing). Forguidelines on multithreading applications see Developing Multithreaded Applications: APlatform Consistent Approach. For symmetric multi-processing using Wind River*VxWorks*, see Best Practices: Adoption of Symmetric Multiprocessing Using VxWorks

and Intel Multi-core Processors White Paper.

OS Based (SMP Affinity) - Use processor affinity mechanisms to assign specific cores tospecific tasks/threads. This method can improve performance on multiprocessorsystems by pinning threads that share data to cores that share cache, which improves

data locality in cache and thus, improves cache hits. Refer to the Intel SoftwareNetwork article Improved Linux* SMP Scaling: User-directed Processor Affinity fordetails about user directed affinity. An example where SMP affinity improvedperformance on a dual processor multi-core system is the case study Intel performedon an open source intrusion detection application known as SNORT*. Read the casestudy Supra-linear Packet Processing Performance with Intel Multi-core Processors formore details.

Most of the popular commercial OSs have SMP products, such as Microsoft* Windows*

server and client and Linux distributions. However, this isnt the norm for embeddedand real-time OSs. Understand the level of SMP support provided by your OS.
http://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdfhttp://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdfhttp://download.intel.com/design/intarch/papers/321307.pdfhttp://download.intel.com/design/intarch/papers/321307.pdfhttp://download.intel.com/design/intarch/papers/321307.pdfhttp://download.intel.com/design/intarch/papers/321307.pdfhttp://download.intel.com/design/intarch/papers/321307.pdfhttp://software.intel.com/en-us/articles/improved-linux-smp-scaling-user-directed-processor-affinity/http://download.intel.com/technology/advanced_comm/31156601.pdfhttp://download.intel.com/technology/advanced_comm/31156601.pdfhttp://download.intel.com/technology/advanced_comm/31156601.pdfhttp://download.intel.com/technology/advanced_comm/31156601.pdfhttp://download.intel.com/technology/advanced_comm/31156601.pdfhttp://software.intel.com/en-us/articles/improved-linux-smp-scaling-user-directed-processor-affinity/http://download.intel.com/design/intarch/papers/321307.pdfhttp://download.intel.com/design/intarch/papers/321307.pdfhttp://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdfhttp://cache-www.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdf


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RTOS vendors that provide real-time SMP support for Intel architecture are:

Green Hills Integrity*

LynuxWorks LynxOS*

QNX* Neutrino* Wind River* VxWorks*

Virtualization

The beauty of virtualization is that it can bring together the benefits of all multi-coresolutions on a single system and extend those benefits with additional features such assecurity, quality of service (QoS), high availability (HA), and load distribution.

Virtualization provides a software management layer that increases software protectionbetween the partitions and provides core management to optimize power efficiency.Basically, the CPU is run as multiple independent partitions each running their own OSand application. This is a very effective strategy for applications that are constructedfrom multiple application-components that are independent and CPU bound (i.e. not

bound by contention to shared resources).

There is no need to make legacy software stack changes when using virtualization to

partition multiple OSs to run within virtual machines (VM). Instead, let the VirtualMachine Manager (VMM) manage the assignment and access between the VMs andplatform resources. There are several use cases for partitioning including: system

consolidation, running an RTOS side-by-side with a GPOS (also referred to as OS co-location), and leveraging the additional processing power of multi-core hardware byreplicating the application(s) and OSs across multiple cores. Intel VirtualizationTechnology (Intel VT) provides features that make VMM development easier andenhance performance of virtualized systems enabled with the technology. Visit theIntel Product Technologies for Intel Embedded and Communications Applicationsweb site for more information about Intel VT and other technologies: http://www.intel.com/technology/advanced_comm/index.htm.

VMM vendors that support real-time and Intel VT features are:

Green Hills Integrity Padded Cell*

LynuxWorks LynxSecure*

TenAsys*

VirtualLogix VLX*

Wind River*
http://ghs.com/products/rtos/integrity.htmlhttp://ghs.com/products/rtos/integrity.htmlhttp://www.lynuxworks.com/http://www.lynuxworks.com/http://www.qnx.com/products/neutrino_rtos/http://www.qnx.com/products/neutrino_rtos/http://www.windriver.com/http://www.windriver.com/http://www.intel.com/technology/advanced_comm/index.htmhttp://www.intel.com/technology/advanced_comm/index.htmhttp://www.tenasys.com/http://www.tenasys.com/http://www.virtuallogix.com/http://www.virtuallogix.com/http://www.virtuallogix.com/http://www.tenasys.com/http://www.intel.com/technology/advanced_comm/index.htmhttp://www.intel.com/technology/advanced_comm/index.htmhttp://www.windriver.com/http://www.qnx.com/products/neutrino_rtos/http://www.lynuxworks.com/http://ghs.com/products/rtos/integrity.html


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Training and Design Information

Intel Software CollegeThe Intel Software College provides training for Intel processors, softwaredevelopment products, multi-core, and software technologies such as parallelprogramming. There are several classroom, online, and on-demand web-based courses

available. Refer to the following web site for more information about the Intel SoftwareCollege:https://shale.intel.com/softwarecollege/.

Intel Software Network

Intel has a global network of software tools and resources that bring together the

proven depth and breadth of Intel's engineering expertise, technology leadership,strategic insight, and global reach, delivering an offering that works better for you.

Connect with community developers and engineers within the network forums andblogs, and access software development products, training, and knowledge bases foryour software development requirements. Find the Intel Software Network homepage at: http://software.intel.com.

Migration Design Guide (Putting ItAll Together)

Up to this point, this paper discussed the software design areas that need to beconsidered when migrating from PowerPC* to Intel architecture. The migrationmethodology provides guidelines for the procedures of the migration. The guide stepsthrough situational decisions, resulting in an outline for the overall migration solutionand plan. For each step the Embedded Design Center can be consulted for furtherdesign information. There are five ordered steps for the migration and cover OSrequirements, hardware differences, and software optimization on the target Intelarchitecture platform:

1. Port Code to Target Operating System

2. Execute code correctly on one Intel architecture core.

3. Optimize the code for performance on one Intel architecture core.

4. Apply multi-core software design updates.

5. Optimize the software design for multi-core Intel architecture performance.
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Step 1 Port Pow erPC* Code to Target OperatingSystem

If the architecture migration includes a port to a different operating system, complete

the port to the new operating system before starting the migration of the PPC softwareto the Intel architecture hardware. The goal in this step is to ensure that the softwareperforms as expected and correctly on the new OS. Since this step requires stability ofthe same code running on the target OS, do not make other software design changes inthis step. Refer to the OS section in this paper for more details.

Step 2 Execute Code Correctly on OneIntel Architecture Core

1. Update the operating system related code for Intel architecture:

Whether the current and target OS are the same or different, device drivers,libraries, and software development tools need to be surveyed and availability forIntel architecture determined.

a. Intel Embedded Graphics Drivers (IEGD) can be downloaded at:www.intel.com/go/iegd.

b. Intel embedded chipset drivers:

i. Standard desktop, mobile, and server chipset drivers for Microsoft (XP orVista*) can be downloaded at: http://downloadcenter.intel.com/ .

ii. Board support packages (BSPs) for RTOSs are provided by the RTOS vendor.

iii. Board support packages (BSPs) for Microsoft* Windows CE*, can bedownloaded from these third party vendors sites:

Adeneo Corporation*

BSQUARE*

Wipro Technologies*

c. If any device drivers or libraries are developed in-house, they will need to be re-written for Intel architecture.

d. If any third party drivers or libraries are required, check with the third partyvendor (TPV) for equivalent Intel architecture products.

e. Development tools for Intel architecture. See the Intel SoftwareDevelopment Products section for information about Intel tools and visit theproducts web sites for information on OS support. On Chip Debugging Tools forIntel architecture are supported by American Arium or Macraigor Systems LLC(February 2009).

2. Choose the Method for System Initialization:

a. BIOS Choose BIOS and/or UEFI firmware if the design will support multiplestandard interfaces and expansion slots, or a host mainstream OSs with a broad

set of pre-OS features, which are ready to run multiple applications.b. Boot Loader Choose a boot loader for minimal or specialized firmware stacks

where requirements might include optimization for speed, size, or specificsystem requirements, and will support minimal upgrade or expansioncapabilities.

QNX Fastboot Technology is available for Intel AtomTM Processors.
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3. If any part of the code written in assembly code it will need to be updated for IAinstructions.

Solutions:

a. Basic assembly instructions Manually update the basic assembly instructions

using the Intel

64 and IA-32 Architectures Software Developer's Manuals.b. Vector Oriented Code

Solutions:

i. Manually update vector oriented code using the AltiVec/SSE Migration Guide

ii. Translate the vector oriented code using the NASoftware*/PowerPC*/Altivec* to Intel/SSE conversion tools.

4. Does the software abstract the memory architecture of the processor?

a. Yes The code is endian-neutral. No changes are required.

b. No The code will need to be updated for little-endian memory architecture.

Manually update the Endianness differences in the code. Use the EndiannessWhite Paper as a guide to the required changes.

5. Refer to Table 1 for any other architecture differences that may need softwareupdates.

6. Build, test and debug the code using one Intel architecture core.

Step 3 Optimize the Code for Performance onOne Intel Architecture Core

Although the end product will run on multi-core architecture, performance tuningmethodology first requires that serial code be optimized for serial performance.

1. Use the top down, closed end loop performance methodology, and when applicableuse the Intel Software Development Products.

a. Analyze the performance

i. Use the Intel VTune Performance Analyzer to pinpoint hotspots in the codewhere the processing could be distributed between the available cores.

ii. Use the Intel Thread Profiler to identify any thread imbalances.

b. Generate alternatives and implement code changes

i. Use the Intel C++ Compiler and select features to implement advancedoptimizations using Profile Guided Optimization (PGO), executable size, andpower consumption.

ii. Use the Intel Performance Libraries to Increase performance with a varietyof APIs that are highly tuned for Intel architecture. Functions includevideo, imaging, compression, cryptography, audio, speech recognition, andsignal processing functions and codec component functions for digital mediaand data-processing applications.

c. Debug the codeUse the Intel Thread Checker to identify threading bugs, such as data raceand deadlock conditions.

2. The OSV should also provide a set of software development tools. Check with theOSV to understand which tools are available.

3. Use an on-chip debugging tool (JTAG) for low level debugging at the hardware leveland where a high level debugger would otherwise interfere with timing criticalcode.
http://software.intel.com/en-us/articles/de-mystifying-software-performance-optimization/http://software.intel.com/en-us/articles/de-mystifying-software-performance-optimization/http://software.intel.com/en-us/articles/de-mystifying-software-performance-optimization/


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Step 4 Apply Multi-core Software DesignUpdates

Intel multi-core processors are based on Intel Core microarchitecture. There

are several ways to benefit from multi-core. PPC migrations will most likelystart from serial code bases. Therefore, the target software design needs toidentify the solution to meet the migration requirements. SMP can improveapplication performance and can be designed to scale as the number ofprocessors increase. However, SMP requires analysis to identify opportunitiesfor parallelism in the code and re-writing the source code to introduce theparallelism using multithreading. For CPU intensive code, which is difficult toredesign for parallel processing using SMP and multithreading, AMP could be agood alternative solution.

1. Choose the Multi-core Design

a. AMP Choose AMP if the migration requirements specify that no changes can bemade to the application or operating system.

b. SMP Choose SMP if one operating system will be run, using all of the cores as

equal processing resources, and the applications can be parallelized to benefitfrom SMP systems. SMP Affinity can sometimes improve cache hit rates onmultiprocessor systems by pinning certain tasks to certain cores to improve datalocality.

c. Virtualization Choose virtualization for system consolidation, OS co-location,and the additional benefits of features such as security, quality of service (QoS),high availability (HA), and load distribution.

Step 5 Optimize the Software Design for Multi-core Intel Architecture Performance

Whether the design is SMP or AMP, multi-core software designs require specializedsoftware development tools. For SMP the tools help identify and implement parallelism

into the code and pinpoint threading issues such as race conditions, deadlocks, andthread load imbalances. The tuning methodology is the same as for a uni-processor,except that the goal is to correctly and efficiently execute multiple processes or threadssimultaneously across multiple cores. Multi-core tools help implement parallelism and

help tune and debug the parallelized code.

1. Use the top down, closed end loop performance methodology, and when applicable

use the Intel Software Development Products.

a. Intel VTune Performance Analyzer Pinpoints hotspots in the code where theprocessing could be distributed between the available cores.

b. Intel C++ Compiler Multi-core features include OpenMP and auto-parallel.

c. Intel Performance Libraries Increase parallelism with performance threadedAPIs that are highly tuned for Intel architecture multi-core.

d. Intel Threading Tools Implement threads with Intel Thread Building Blocks.Debug threads with Intel Thread Checker. Identify workload imbalances andlock contention of the threads with Intel Thread Profiler.

2. The OSV should also provide a set of multi-core development tools. Check with the

OSV to understand which tools are available.

3. Use an on-chip debugging tool (JTAG) for low level debugging at the hardware level

and where a high level debugger would otherwise interfere with timing criticalcode.
http://softwarecommunity.intel.com/UserFiles/en-us/sma.pdfhttp://softwarecommunity.intel.com/UserFiles/en-us/sma.pdfhttp://softwarecommunity.intel.com/UserFiles/en-us/sma.pdfhttp://softwarecommunity.intel.com/UserFiles/en-us/sma.pdf


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Conclusion

This paper overviewed the software considerations and guidelines for completing asuccessful PowerPC* to Intel architecture software migration, as well as resources

that can assist during the migration software design and implementation. The paperincluded information about architecture differences, migration tools, systeminitialization, operating system considerations, Intel software development products,

and available training for Intel architecture. Remember, each situation is different andthe effort required for the migration depends on the amount of abstraction that isalready programmed into the code. Therefore the migration could be as simple asrecompiling the software or more involved, requiring extra programming for areas ofsoftware that are hardware or OS dependent. Completing a successful port involvesassessing and understanding the current situation and requirements, and planningeach step before the migration begins.

Dont forget to visit the Embedded Design Center at http://www.intel.com/embedded/

edc for the one-stop-shop to embedded Intel

architecture design information.
http://www.intel.com/embedded/edchttp://www.intel.com/embedded/edchttp://www.intel.com/embedded/edchttp://www.intel.com/embedded/edc


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Authors

Lori M. Matassa is a Software Technical Engineer with Intel.

Acronyms

AMP Asymmetric Multiprocessing

API Application Programming Interface

BIOS Basic Input Output System

CSM Compatibility Support Module

DSP Digital Signal Processing

EDC Intel Embedded Design Center

EDK EFI Developer Kit

EFI Extensible Firmware Interface

GPOS General Purpose Operating System

HA High Availability

IA Intel Architecture

IEGD Intel Embedded Graphics Driver

ISN Intel Software Network

JTAG Joint Test Action Group

LSB Least Significant Bit

OS Operating System

PCI Peripheral Component Interconnect

POSIX Portable Operating System Interface

PPC PowerPC

QoS Quality of Service

RTOS Real-time Operating System

SIMD Single Instruction, Multiple data

SMP Asymmetric Multiprocessing

SSE Streaming SIMD ExtensionsUEFI Unified EFI Forum

VM Virtual Machine

VMM Virtual Machine Manager


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LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL

PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTELS TERMS

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Intel may make changes to specifications and product descriptions at any time, without notice.

This paper is for informational purposes only. THIS DOCUMENT IS PROVIDED "AS IS" WITH NO

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NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE

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Unless otherwise agreed in writing by Intel, the Intel products are not designed for nor intended

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Designers must not rely on the absence or characteristics of any features or instructions marked

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Contact your local Intel sales office or your distributor to obtain the latest specifications and

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Intel literature may be obtained by calling 800-548-4725 or by visiting Intels website.

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Copyright 2009, Intel Corporation. All rights reserved.

ppc to intel arch migration

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