ppt-2 intro to comp

8/3/2019 PPT-2 Intro to Comp

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Introduction to Microprocessor


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Micro-Operations

A computer executes a program Fetch/execute cycle

Each cycle has a number of steps

Called micro-operations

Each step does very little

Atomic operation of CPU


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Types of Micro-operation

Transfer data between registers Transfer data from register to external

Transfer data from external to register

Perform arithmetic or logical ops


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Structure - Top Level

Computer

Main

Memory

Input

Output

Systems

Interconnection

Peripherals

Communication

lines

CentralProcessing

Unit

Computer


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Structure - The CPU

Computer Arithmeticand

Login Unit

Control

Unit

Internal CPU

Interconnection

Registers

CPU

I/O

Memory

SystemBus

CPU


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Basic Elements of Processor

ALU Registers

Internal data pahs

External data paths

Control Unit


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Organization of A Microprocessor-based System (Computer)

CPU Central Processing Unit Memory

ROM Read Only Memory RAM Random Access Memory

I/O Keyboard Display Device

Clock Square Wave Oscillator (Timing) System Bus


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Microprocessor (CPU)Programmable integrated device (silicon chip) that has

computing & decision making capabilities

Communicates & operates in binary numbers 0 & 1,called bits

Has a fixed set of instructions in the form of binarypatterns machine language

Difficult for humans to remember machine language each instruction is represented using abbreviated names(mnemonics)


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MemorySymbolic representation

0000

0001

FFFF

FFFE

64KByte

8 bit

Instruction 1

Instruction 2

Instruction 2

Word: no. of bits micro-Precognizes and processes at a time

( 4 - 64bit ). Instruction: combination of bit

patterns with specific meaningknown to micro-P.

Program: Set of all instructions.address

Word length

1 word instruction

2 word instruction


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I/O

Microprocessors connection to the outsideworld

Input: Keyboard, mouse

Output: Monitor, printer


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System Bus wires connecting memory &I/O to microprocessorAddress Bus

Unidirectional

Identifying peripheral or memory location

Data Bus Bidirectional

Transferring data

Control Bus

Synchronization signals

Timing signals Control signal


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Actions performed by microprocessor:CPU Memory

CPU I/O

Data Processing

Arithmetic operations

Logical operations

Control

Jump

Interrupts


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Basic Concepts of Microprocessors

Differences between:

Microcomputer a computer with a microprocessor as itsCPU. Includes memory, I/O etc.

Microprocessor silicon chip which includes ALU, registercircuits & control circuits

Microcontroller silicon chip which includes microprocessor,memory & I/O in a single package.


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Differences between: High level language

Assembly language

Machine language

C compiler Assembler

swap (int v[], int k){int temp;

temp = v[k];v[k] = v[k+1];v[k+1] = temp;

}

swap;muli $2, $5,4add $2, $4,$2lw $15, 0($2)lw $16, 4($2)

00011100011100

01111000011100

11110000111001

01101011001001

High LevelLanguange (in C)

AssemblyLanguange

MachineLanguage


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Fetch - 4 Registers

Memory Address Register (MAR)Connected to address bus

Specifies address for read or write op

Memory Buffer Register (MBR)

Connected to data bus

Holds data to write or last data read

Program Counter (PC)

Holds address of next instruction to be fetched

Instruction Register (IR)

Holds last instruction fetched


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Functions of Control Unit

SequencingCausing the CPU to step through a series of

micro-operations

Execution

Causing the performance of each micro-op

This is done using Control Signals


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Control Signals

ClockOne micro-instruction (or set of parallel micro-instructions) per clock cycle

Instruction registerOp-code for current instruction

Determines which micro-instructions areperformed

FlagsState of CPU

Results of previous operations

From control busInterrupts

Acknowledgements


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Model of Control Unit


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FetchSequence

Address of next instruction is in PC Address (MAR) is placed on address bus

Control unit issues READ command

Result (data from memory) appears ondata bus

Data from data bus copied into MBR

PC incremented by 1 (in parallel with data

fetch from memory) Data (instruction) moved from MBR to IR

MBR is now free for further data fetches


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Intel 8085 Microprocessor

Microprocessor consists of:Control unit: control microprocessor operations.

ALU: performs data processing function.

Registers: provide storage internal to CPU.

Interrupts

Internal data bus


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Intel 8085 CPU Block Diagram

ALU


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Intel 8085 Pin

Configuration


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RegistersGeneral Purpose Registers

B, C, D, E, H &L (8 bit registers)

Can be used singly

Or can be used as 16 bit register pairs+BC, DE, HL

H & L can be used as a data pointer (holds memory

address)Special Purpose Registers

Accumulator (8 bit register)+Store 8 bit data

+Store the result of an operation

+Store 8 bit data during I/O transfer


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Flag Register

8 bit register shows the status of the microprocessor

before/after an operation S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity

flag) & CY (carry flag)

Sign Flag

Used for indicating the sign of the data in the accumulator

The sign flag is set if negative (1 negative)

The sign flag is reset if positive (0 positive)

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY


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Zero Flag

Is set if result obtained after an operation is 0

Is set following an increment or decrement operation of thatregister

Carry Flag Is set if there is a carry or borrow from arithmetic operation

10110011

+ 01001101

---------------

1 00000000

10110101

+ 01101100

---------------

Carry 1 00100001

10110101

- 11001100

---------------

Borrow 1 11101001


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Auxillary Carry Flag Is set if there is a carry out of bit 3

Parity Flag

Is set if parity is even

Is cleared if parity is odd

10110101

+ 01101100

---------------

1 00100001


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16 Bit RegistersProgram Counter

A pointer to the next instruction to be executed

Contains the 16-bit memory address of the next instruction

Updated after processor has fetched the instruction

Stack Pointer

Stack an area in memory in which temporary info isstored

Stack FILO (First In Last Out) basis

Holds the address of the top of the stack


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Non Programmable Registers

Instruction Register & Decoder

Instruction is stored in IR after fetched by processor

Decoder decodes instruction in IR

Internal Clock generator 3.125 MHz internally

6.25 MHz externally


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Microprocessor 8085 pin Configuration

Intel 8085 is an 8 bit,. It is a 40 pin IC package fabricated on asingle LSI.

Description of various pins:

1. A8-A15(Output): These are address bus and are used for theMSB of the memory address. or I/O address.

1. ADo-AD7 (Input / Output): These are time multiplexed address/ data bus i.e. they serve dual purpose. They are used for the LSBof the memory address. or I/O address during the first clock cycleof the machine cycle. They are used as data during the second andthird clock cycle of the machine cycle.

1. ALE (Output): It is an address latch enable signal. It goes highduring the first clock cycle of the machine cycle and enables thelower 8 bits of the address to be latched either into the memory orexternal latch.


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4. IO/M (Output): It is a status signal which distinguisheswhether the address is for memory or I/O. When it goeslow the address in the address bus is for the memory.

5. So,S1(Output): These are status signals sent by the

microprocessor to distinguish the various types ofoperation given .1. 0,0 - Halt2. 0,1 - write3. 1,0 - Read4. 1,1 - Fetch

___

6. RD(Output): It is a signal to control READ operation.When it is low the selected memory or I/O device is read.


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7. WR (Output): It is a signal to control WRITE operation.When it is low the data on the data bus is written intothe selected memory or I/O device.

8. READY (Input) It is used by the microprocessor to

check whether the peripherals is ready to transfer data ornot. If READY is high the peripheral is ready. If it is lowMP waits for the signal to goes high.

9. HOLD (Input): It indicates that another device isrequesting the use of the address and data bus. Havingreceived a HOLD request the MP relinquishes the use ofthe buses as soon as current machine cycle is completed.

10. HLDA (output): It is a signal for HOLDacknowledgement. It indicates that the HOLD requesthave been received.


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11. INTR (input): It is an interrupt request signal. Among interruptsit has lowest priority. When it goes high the program counter doesnot increment its contents. The microprocessor suspends itsnormal sequence of operations. After completing the instruction athand it goes to the call instruction. The INTR line is sampled in thelast state of the last machine cycle of the instruction. Themicroprocessor acknowledges the interrupt signal and issues INTA

signal.

12. RST5.5.6.5.7.5 and TRAP (inputs): These are interrupts. Whenan interrupt is recognized the next instruction is executed from afixed location in the memory as given below:

1. TRAP 00242. RST5.5 002C

3. RST6.5 0034

4. RST7.5 003C

RST 7.5,6.5.5.5are the restart interrupts. They cause aninternal restart to be automatically inserted. Each of them has aprogrammable mask. The TRAP has the highest priority amonginterrupts. It is a nonmaskable interrupts. It is unaffected by anymask or interrupt. The priority of the interrupts is in the order ofTRAP(Highest) , RST7.5. RST6.5, RST5.5, INTR.


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13. RESET IN (Input): It resets the program counter to zero. It

also resets the interrupt enable and HLDA flip-flops. It does noteffect any other flag or register except the instruction register,The CPU is held in reset condition as long as RESET is applied.

14. RESET OUT (Output): It indicates that the CPU is being reset.

15. X1, X2: (Input): These are terminals to be connected to an

external crystal oscillator which drives an internal circuitry ofthe microprocessor to produce a suitable clock for the operationof microprocessor.

16. CLK : It is a clock output for user, which can be used for otherdigital ICs Its frequency is same at which processor operates.

17. SID (Input) It is data line for serial input.18. SOD (Output): it is a data line for serial output.

19. VCC: +5 Volts Supply

20. VSS: Ground Reference


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The 8085 Machine Cycle and Bus Timings

An instruction is a command given to a computer to perform aspecified operation on the given data. To perform a particular task aprogrammer writes a sequence of instructions, called a program.Program and data are stored in the memory. The processor fetchesone instruction from the memory at a time and execute it. Itexecutes all the instructions of the program one by one and producethe final result.

Instruction Cycle The necessary steps which a processor carries out

to fetch an instruction and data from the memory and to execute thatinstruction constitute and instruction cycle.

An instruction cycle consist of two steps Fetch cycle and Executecycle. In the fetch cycle the processor fetches the instruction fromthe memory. The necessary steps which are carried out to get dataand perform the specific operation given in the instruction constitutea execute cycle.

IC = FC + EC


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Op-code & Operand Each instruction contains two

parts Operation Code (Opcode) and Operand. The

first part of the instruction which specifies a task to

be performed by the processor is called Opcode. Thesecond part of the instruction is the data to be

operated upon is called Operand.


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Instruction and Data Flow

Instruction

RegisterMDR

Instruction Decoder----------------------------------

ControlProgramCounter MAR

Memory

Data Bus

Memory

Address

Bus


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Addressing Modes of MP 8085

Each instruction performs an operation on the specified data called operand. An

operand must be specified for an instruction to be executed. The operand maybe in the general purpose register, accumulator or in a memory location. Theway in which the operand is specified for an instruction is called addressingmode. Various addressing modes used in MP 8085 are:

1. Direct Addressing2. Register Addressing3. Register Indirect Addressing4. Immediate Addressing.

5. Implicit Addressing

Direct addressing: In this mode of addressing the address of the operand(data) is given in the instruction itself. For example:

1. STA 2400H: Store the content of the accumulator to memory location 2400H.2. IN 02: Read data from port C , 02 is the address of the port C of an I/O port from

where data is to be read.

Register Addressing: In register addressing mode the operands are in thegeneral purpose registers. For example:

1. MOV A,B: This instruction moves the contents of register B to register A orAccumulator.

2. ADD B: Add the contents of register B to accumulator.


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Register indirect addressing: In this mode of addressing the address of

the operand (data) is specified by a register pair. For example:1. LXI H, 2500H: Load HL pair with 2500H.

MOV A,M : Move the contents of memory location whose address is given in HLpair to the accumulator.

HLT: Stop the program.In this program MOV A,Mis the example of Register Indirectaddressing.

2. LXI H, 2500H: Load HL pair with 2500H.ADD M : Add the contents of memory location whose address is given in HL

pair to the accumulator.HLT: Stop the program.In this program ADD ,Mis the example of Register Indirect addressing.

Immediate Addressing: In immediate addressing mode the operandsare specified within the instruction itself. For example:

1. MVI A,05 : Move 05 in the Accumulator.2. ADI 06 : Add 06 to the contents of the accumulator.

Implicit Addressing: There are certain instructions which operate on thecontent or the Accumulator directly, these instructions do not require theaddress of the operands. For example

1. CMA : Compliment the contents of the Accumulator.2. RAR : Rotate the contents of the accumulator right by one bit.3. RAL : Rotate the contents of the accumulator left by one bit.


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The steps which MP8085 takes to fetches machine codes from the memory can beunderstood with the help of the command MOV C,A (4F) stored at memorylocation 2005H :

1. The program places the 16 bit address on the address bus. At time T1 the high orderaddress 20H is placed on the address line A15-A8, the low order memory address05H is placed on the data bus AD7-AD0 and the address latch signal goes high.Similarly the status signal IO/M goes low, indicating that this is memory relatedoperation.

2. The control unit sends the control signal RD to enable the memory chip. This signalis sent out during the clock period T2, thus enabling the memory chip. The RDsignal is active during two clock periods.

3. The byte from the memory location is placed on the data bus. When the memory isenabled the instruction byte (4F) is placed on the bus AD7-AD0 and transferred tothe microprocessor.

4. The byte is placed in the instruction decoder of the microprocessor, and the task is

carried out. The machine code 4F is decoded by the instruction decoder and thecontents of the accumulator are copied into the register C. This task is performedduring the period T4


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The 8085 Machine Cycle and Bus Timings (cont..)

Example :- In MP8085 we have two machine codes 3EH ( MVI A, data) and32H are stored at memory location 2000H and 2001H respectively. Illustrate

the bus timing . Calculate the required time to execute the Opcode Fetch and

Memory Read cycles and the entire instruction cycle if the clock frequency is

2 MHzs.

Ans :- This instruction consists of two bytes; the first op-code and the second

is the data byte. The MP reads these bytes from the memory and thus requires

at least two machine cycles. The first machine cycle is the Opcode fetch and

the second machine cycle is the memory read .


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First machine cycle M1:-

At T1 microprocessor places the memory address 2000H from thePC on the address bus. 20H on the A15-A8, and 00H on the busAD7-AD0. The ALE signal goes high during T1. which is used tolatch the low order address 00H to AD7-AD0. The status signals areS1 = 1, S0=1

At T2 the MP asserts the RD control signal, which enables the

memory, and memory places the byte 3EH from location 2000H onthe data bus.

During T3 the MP places the opcode in the instruction register anddisables the RD signal . The fetch cycle is completed in state T3

During T4 the instruction is decoded


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Second machine cycle M2:-

At T1 microprocessor places the memory address 2001H from the

PC on the address bus. 20H on the A15-A8, and 01H on the bus

AD7-AD0. The ALE signal goes high during T1. which is used to

latch the low order address 00H to AD7-AD0. The status signals are

S1 = 1, S0=0

At T2 the MP activates the data bus as the input bus, memory placesthe data byte 32H on the data bus.

During T3 the MP reads and store the byte in accumulator.


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The execution time

Clock frequency f = 2 Mz

T- state = Clock Period = 1/f = 0.5 s

Execution time for fetch cycle = 4 X .5 = 2 s

Execution time for Memory Read = 3 X .5 = 1.5 s

Execution time for the instruction = 3.5 s


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The 8085 Machine Cycle and Bus Timings (cont..)

Example :- In MP8085 explain the machine cycle for the instruction STA 2065(32H,65,20). The machine codes are stored at the memory locations 2010H,2011H, 2012H.

Ans :- This instruction consists of three bytes; the first op-code and thesecond and the third are the address of the memory location. This instructionstores the contents of the accumulator in the memory location 2065H. Itconsists of 4 machine cycles.

1. First machine cycle M1:-In the first machine cycle the MP places the address 2010 on the address bus and

fetches the opcode 32h. It requires 4T states.2. Second machine cycle M2:-

In the second machine cycle the memory is read. The processor places the address2011 and gets the low order byte 65H. It requires 3T states.

3. Third machine cycle M3:-The third machine cycle is also the Memory Read cycle. The processor gets the high

order byte 20H from the memory location 2012. It requires 3 T states

4. Forth machine cycle M4 :-The last machine cycle is the memory write . The MP places the address of 2065H on

the address bus, identifies the operation as Memory Write ( S1=0, S0=0 ). It placesthe contents of the accumulator on the data bus AD7-AD0 and asserts the WR signal.During the last T state the contents of the data bus are placed in memory location2065H. It requires 3T states.


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Instruction Set of 8085

An instruction is a command given to the computer to

perform a specified operation on given data.

The 8085-instructions are classified into five group:

1. Data Transfer Group

2. Arithmetic Group3. Logical Group

4. Branch Control Group

5. I/O and Machine Control Group


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Data Transfer Group

Related with moving data from one place toanother.

Not be mistaken as the idea that data is literally

moved, instead it is copied from one location to

another.

This particular type of instruction set does not

modify data.


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Data Transfer Group (Contd.)

Instructions related with this category perform

the following transfers:

Load data from memory into microprocessor.

Store data from the microprocessor into memory.

Move data within the microprocessor. Input data to the microprocessor.

Output data from the microprocessor.


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MOV r, M.Move the content of memory location, whose address is in H-L

pair, is moved to register r.

MOV M, r.The content of register r is moved to the memory location

addresses by H-L pair.


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MVI r, data.Move immediate data in the register r.

MVI M, data.

The data is moved to memory location whose address is in H-L

pair

LXI rp, data (16-bits)

Load the register pair with 16-bits data.


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LDA addr.

The content of the memory location, whose address is specified by the 2nd

and 3rdbytes of the instruction; is loaded into the accumulator.

STA addr.

The content of accumulator is stored in the memory location whose address

is specified by the 2nd and 3rdbytes of the instruction.


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LHLD addr.

The content of the memory location, whose address is specified by the 2nd

and 3rdbytes of the instruction is loaded into register L, the content of next

memory location is loaded into register H.

SHLD addr.

The content of the register L is stored in the memory location whose

address is specified by the 2nd and 3rdbytes of the instruction, the content of

register H is stored in the next memory location.


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LDAX rp.

The content of memory location, whose address is in the register pairrp, is

loaded into the accumulator.

STAX rp.

The content of the accumulator is stored in the memory location whose

address is in the register pairrp.

XCHG.The contents of H-L pair are exchanged with contents of D-E pair.


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Arithmetic Group

Related with performing arithmetic operations.

This particular type of instruction set modify data.

The operations are:-

Addition

SubtractionIncrement

Decrement


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ADD r.The content of registerris added to the content of the accumulator, and thesum is placed in the accumulator.

ADD M.

The content of the memory location addressed by H-L pair is added to thecontent of the accumulator.

ADC r.

The content of registerrand carry status are added to the content of theaccumulator.

ADC M.

The content of the memory location addressed by H-L pair and carry statusare added to the content of the accumulator.


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ADI data.The immediate data is added to the content of the accumulator.

ACI data.

The immediate data and the carry status are added to the contentof the accumulator.

DAD rp.

The contents of register pairrp are added to the contents of H-Lpair and the result is placed in H-L pair.


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SUB r.The content of registerris subtracted from the content of the

accumulator, and the result is placed in the accumulator.

SUB M.

The content of the memory location addressed by H-L pair issubtracted from the content of the accumulator.

SBB r.The content of registerrand carry status are subtracted from the

content of the accumulator. SBB M.The content of memory location addressed by H-L pair and carry

status are subtracted from the content of the accumulator.


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SUI data.The immediate data is subtracted from the content of the

accumulator.

SBI data.

The immediate data and carry status subtracted from the contentof the accumulator.

INR r.The content of registerris incremented by one.

INR M.The content of memory location addressed by H-L pair is

incremented by one.


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DCR r.The content of registerris decremented by one.

DCR M.The content of memory location addressed by H-L pair is

decremented by one.

INX rp.The content of register pairrp is incremented by one.

DCX rp.

The content of register pairrp is decremented by one.


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DAA.

This instruction is used in the program after ADD, ADI, ACI,

ADC, etc instruction. After the execution of ADD, ADC, etc

instruction the result is in hexadecimal and it is placed in the

accumulator. This instruction operates on this result and gives the

final result in decimal system.


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Logical Group

Instructions in this group performAND,OR, Ex-Or operations;compare,rotate,or take complement ofdata in register or memory.


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ANA r.->(AND register with accumulator.)

It contents of register are ANDed with the content of the accumulator, and

the result is placed in the accumulator.

ANA M.-> (AND memory with accumulator. ) Contents of memorylocation addressed by H-L pair and is ANDed with the accumulator. The

result is placed in accumulator.


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ANI data(AND immediate data with accumulator )

The 2ndbyte of instruction is data, and it is ANDed with the content of the

accumulator. The result is placed in accumulator.

ORA r (OR) register with accumulator.Contents of registered are ORed with content of accumulator. The result is

placed in the accumulator.


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ORA M.-> (OR memory with accumulator. )Contents of memory location addressed by H-L pair and is ORed with the

accumulator. The result is placed in accumulator.

ORI data (OR immediate data with accumulator )The 2ndbyte of instruction is data, and it is ORed with the content of the

accumulator. The result is placed in accumulator. CS=0 and AC=0.


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XRA r (Ex-OR) register with accumulator.Contents of registered are Ex-ORed with content of accumulator. The result

is placed in the accumulator.

XRA M.-> (Ex-OR memory with accumulator. )Contents of memory location addressed by H-L pair and is Ex-ORed with

the accumulator. The result is placed in accumulator.


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XRI data (Ex-OR immediate data with accumulator )The 2ndbyte of instruction is data, and it is Ex-ORed with the content of

the accumulator. The result is placed in accumulator.

CMA (Compliment the accumulator)1s compliment of accumulator is obtained and result is placed in

accumulator. To obtain the 1s compliment of a binary number 1 is

replaced by 0 or 0 by 1.


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CMC (Compliment the carry status)CS flag is complimented. other flags are not affected.

STC (Set carry status)

Status flag CS is set to 1. Other flags are not affected.


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CMP r.The content of registerris subtracted from the content of the

accumulator and the status flags are set according to the result of

the subtraction. The content of accumulator remains unchanged.

CMP M.The content of memory location addressed by H-L pair is

subtracted from the content of the accumulator and the status

flags are set according to the result of the subtraction. The

content of accumulator remains unchanged.


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CPI data.The 2ndbyte of the instruction is data, and it is

subtracted from

the content of the accumulator. The status flags are setaccording

to the result of subtraction. But the result is discarded.


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RRC.The content of the accumulator is rotated right by one bit. The

zero bit of the accumulator is moved to carry bit as well as to

the seventh bit of the accumulator.

RAL.The content of the accumulator is rotated left one bit through

carry. The seventh bit of the accumulator is moved to carry and

the carry bit is moved to the zero bit of the accumulator.


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RRC.The content of the accumulator is rotated right one bit through

carry. The zero bit of the accumulator is moved to carry bit, and

the carry bit moved to seventh bit of the accumulator.


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Branch Group

The instructions of this group change the normal sequence

of the program. There are two types of branch instructions:

Conditional

Unconditional


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JZ addr (label).The program jumps to the instruction specified by the address

(label) if the result is zero. Here the result after the execution of

the preceding instruction is under consideration.

JNZ addr (label).The program jumps to the instruction specified by the address

(label) if the result is non-zero.

JC addr (label).The program jumps to the instruction specified by the address

(label) if there is a carry.


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JNC addr (label).The program jumps to the instruction specified by the address

(label) if there is no carry.

JP addr (label).The program jumps to the instruction specified by the address(label) if the result is plus.

JM addr (label).The program jumps to the instruction specified by the address

(label) if the result is minus.


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JPE addr (label).The program jumps to the instruction specified by the address

(label) if the result contains even number of 1s.

JPO addr (label).The program jumps to the instruction specified by the address

(label) if the result contains odd number of 1s.


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CALL addr (label).[[SP]-1] [PCH]

[[SP]-2] [PCL]

[SP] [SP]-2

[PC] addr (label)CALL instruction is used to call a subroutine. Before the control

is transferred to the subroutine, the address of the next instruction

of the main program is saved in the stack.


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Conditional CALL addr (label) Addressing: immediate/ reg. indirect. Machine cycles:2/5. If the

condition is true and program calls the specified subroutine, the

execution of a conditional call instruction takes 5 machine cycle; 18states. If condition is not true, only 2 machine cycles; 9 states arerequired for the execution of the instruction.

i. CC addr(label) call subroutine if carry status CS=1.ii. CNC addr(label) call subroutine if carry status CS=0iii. CZ addr(label) call subroutine if result=0; i.e zero status Z=1iv. CNZ addr(label) call subroutine if result is not zero. Z=0

v. CP addr(label) call subroutine if result is plus; the sign signalstatus S=0.vi. CMaddr(label) call subroutine if result is minus; the sign signal status

S=1.vii. CPE addr(label) call subroutine if even parity; the parity status

P=1.viii. CPO addr(label) call subroutine if odd parity; the parity status

P=0.


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RET (Return from subroutine)

[PCL]


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Conditional Return [PCL]


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RST n (Restart)

[[SP]-1]


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RST5 EF 0028

RST6 F7 0030

RST7 FF 0038


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PCHL (Jump to address specified by HL pair)

[PC]


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Stack, I/O and Machine Control Group

IN port-address. (Input to accumulatorfrom I/O port)[A]


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OUT port address. (O/P from accumulator to I/O

port.)

[Port]


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p ( g p

stack)

[[SP-1]


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PUSH PSW (Push processor status word)

[[SP]-1]


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Interrupts in Microprocessor 8085

The primary function of the MP are:

To accept the data from input devices such askeyboard and A/D converters.

Read instructions from memory.

Process data according to the instructions.

Send results to the output devices such as LEDsprinters and monitors.


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These I/O devices are called either peripherals or I/Os.Designing logic circuits (hardware) and writinginstructions (software) to enable MP to communicatewith these peripherals is called interfacing and the logiccircuits are called I/O ports or interfacing devices.

The microprocessor communicates with the peripheralsin either or two formats.

Asynchronous means at irregular intervals. It has a lowspeed data transmission

Synchronous means at the same time the transmitter andreceiver are synchronized with the same clock. It used for

high speed data transmission

Interr pts in Microprocessor 8085 (cont )


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Interrupts in Microprocessor 8085 (cont)

The interrupt is a process of data transfer

whereby an external device or aperipheral can inform the processor that itis ready for communication and itrequests attention. The process is initiated

by an external device and is asynchronousi.e. can be initiated at any time withoutreference to the system clock. Theresponse to the interrupt is controlled by

the microprocessor.


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The interrupt request can be classifiedinto two categories maskable and nonmaskable .

Intel 8085 has five interrupts in thepriority order :1. TRAP

2. RST 7.5

3. RST 6.5

4. RST 5.5

5. INTR

Interrupts in Microprocessor 8085 (cont )


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In MP 8085 the interrupt process is controlled by

the Interrupt Enable flip-flop, which is internal tothe processor and can be set or reset usingsoftware instructions. The working of theseinterrupts can be described as

1. The interrupt process is enabled by writing an instruction

EI in the main program. The instruction EI sets theInterrupt Enable flip flop. The instruction DI resets theflip flop and disables the interrupt process except nonmaskable interrupt TRAP .

2. When the MP is executing a program, it checks the INTR

line during the execution of each instruction.


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3. If the INTR is high and the interrupt is enabled, theMP completes the current instruction, disables theinterrupt Enables flip flop and sends a signal calledINTA interrupt acknowledge. The processor cannotaccept any interrupt requests until the interrupt flipflop is enabled again.

4. The signal INTA is used to insert a restart (RST)instruction (or a call instruction) through externalhardware. The RST instruction is a 1 byte instructionthat transfers the program control to a particularlocation and restarts the execution at the memory

location after executing step 5.5. When the MP receives an RST instruction (or CALL

instruction)



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Hardware and Software interrupts:

Interrupts caused by I/O devices are called hardware interruptse.g. TRAP, INTR

The normal operation of the MP can also be stopped by specialinstruction, such instructions are called software interrupts e.g.RST n when RST n instruction is inserted in a program , theprogram is executed up to that point where RST n has beeninserted.

Interrupt call locations:

When an interrupt occurs the program is transferred to a specificmemory location. Then the monitor transfers the program fromthe specific memory location to a memory location in the memoryin RAM , from where the user can write the program for interruptsub routine . For TRAP , RST 7.5, 6.5,and 5.5 the program is

automatically transferred to specific memory locations without anyexternal hardware. The necessary hardware is already providedwithin 8085. An interrupt for which hardware automaticallytransfers the program to a specific memory location isknown as vectored interrupts.The specific memory location forthese interrupts are as follows.


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Interrupt Call Location

TRAP 0024H

RST 7.5 003CH

RST 6.5 0034H

RST 5.5 002C

I t t i Mi 8085 ( t )


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INTRCall location:There are 8 number of call locations for INTR interrupt

as shown in the table below:

RST n Call Location RST n Call Location

RST 0 0000 RST 4 0020

RST 1 0008 RST 5 0028

RST 2 0010 RST 6 0030

RST 3 0018 RST 7 0038


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For INTR external hardware is used to transfer program to

specific CALL location. The hardware circuit generates RSTcodes for the purpose. The INTR line is sampled by the MPin the last state of the last machine cycle of eachinstruction. When INTR is high the MP saves the contentsof the program counter on the stack and then sends aninterrupt acknowledge signal INTA to the external

hardware. In response to INTA the external hardwaregenerates a RST n code. When MP receives this code, ittransfers program to the corresponding CALL-location. Upto 8 number of I/O devices can be connected to INTRthrough an external hardware. Priority can be assigned toI/O devices connected to INTR through external hardware

or interrupt controller. The external hardware recognizeswhich I/O device has interrupted and it generates properRST code that causes microprocessor to take up ISS forthat particular I/O device.

ppt-2 intro to comp

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