Practical Aspects of Practical Aspects of Reliability Analysis for IC Reliability Analysis for IC DesignsDesigns

Practical Aspects of Practical Aspects of Reliability Analysis for IC Reliability Analysis for IC DesignsDesigns

T. Pompl, C. Schlünder, M. T. Pompl, C. Schlünder, M. Hommel, Hommel,

H. Nielen, J. SchneiderH. Nielen, J. Schneider

PurposePurpose

Address practical links between IC design and Address practical links between IC design and reliability of IC operation. reliability of IC operation.

Demonstrate state of the art aspects as well as Demonstrate state of the art aspects as well as future issues.future issues.

Direct input of experts working in the field of Direct input of experts working in the field of process reliability and ESD.process reliability and ESD.

What’s required in EDA tools to What’s required in EDA tools to promote design-in reliability? promote design-in reliability?

OutlineOutline

Gate oxide integrityGate oxide integrity

Device reliabilityDevice reliability

Interconnect reliabilityInterconnect reliability

Electrostatic discharge (ESD)Electrostatic discharge (ESD)

SummarySummary

Gate oxide integrity:Gate oxide integrity:Overshoot eventsOvershoot events

Each electric stress consumes oxide lifetime; Each electric stress consumes oxide lifetime; degradation is cumulative!degradation is cumulative!

Main driver of degradation is the Main driver of degradation is the voltage dropvoltage drop across gate oxide (other driver: temp., active area).across gate oxide (other driver: temp., active area).

Statistical Statistical nature: qualified for e.g. <10 ppm failure nature: qualified for e.g. <10 ppm failure @[Vdd, 10 y, 10 mm@[Vdd, 10 y, 10 mm22, 100°C]., 100°C].

Voltage overshoot is an Voltage overshoot is an additionaladditional electric stress. electric stress.

Analysis of voltage overshoot between Analysis of voltage overshoot between any any terminal and gateterminal and gate (guideline: > 10% of Vdd). (guideline: > 10% of Vdd).

NeededNeeded: voltage amplitude, duty cycle, device : voltage amplitude, duty cycle, device type, terminals (e.g. gate and drain).type, terminals (e.g. gate and drain).

Gate oxide integrity:Gate oxide integrity:New definition of GOX failure criteriaNew definition of GOX failure criteria

To be used for ultra-thin SiOTo be used for ultra-thin SiO22-based oxides; high-k?-based oxides; high-k?

Consequences: Consequences: addsadds gate leakage and gate noise. gate leakage and gate noise. Digital designs: OK.Digital designs: OK. AnalogAnalog designs: my not tolerate this. designs: my not tolerate this.

log(gate leakage)

log(time)

log(gate leakage)

log(time)

Traditional criterion: Traditional criterion:

11stst soft breakdown (SBD) = soft breakdown (SBD) = 11stst irreversible local leakage irreversible local leakage path across the gate oxide.path across the gate oxide.

Future criterion: Future criterion:

11stst SBD reaching a certain SBD reaching a certain absolute current level.absolute current level.

t

Gate oxide integrity:Gate oxide integrity:New definition of GOX failure criteriaNew definition of GOX failure criteria

Circuit simulation of NOR gate withCircuit simulation of NOR gate with SBDSBD between gate/source and gate/drain. between gate/source and gate/drain.

1.55 1.60 1.65 1.70

0.250.500.751.00

no SBDlow level SBD

high level SBD

C

DF

delay between selected output transitions (ns)

0.02 0.03 0.04 0.05

0.250.500.751.00

no SBD

low level SBD

high level SBD

rise

CD

Frise or fall time (ns)

0.250.500.751.00

high level SBDlow level SBDno SBD fall

CD

F

5000 5000 Monte CarloMonte Carlo runs: runs: Up to 8 SBD on/off.Up to 8 SBD on/off. Device parameter Device parameter

variation.variation.

SBD withSBD with low & high low & high gate leakage level.gate leakage level.This is a worst case This is a worst case study; realistic is study; realistic is one one SBD.SBD.

OK for low level SBDOK for low level SBD

Device reliability:Device reliability:Increasing challengeIncreasing challenge

2 4 6 8 104

5

6

7

T13

ITRS 2005 - predictionprocess development

T12T11

T10

T9

T8

0.065µm 0.18µm 0.35µm

Technology-node

EO

X [

MV

/cm

]

EOTelec

in inversion [nm]

Process evolution will Process evolution will lead to higher device lead to higher device stress.stress.Reliability safety Reliability safety margins decreases in margins decreases in modern technologies.modern technologies.

Electric field across gate oxideElectric field across gate oxide

Designers have to be supported by smart soft-Designers have to be supported by smart soft-ware tools with build-in reliability know how!ware tools with build-in reliability know how!

Circuit reliability is not longer a task only for tech-Circuit reliability is not longer a task only for tech-nology development but also for circuit designers.nology development but also for circuit designers.

Device reliability:Device reliability:Full-custom designFull-custom design

Reasonable for relatively low numbers of transistors Reasonable for relatively low numbers of transistors (analog / RF circuits).(analog / RF circuits).

Circuit simulators with built-in reliability can simulate Circuit simulators with built-in reliability can simulate entire circuit blocks. entire circuit blocks.

Based on models parameter Based on models parameter degradation for each device can be degradation for each device can be calculated.calculated.

Designers can access each device Designers can access each device characteristic to optimize the circuit.characteristic to optimize the circuit.

fresh 10y1y

200 ps

volt

ag

e (V

)

time (ns)

Device reliability:Device reliability:Constrains for semi-custom designConstrains for semi-custom design

For digital applications a more automated design For digital applications a more automated design approach is used.approach is used.

Library elements are placed automatically.Library elements are placed automatically.

Designers don’t know in advance where a single Designers don’t know in advance where a single element is placed. No direct access.element is placed. No direct access.

Thus, it’s difficult to manually determine reasonable Thus, it’s difficult to manually determine reasonable operation conditions for single library elements.operation conditions for single library elements.

A single library element is used in many different A single library element is used in many different sub-circuits, and within, is exposed to a lot of sub-circuits, and within, is exposed to a lot of different applications/operation conditions.different applications/operation conditions.

For all of these combinations a delay-calc. would be For all of these combinations a delay-calc. would be necessary, since digital design is delay driven.necessary, since digital design is delay driven.

Device reliability:Device reliability:On-chip variation (OCV) approachOn-chip variation (OCV) approach

Smart software tools can Smart software tools can check time paths.check time paths.

In the case of time In the case of time conflicts, gates can be conflicts, gates can be replaced by faster ones, replaced by faster ones, but this but this consumes area consumes area & power.& power.

In semi-custom design a completely different In semi-custom design a completely different approach is necessary.approach is necessary.

A possible consideration: calculation of parameter A possible consideration: calculation of parameter degradation as a part of degradation as a part of OCV.OCV.

Stress-induced parameter variation can be Stress-induced parameter variation can be transformed in propagation-delays.transformed in propagation-delays.

D Q

CK

D Q

CK

logic

CLK

Tsetup Thold

Interconnect reliability:Interconnect reliability:Critical layout structuresCritical layout structures

Electromigration Single vias connected to …Single vias connected to … Wide metal lines with …Wide metal lines with … Current flow in downstream direction.Current flow in downstream direction.

Stress-induced voiding Single vias connected to …Single vias connected to … Wide metal plates or slitted plates.Wide metal plates or slitted plates.

Breakdown of Inter-metal dielectric Metal lines with minimum pitch, operated at …Metal lines with minimum pitch, operated at … Maximal potential difference of neighbored lines.Maximal potential difference of neighbored lines.

Interconnect reliability:Interconnect reliability:Analysis of critical structuresAnalysis of critical structures

Geometrical Geometrical dimensions.dimensions.

Electrical operation Electrical operation conditions: conditions: DC-current densityDC-current density DC-pulsesDC-pulses AC-currentAC-current

Other operation Other operation conditions: conditions: duty cycle of duty cycle of

operationoperation temperaturetemperature ……

Example for geometrical Example for geometrical analysisanalysis

sing

le C

A

sing

le V

ia1

sing

le V

ia2

sing

le V

ia3

sing

le V

ia4

sing

le V

ia5

25 mm²40 mm²

54 mm²70.6mm²

128.8 mm²

0,0E+00

2,0E+07

4,0E+07

6,0E+07

8,0E+07

1,0E+08

Single Contacts, Vias

Interconnect reliability:Interconnect reliability:EM – Influence of geometryEM – Influence of geometry

EM life time as function of line width for a single EM life time as function of line width for a single via down-stream structurevia down-stream structure

0,0 0,1 0,2 0,3 0,4 0,5w [µm]

t-5

0 [

a.u

.]

lot 1 lot 2

mininimumdesign width

w

EM life time is limited by EM life time is limited by single vias on wide lines.single vias on wide lines.

By avoiding these structures higher current By avoiding these structures higher current densities could be used for product design.densities could be used for product design.

Interconnect reliability:Interconnect reliability:SIV – Influence of geometrySIV – Influence of geometry

Life time of stress-induced voiding (SIV) as function Life time of stress-induced voiding (SIV) as function of line extension length Lof line extension length L

100

1000

0 0,5 1 1,5 2Line extension length L [µm]

MT

F [

hrs

]

L L

Increasing the Increasing the distancedistance of the single via from the of the single via from the plate increases the SIV life time.plate increases the SIV life time.

Electrostatic discharge (ESD)Electrostatic discharge (ESD)

ESD represents a major threat to ICs.ESD represents a major threat to ICs.

Standard ESD specificationsStandard ESD specifications Human Body Model (HBM)Human Body Model (HBM)

Pre-charged human being touches IC.Pre-charged human being touches IC. VVchargecharge = 2 kV, corresponding to I = 2 kV, corresponding to Imaxmax ~ 1.3 A, pulse width ~ 1.3 A, pulse width

of 150 ns.of 150 ns. Charged Device Model (CDM)Charged Device Model (CDM)

Pre-charged IC discharges via one pin.Pre-charged IC discharges via one pin. 500 V, I500 V, Imaxmax ~ 10-20 A, pulse width 1-2 ns. ~ 10-20 A, pulse width 1-2 ns.

ESD damageESD damage Melting in silicon (diffusions of MOS devices, diodes,…).Melting in silicon (diffusions of MOS devices, diodes,…). Breakdown of gate oxides.Breakdown of gate oxides.

Electrostatic discharge:Electrostatic discharge:ESD and IC designESD and IC design

P1

N1

D1

D2

VDD

VSS

ggnmosESD

Out

2 types of rules2 types of rules DRC like: standard DRC tools with ESD marking layers.DRC like: standard DRC tools with ESD marking layers. Net-oriented: in-house tools for circuit analysis.Net-oriented: in-house tools for circuit analysis.

Lots of ESD rules to be Lots of ESD rules to be followed…followed… Special diodes Special diodes D1D1, , D2D2 in in

place.place. Power clamp Power clamp ggnmosESD ggnmosESD

in place.in place. Output drivers Output drivers N1N1, , P1P1 must must

follow ESD layout rules.follow ESD layout rules. N1N1, , P1P1 must match to the must match to the

supply voltage at VDD.supply voltage at VDD.

Electrostatic discharge: Electrostatic discharge: Design rule check (DRC)Design rule check (DRC)

Detect ESD relevant areas via ESD layer.Detect ESD relevant areas via ESD layer.

Recognize layout of diodes, MOS devices, SCR, …Recognize layout of diodes, MOS devices, SCR, …

Example: drain contact-to-gate spacing aExample: drain contact-to-gate spacing aDD with with silicide blocking.silicide blocking.

Requires some awareness of layouter.Requires some awareness of layouter.

Better: parameterized ESD cells. Better: parameterized ESD cells.

aD

D S

sal. block

Electrostatic discharge: Electrostatic discharge: Net-oriented rule checkingNet-oriented rule checking

Idea: extract netlist from layout and check ESD rulesIdea: extract netlist from layout and check ESD rules Like LVS, take ESD marking layers into account.Like LVS, take ESD marking layers into account. Information on pin types needed, e.g. supply voltages.Information on pin types needed, e.g. supply voltages. Can also be realized on pre-layout netlists.Can also be realized on pre-layout netlists.

Rule typesRule types Existence and connectivity of ESD devices.Existence and connectivity of ESD devices. Matching of device classes and supply voltage classes.Matching of device classes and supply voltage classes.

Examples:Examples: Thin oxide device between Thin oxide device between

power domains (not allowed).power domains (not allowed). Thin oxide cap. at VDD/VSS.Thin oxide cap. at VDD/VSS. Existence of correct power Existence of correct power

clamps.clamps.

thin oxide

thin oxide

VDD2

VSS

VDD1

detecteddevices

Electrostatic discharge: Electrostatic discharge: ESD awareness of future EDA toolsESD awareness of future EDA tools

ESD DRC is OK with existing DRC tools.ESD DRC is OK with existing DRC tools.No commercial tools for No commercial tools for net-orientednet-oriented ESD rules ESD rules available.available. Should be imbedded in design flow.Should be imbedded in design flow. Need for infrastructure: ESD pin types, power domains, Need for infrastructure: ESD pin types, power domains,

ESD endangered interfaces.ESD endangered interfaces. Also for pre-layout-synthesis checks.Also for pre-layout-synthesis checks. Should work on data of a whole IC.Should work on data of a whole IC.

Tool for Tool for IR-drop analysisIR-drop analysis of ESD pulses. of ESD pulses. Find bad metallization, ESD endangered positions on Find bad metallization, ESD endangered positions on

IC,… IC,…

Auto-placement Auto-placement of ESD cells according to some of ESD cells according to some formalized guidelines would be great!formalized guidelines would be great!

SummarySummary

Gate oxide reliabilityGate oxide reliability Identify voltage overshoot events.Identify voltage overshoot events. New gate oxide failure criteria to be considered.New gate oxide failure criteria to be considered.

Device reliabilityDevice reliability Increasing electric field; NBTI becomes design issue.Increasing electric field; NBTI becomes design issue. Simulation using degraded devices: constraints for Simulation using degraded devices: constraints for

semi-custom design OCV approach.semi-custom design OCV approach.

Interconnect reliabilityInterconnect reliability Control via placing to improve EM & SIV.Control via placing to improve EM & SIV. Identify metal line with minimal pitch (TDDB risk).Identify metal line with minimal pitch (TDDB risk).

ESDESD Net-orientated ESD rules, IR-drop analysis.Net-orientated ESD rules, IR-drop analysis. Automated placement of ESD and I/O cells.Automated placement of ESD and I/O cells.