pre-emphasis and equalization parameter optimization with ... · pre-emphasis and channel pulse...

© 2005 Altera Corporation© 2007 Altera Corporation, Mentor Graphics & Molex

Pre-Emphasis and Equalization Parameter Optimization with Fast, Worst-Case/Multibillion-Bit VerificationAndy Turudic, Altera CorporationSteven McKinney, Mentor GraphicsVladimir Dmitriev-Zdorov, Mentor GraphicsVince Duperron, MolexKaren Stoke, Altera Corporation

2© 2007 Altera Corporation, Mentor Graphics & Molex

AgendaAgendaSystem issues when designing high-speed serial interfacesTypical high-speed system interconnect components− FPGA with transceiver− Backplanes− Connectors

Optimizing signal integrity settings for high-speed channels− Estimation and simulation tools and techniques− Advanced vs. conventional simulation techniques

Results


The Right Choice of FPGAs, EDA Tools, and

Interconnects Is Critical to Design Success!

Designing a Robust, High-Speed Serial InterfaceWill it Work? Will it Meet Specifications?Designing a Robust, High-Speed Serial InterfaceWill it Work? Will it Meet Specifications?

Primary concerns for system designers and architects:− Signal integrity – many channels − Reducing system power dissipation− Aggregate bandwidth and line bitrate− Increasing capacity of legacy systems− Bit-error rate (BER)

Design and prototype cycles are expensive and difficult to troubleshoot− Ideally simulate in EDA− Well correlated models and techniques

BER specification of 10E-18 − Can take years to verify sequentially,

requiring extrapolation of bathtub curves


Backplane

Lossy Transmission Lines

Switch OC48 LineCard

Will It Work? Will It Meet Specs? Will I Get Fired?

Typical System with Serial InterfaceTypical System with Serial Interface


Stratix II GX FPGA - Transceiver BlocksStratix II GX FPGA - Transceiver BlocksTransceiver functionality− 8b/10b encoder/decoder− Rate matcher− Phase compensation FIFO− 8,10,16, 20, 32, 40 bit

interface to core

600 Mbps - 6.375 Gbps with analog clock data recovery (CDR)− OC48/STM16 optical jitter

compliant

Pre-emphasis and equalization− With over 5000 settings,

can drive 1.25m FR4


PCIe state machine− Power state sequencing− Electrical idle, receive detect,

and others− Physical interface to PCIe (PIPE)

to core

Gigabit Ethernet state machine− Comma character insertion/deletion− GMII-like interface to core

XAUI state machine− Channel deskew, alignment,

and bonding− XGMII-like interface to core

Transceiver-Based ApplicationsTransceiver-Based Applications


Stratix II GX SI Board DiagramStratix II GX SI Board Diagram6 Full Duplex Transceiver Channels

Routed to SMAs

1 Channel 40” Tx, 5” Rx

4 StriplineTx and Rx Channels

1 Microstrip Channel (Tx) (Rx is stripline)

Power SupplyAC Adapter or Banana Jacks

USB PortPC Interface

User I/Os – LEDs,Pushbuttons, DIP Switch,

7-Segment Displays

Rx Tx Output Clocks(FPGA)

Input Clocks

Trigger Clocks

Input Clocks(FPGA)


Backplane OverviewBackplane Overview

GbX I-Trac

The GbX® Reference Backplane and the I-Trac™ Reference Backplane served as interconnect channels for this study

Three 1m channels were measured;− 1m GbX Backplane 7/7/7 mil construction channel− 1m I-Trac Backplane 6/7/6 mil construction channel− 1m VHP I-Trac Backplane 7/9/7 mil construction channel

GbX is a registered trademark of Amphenol Corporation


Connectors OverviewConnectors OverviewThe GbX® Connector and I-Trac™ Connector

GbX, Edge Coupled I-Trac, Broadside Coupled



SMA Launch OptimizationSMA Launch OptimizationGbX® daughtercards use blind launchesI-Trac™ daughtercards use backdrilled launches

SMA, PCB Interface, and Stripline Insertion and Return Loss



Connector Launch OptimizationConnector Launch OptimizationGbX® Backplane uses a six backdrill depth scheduleI-Trac™ Backplane uses a three backdrill depth schedule

Do nothing, unacceptable in a 6.375Gbps backplane

Note blue curve. This is the insertion loss that results from a top to signal 1 transition if that pin via is backdrilled as deeply as possible. Leave just the barrel required to accommodate the compliant pin.

Three depths are sufficient to equal or better the performance of compliant pin stub.



Connector Launch DesignConnector Launch Design

GbX® PCB interface I-Trac™ PCB interface1m channel

I-Trac PCB interface1m VHP channel

All connectors to PCB Interfaces Use Polygon Antipads and “flag” Escapes



Tdd11 and Sdd11 CurvesTdd11 and Sdd11 Curves

GbX® 1m Channel, Tdd11 I-Trac™ 1m Channel, Tdd11 GbX and I-Trac 1m Channels, Sdd11

GbX 1m I-Trac 1m I-Trac 1m VHP



Sdd12Sdd12GbX® 1m channel (Green)I-Trac™ 1m channel (Blue)I-Trac 1m VHP channel (Red)

BER and Eye-Opening Track Insertion Loss.



Pre-Emphasis and Channel Pulse ResponsePre-Emphasis and Channel Pulse Response

↑ Far-end 1m I-Trac™ pulse responses• No pre-emphasis produces “tail”• Pre-emphasis minimizes pulse distortion↓ Near end pre-emphasized pulse

Far End Composite 1m I-Trac Pulse Responses with Stratix® II GX FPGA

Sweeping Pre-Emphasis


Another Pre-Emphasis TechniqueAnother Pre-Emphasis TechniqueProduce a clock pattern of five ones and five zerosSearch settings until qualitatively “square” waveform


Too Much Pre-Emphasis?Too Much Pre-Emphasis?

Far-End Eyes for a 15-inch GbX® Backplane Channel

0mA 3mA 6mA

Opening

Pre-Emphasis

Curve Shape Is Channel and Bit-Rate Dependent



Altera’s Pre-emphasis & Equalization Link Estimator (PELE)- EDA tool for FAEs to estimate customers’ pre-emphasis and equalization coefficientsAltera’s Pre-emphasis & Equalization Link Estimator (PELE)- EDA tool for FAEs to estimate customers’ pre-emphasis and equalization coefficients

TxModel

TxModel

RxModel

RxModelCustomer Provided S-Parameters

PELE

Backplane

Coefficients


S-Parameters—Not “Scary”S-Parameters—Not “Scary”Can be obtained from a number of sources− Simulated/extracted (yellow), VNA (magenta), iConnect TDR/TDT (red)− Example shows “S21” which is insertion loss for I-Trac™ VHP 1m backplane channel


PELE Estimated Eye from VNA S-Parameter Data

PELE Estimated Eye from SPICE S-Parameter Data

Measured 1m I-Trac™ Eye

PELE Estimations vs. Bench at 6.25 GbpsPELE Estimations vs. Bench at 6.25 Gbps

PELE takes ~3 minutes to runPELE inputs from bench or EDAPELE outputs then control SPICE model


Design kit for use in Mentor Graphics’ HyperLynx signal integrity software− Includes example topologies using Eldo SPICE models from Altera

Customized model configurator for easy model setup− Includes integration with Altera’s PELE tool

Altera Stratix II GX Design KitAltera Stratix II GX Design Kit


Mentor Graphics’ Fast-Eye Diagram Simulation Tool (FEST)—Data FlowMentor Graphics’ Fast-Eye Diagram Simulation Tool (FEST)—Data Flow

Circuit Simulator

Fast-Eye-Diagram Subsystem or

or

or

MeasurementSubsystem

Interconnect Channel

Driver/Receiver Devices

Model of Interconnect

Channel

Driver- and Receiver-IC

Models

Eye-Diagram Contour

BER Bathtub Curve

Worst-Case Stimulus

ChannelS-Parameter

Model

Pulse/Step Response

Built-in Stimulus Generator

Built-in Jitter

Generator

EyeStimulus


Worst-case bit sequence always generates the maximally closed eye− Even beyond what is seen with billions of bits of data

Can be 8b/10b protocol constrained

0 50 100 150 200 250 3000

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0 1,000 2,000 3,000 4,000 5,000 6,0000

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

Bit Rate Bit Rate

Uni

t Int

erva

l

Uni

t Int

erva

l

Worst-Case Bit Sequence and the EyeWorst-Case Bit Sequence and the Eye


There are several different approaches to fast-eye analysis− Statistical analysis− Step and impulse responses are collected and analyzed

using 1 of 2 different techniquesConvolution approach to build the eyeInternal State Variable (ISV) approach to build the eye

Different Methods of FESTDifferent Methods of FEST


Results using the different impulse methods

103

104

105

106

107

108

109

1010

1011

0

0.05

0.1

105 106 107 108 109 1010 1011

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

Uni

t Int

erva

l

Bit Rate104

Different Methods of FESTDifferent Methods of FEST

Internal State Variable

Convolution

8b/10b – 100 billion bits

Unconstrained psuedo-random binary sequence (PRBS) – 100,000 bits

8b/10b – 10 million bits

unconstrained PRBS –10 million bits


-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

10-20

10-15

10-10

10-5

Time offset in UI

Different Methods of FESTDifferent Methods of FESTStatistical analysis provides a bathtub curve of results− Includes both Gaussian and Sinusoidal jitter


0.2 0.3 0.4 0.5 0.6 0.7 0.8

-0.03

-0.02

-0.01

0

0.01

0.02

0.03

Correlation of ResultsCorrelation of ResultsStatistical results versus impulse response with ISV− Eye widths and heights are approximately equal in both cases

Width = ~0.3 UIHeight = ~ 25 mV

-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5-0.06

-0.04

-0.02

0

0.02

0.04

0.06Statistical

ISV


Correlation of ResultsCorrelation of ResultsResults of FEST analysis using ISV with measured vs. simulated step/pulse response− 1 billion bits observed

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-0.1

-0.08

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

0.1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

Measured Simulated


Correlation of ResultsCorrelation of ResultsOverall good correlation between both responsesDifferences are a result of:− Extracted s-parameter data vs. using actual board

data from measurement− Bandwidth limitations of the scope-limited sample size

of pulse and step responses


Correlation ResultsCorrelation ResultsSimulated eye vs. lab measurement− 30,000 samples in scope− 1 billion bits in simulation

Using constrained 8b/10b pattern

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

-0.15

-0.1

-0.05

0

0.05

0.1

0.15


Correlation ResultsCorrelation ResultsOverall good correlation between lab and simulated eye− In the simulated results, the eyes are more closed, but

this is expected based on difference in samples used− Artifacts seen in measurement correlate very closely

to artifacts in simulation


Conclusion (1/2)Conclusion (1/2)Eliminates guesswork for optimal signal integrity settings for high-speed channels− PELE tool estimates pre-emphasis and equalization settings

based upon S-parametersS-parameters extracted from EDA flow or benchEDA models are well correlated to bench measurements

− Integrating PELE allows direct configuration of ELDO/SPICE Models are well correlated to actual devicesReduces errorsEnsures interworking of files, models, and toolsIncreases productivity by reducing simulation iterations


Conclusion (2/2)Conclusion (2/2)Now possible to validate design reliability at billions of bits using EDA tools like the Fast Eye Simulation Tool (FEST)− Faster than traditional time-domain simulations

Nearly identical results with SPICE runs− Worst-case bit sequences can be generated with FEST

Produces condensed test pattern resulting in maximally closed eye

− Designers can have confidence in meeting system design BER targets

Integration of High-density Digital Functions With High Aggregate Capacity Serial

Interconnects Is Possible By Using These Advanced Tools, Interconnects, and FPGAs


For More Information….For More Information….Andy Turudic, Altera Corporation [email protected] McKinney, Mentor Graphics [email protected] Dmitriev-Zdorov, Mentor Graphics [email protected] Duperron, Molex [email protected] Stoke, Altera Corporation [email protected]

www.altera.com

www.mentor.com

www.molex.com


AcknowledgementsThe authors would like to thank Gourgen Oganessyan and David Dunham at Molex; Leonard Dieguez, Tina Tran, Mark Flanigan, Naresh Raman, Venkat Yadavalli, Samson Tam, Sergey Shumarayev, Sarah Adams, James Adams, Kelly St. Denis, Zhi Wong, Jan-Sian Tai, Jeff Holmbeck, James Smith, Michael Woo, Toan Nguyen, Amy Lee, Christine Young and Dave Greenfield at Altera; Gary Pratt at Mentor; and Steve Bright and Eugene Mendeleyev at Tektronix.

ReferencesWilson Wong, Tin Lai, Sergey Shumarayev, Simardeep Maangat, Tim Hoang, Tina Tran, “Digitally Assisted Adaptive Equalizer in 90 nm With Wide Range Support From 2.5 Gbps–6.5 Gbps”. DesignCon 2007

Eric Bogatin, “From Bit-banger to Gigabit Guru”. High Speed Seminar Proceedings CD, Altera Corp, March 2006.

Leonard Dieguez, “High Speed Channel Design”. High Speed Seminar Proceedings CD, Altera Corp, March 2006.

Eric Bogatin, ibid.

Andy Turudic, “Abracadabra: Making system interconnect disappear with FPGAs”. EDN Magazine, Sept. 14, 2006, http://www.edn.com/index.asp?layout=article&articleid=CA6368447&industryid=2284

Tina Tran, Gary Pratt, Kazi Asaduzzaman, Mei Luo, Simar Maangat, Toan Nguyen, Sergey Shumarayev, Kwong-Wen Wei,“Equalization Challenges for 6-Gbps Transceivers Addressed by PELE—A Software-Focused Solution!”DesignCon 2007.

Min Wang, Henri Maramis, Donald Talian, and Kevin Chung, “New techniques for designing and analyzing multi-GigaHertz serial links”. DesignCon 2005.

Bryan K. Casper, Matthew Haycock, Randy Mooney. - Circuit Research, Intel Labs, Hillsboro Oregon, “An accurate and efficient analysis method for multi-Gbs chip-to-chip signaling schemes”. VLSI Circuits Digest of Technical Papers, June 13, 2002, pages 54-57.

Anthony Sanders, Mike Resso, John D’Ambrosia, “Channel compliance testing utilizing novel statistical eye methodology”. DesignCon 2004.


Thank You!Thank You!Visit Altera’s booth #503 to see demonstrations of FPGAs driving backplanes and cables

Visit Mentor’s booth #604 to see HyperLynxtools with PELE demonstration

Visit Molex booth #301 for multi-gigabit backplane and cable demonstrations

pre-emphasis and equalization parameter optimization with ... · pre-emphasis and channel pulse...

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