prepared by s.ravindrakumar,senior assistant...

PREPARED BY S.RAVINDRAKUMAR,Senior Assistant Professor/ECE,Chettinad College of Engineering and Technology


The 80186 Processor

80186/80188 Architecture:

The 80186 and 80188, like the 8086 and 8088, are nearly identical. The only difference between the 80186

and 80188 is the width of their data buses.

The 80186 (like the 8086) contains a 16-bit data bus, while the 80188 (like the 8088) contains an 8-bit data bus.

The internal register structure. of the SOIS6/S0ISS is virtually identical to the 8086/8088. About the only

difference is that the 80186/80188 contain additional reserved interrupt vectors and

some very powerful built-in I/O features. The 80l86 and 80188 are often called embedded controllers because

of their application as a controller, not as a microprocessor-based computer.

FOR EXAMPLE

The 512's microprocessor is an Intel 80186, which runs at a clock speed of 10 MHz. The 80186 is object code

compatible with the 8086 processor, though there are extensions in the 80186 instruction set which are not

present in the 8086. There are two later processors in this series, the 80286 and 80386. Code produced

specifically for them or compiled on them to use the extra facilities will not run in an 80186 machine.

The most notable omission from the 80186 chip, when compared with some of its contemporaries, is the

absence of support for an 8087 maths co-processor. This is a hardware floating-point processor, which has its

own range of separate instructions. When a machine fitted with an 8087 performs large calculations, the

program can be written so that both processors can execute their own code, to a large extent, independently.

The only implication of the lack of an 8087 should be that a system would run slowly when performing large or

complicated calculations. The presence or absence of an 8087 can be detected in software, so applications

which can use the 8087 should check for its presence and self configure in it's absence to use overlaid software

routines instead. A few calculation intensive applications do not verify the presence of the 8087 and cannot be

run in the 512. These will crash as soon as an 8087 instruction is encountered.

Programs in this category the heavyweight statistical analysis and modelling routines or pure scientific

applications. It must be assumed that the authors expected that no one would attempt to run such applications in

a machine without an 8087 co-processor and did not feel the need to check for it.

Versions of the 80186/80188

As mentioned, the 80l86 and 80188 are available in four different versions, which are all CMOS

microprocessors. Table 16-1 lists each version and the major features provided. The 80C186XL and 80C188XL

are the most basic versions of the 80186/80188. while the 80C186EC and 80C188XL are the most advanced.

This text details the 80C186XL/80C188XL, and then describes the additional features and enhancements

provided in the other versions.


Table 1:

80186 Basic Block Diagram

Figure below provides the block diagram of the 80188 microprocessor that generically represents all

versions except for the enhancements and additional features outlined in Table 1. Notice that this

microprocessor has a great deal more internal circuitry than the 8088. The block diagrams of the 80186

and 80188 are identical except for the pre-fetch queue, which is four bytes in the 80188 and six bytes in the

80186. Like the 8088, the 80188 contains

a bus interface unit (BIU) and an execution unit (EU).

In addition to the BIU and EU, the 80186/80188 family contains a clock generator, a programmable interrupt

controller, programmable timers, a programmable DMA controller and a programmable chip selection unit.

These enhancements greatly increase the utility of the 80186/80188 and reduce the number of peripheral

components required to implement a system. Many popular subsystems for the personal computer use the

80186/801S8 microprocessors as caching disk controllers, local area network (LAN) controllers, etc. The

80186/80188 also finds application in the cellular telephone network as a switcher.

Software for the 80186/80188 is identical to the 80286 microprocessor, without the memory management

instructions. This means that the 80286-like instructions immediate multiplication immediate shift counts, string

I/O, PUSHA, POPA, BOUND, ENTER, and LEAVE all function on the 80186/80188 microprocessors.

Processor Registers

The 80186 is a 16-bit processor, which means that each of its registers are 16 bits, or two bytes, wide. This has

several direct implications for the capabilities of the system as a whole, governing factors as diverse as the total

amount of memory that can be addressed, how so phisticated individual machine code instructions can be, and

how comprehensively the processor can monitor events in the system by means of its range of status flags.


A further ramification is the maximum number of possible instructions in the instruction set. In the

6502, which can manipulate only two or three bytes at a time, the first byte always indicates the opcode, hence

there could never be a repertoire of more than 256 instructions. The 86 series of processors has no such

restrictions and more instructions have been added with each succeeding version, which is why code produced

specially for the 80286 or 80386 processors is incompatible with the 80186.

The registers essentially fall into four categories, which are general purpose, segment, index (also called offset)

and status.

General Purpose Registers

In the first category are the registers, which are used for arithmetic and testing of values and results. The four

general purpose registers are called A, B, C and D, but they can each be used both as a single two byte (word)


register, or as two separate single byte registers. Depending on the current operation they have modified names

in programs to indicate their current mode of use.

Note that there is no switch of mode. The portion of the register affected or used is controlled entirely by the

form of the name used in each individual instruction in a program. This may vary from one instruction to the

next.

When used as word registers, A, B, C and D are suffixed by x and are referred to as AX, BX, CX and DX.

When coded into program instructions by these names, all sixteen bits in the register are involved in any

operation.

Although there are two bytes in each of these registers, when used for memory address manipulation it is

convenient to be able to manipulate the high address byte and the low address byte independently. When byte

operations are performed a means is required to indicate which half of which register is to be used. The

convention is to replace the x in each name by an H to refer to the high byte, or an L for the low byte. AX, BX,

CX and DX therefore become AH and AL, BH and BL, CH and CL and DH and DL respectively.

Segment Registers

The second register category is segment registers. These are used to contain the number of the memory block

that is the segment part of the RAM address for memory addressing operations (see Segmentation below). The

four 16-bit segment registers are CS, DS, ES, and SS. These registers cannot be addressed as two separate bytes

and so the following are the only recognised names for these registers. The segment register names mean:

CS Code segment

DS Default segment

SS Stack segment

ES Extra segment

By convention three of these registers have agreed uses within programs, but the purpose of Cs is fixed by the

processor. CS always points to the segment in which code is currently being executed. In fad all the segment

registers are set to this value automatically when a .COM or .CMD program first loads (as is the general

purpose register DX), though they may be altered within the program or during the initialisation process.

CS cannot be directly altered, but a program jump to a different segment (usually initially set up in ES)

automatically causes the value in CS to change appropriately.

CS cannot be directly altered, but a program jump to a different segment (usually initially set up in ES)

automatically causes the value in CS to change appropriately.

Depending on the particular assembler used, it may be necessary to make declarations at the start of source code

about initial segment registers set-up. This can often be seen in 86 assembler source program as a series of

'ASSUME' statements, which may look like this:

ASSUME CS = CODE

ASSUME DS = CS


ASSUME SS = CS

ASSUME ES = nothing

DS is under program control and usually initially defaults to the code segment. When used to indicate a

different segment, DS can be pointed to a segment of memory where the program's data is stored, like the

currently used part of a document in word processing. For most program operations involving addressing, if no

other segment register is explicitly supplied the segment value in DS is used.

The stack segment is analogous to the stack page in the 6502, but it can be much larger. Programs in DOS have

a local stack, that is, one unique to the program, and this may or may not be in the current code segment. This

technique is employed to ensure, as far as possible, that no matter what happens within a program, nothing else

in the machine should be affected. It is also necessary because, without local stacks, multiple simultaneous

program operation, like foreground and background tasks, would be impossible.

The stack segment initially defaults to the code segment, but it can be located elsewhere if required. The

maximum size of a program's stack is unlimited, but in practice is usually confined to the maximum address

range of 16 bits (64k) and it can be anywhere within its available memory that a program chooses to put it. If

required you can allocate a separate segment entirely for the stack. In this case the segment register is program

controlled.

The extra segment register, ES, is conventionally used to point to any other area of memory not within a

currently identified segment. For example, with Ds pointing to your current working data segment, you might

set ES to point to another segment from which you wish to transfer data into the DS segment. At the same time

CS points to the current code segment, while SS might point to a stack segment for temporarily stored data that

you may need to retrieve later.

All segment registers are used in conjunction with a two-byte offset to address the memory location within the

segment. This can be a hard coded literal value, or it may be a derived or calculated value contained in a

memory location or one of the index registers. In the case of CS, the offset address is always indicated by the

instruction pointer (See IP), the contents of which cannot he varied directly.

Index and Pointer Registers

The two index registers, SI and DI are the third category of register. These are both 16 bit registers and can be

used in conjunction with the segment registers. When used together, a segment register and a segment offset can

define any address in any part of the memory. For this reason the index registers are sometimes also called

offset registers.

The fourth register category is the pointer registers. These are also 16 bit register and are called:

SP Stack pointer

BP Base pointer

IP Instruction pointer

The stack pointer holds the address of the next free stack entry in the stack segment. The stack pointer must be

initialised by the program to point to the top of the space reserved for the stack if the programmer wishes to


specify a special stack area. On initial load the stack pointer is set to the address of the end of the code segment

minus two bytes. Stack space is used from the top downward in the same manner as the 6502's stack. Note that

it is up to the program itself to allocate stack space and to point SR to it (and SS too if necessary) before The

stack is used. For example the instruction:

PUSH A

executed with SR set at 1000h would push the contents of registers AX, CX, DX, BX, SP, BP, SI and DI onto

the stack and decrement SR by two for each, leaving it pointing to 0FF0h.

The base pointer is used as a pointer into memory, often as a sort of memo to an address in a local table, or as

the starting value for an index register which will be varied. It is entirely under program control and is mainly

intended to be used to address local variables stored on the stack. For this reason the default segment register for

BP is SS, not Ds as it is for most other operations.

There is a third pointer register, the implicit instruction-pointer, IP. Arguably IP is not a register in the usual

sense as, in conjunction with CS, if points to the address of the currently executing program instruction. Like Cs

it cannot be changed directly, but only as a result of executing jumps or returns within the program code.

The last register, the status register, is also known as the flags register. It performs the same function as in other

processors. Various bits are set or unset as a result of arithmetic operations, comparisons and moves. These

status bits, or flags, can then be used to govern the actions of following conditional instructions.

There is one particularly interesting extra feature of the 86 status register over that of the 6502. One of the flags

is the direction flag. As will be seen shortly, numerous automatic indexing and counting instructions exist and

two instructions, 'STD' (SeT Direction) and 'CLD' (CLear Direction) set or clear this flag respectively. The

setting of this flag dictates whether the automatic increment for certain instructions is positive or negative. The

word 'advancing' is conventionally used to denote either of these in describing instruction operations.

80186/80188 Basic Features

Clock Generator:

The internal clock generator replaces the external 8284A clock generator used with the 8086/8088 microprocessors. This

reduces the component count in a system. The internal clock generator has three pin connections: X1, X2, and CLKOUT

(or on some versions: CLKIN, OSCOUT, and CLKOUT). The X1 (CLKIN) and X2 (OSCOUT) pins are connected to a crystal

that resonates at twice the operating frequency of the microprocessor. In the 8 MHz version of the 80186/80188, a 16

MHz crystal is attached to X1 (CLKIN) and X2 (OSCOUT). The 80186/80188 is available in 6 MHz, 8 MHz, 12 MHz, 16 MHz,

or 25 MHz versions. The CLKOUT pin provides a system clock signal that is one-half the crystal frequency, with a 50

percent duty cycle. The CLKOUT pin drives other devices in a system and provides a riming source to additional

microprocessors in the system.

In addition to these external pins. the clock generator provides the internal timing for synchronizing the READY input

pin, whereas in the 8086/8088 system, READY synchronization is provided by the 8184A clock generator.


Programmable Interrupt Controller:

The programmable interrupt controller (PIC) arbitrates the internal and external interrupts, and controls up to two

external 8259A PICs . When an external 8259 is attached, the 80186/80]88 microprocessors function as the master and

the 8159 functions as the slave, The 80CI86EC and 80CI88EC models contain an 8259A-compatible interrupt controller in

place of the one described here for the other versions (XL, EA, and EB). If the PIC is operated without the external 8259,

it has five interrupt inputs: INT0-INT3 and NMI. Note that the number of available interrupts depends on the version: the

EB version has six interrupt inputs and the EC version has 16. This is an expansion from the two interrupt inputs available

on the 8086/8088 microprocessors. In many systems, the five interrupt inputs are adequate.

Timers:

the timer section contains three fully programmable 16-bit timers. Timers 0 and 1 generate waveforms for

external use, and are driven by either the master clock of 80186/80188 or by an external clock. They are also

used to count external events. The third timer, timer 2, is internal and clocked by the master clock. The output

of timer 2 generates an interrupt after a specified number of clocks and can provide a clock to the other timers.

Timer 2 can also be used as a watchdog timer because it can be programmed to interrupt the microprocessor

after a certain length of time. The 80CI86EC and 80CI88EC models have an additional timer called a

watchdog.The watchdog timer is a 32-bit counter that is clocked internally by the CLKOUT signal (one-half

crystal frequency). Each time the counter hits zero, it reloads and generates a pulse on the /WDTOUT pin that is

four CLKOUT periods wide. This output can be used for any purpose:it can be wired to the reset input to cause

a reset or to the NMI input to cause an interrupt. Note that if it is connected to the reset or NMI inputs, it is

periodically reprogrammed so that it never counts down to zero. The purpose of a watchdog timer is to reset or

interrupt the system if the software goes awry.

Programmable DMA Unit:

The programmable DMA unit contains two DMA channels or four DMA channels in the

80C186EC/8OC188EC models. Each channel can transfer data between memory locations, between memory

and I/O, or between I/O devices. This DMA controller is similar to the 8237 DMA controller discussed in

Chapter 13. The main difference is that the 8237 DMA controller has four DMA channels, as does the EC

model.

Programmable Chip Selection Unit:

The chip selection is a built-in programmable memory and I/O decoder. It has six output lines to select

memory, seven lines to select I/O on the XL and EA models, and 10 lines that select either memory or I/O on

the EB and EC models. On the XL and EA models, the memory selection lines are divided into three groups

that select memory for the major sections of the 80186/80188 memory-map. The lower memory select signal

enables memory for the interrupt vectors,

the upper memory select signal enables memory for reset, and the middle memory select signals enable up to

four middle memory devices. The boundary of the lower memory begins at location 00000H and the boundary

of the upper memory ends at location FFFFFH. The sizes of the memory areas are programmable, and wait

states (0-3 waits) can be automatically inserted with the selection of an area of memory. On the XL and EA

models, each programmable I/O selection signal addresses a 128-byte block of I/O space. The programmable


I/O area starts at a base I/O address programmed by the user, and all seven 128-byte blocks are contiguous. On

the EB and EC models, there is an upper and lower memory chip selection pin, and eight general-purpose

memory or I/O chip selection pins. Another difference is that from 0-15 wait states can be programmed in these

two versions of the 80186/80188 embedded controllers.

Power Save/Power Down Feature:

The power save feature allows the system clock to be divided by 4, 8, or 16 to reduce power consumption.

The power-saving feature is started by software and exited by a hardware event such as an interrupt. The power

down feature stops the clock completely. but it is not available on the XL version. The power down mode is

entered by executing a HLT instruction and is exited by any interrupt.

Refresh Control Unit:

The refresh control unit generates the refresh row address at the interval programmed. The refresh control

unit does not multiplex the address for the DRAM-this is still the responsibility of the system designer. The

refresh address is provided to the memory system at the end of the programmed refresh interval, along with the

/RFSH control signal. The memory system must run a refresh cycle during the active time of the /RFSH control

signal. More on memory and refreshing is provided in the section that explains the chip selection unit.

PIN DIAGRAM OF 80186

Architecture of Intel 80286

Key Features –


16-bit date bus

24-bit non-multiplexed bus

Packaged in a 68-pin ceramic pack

80286 has 2 24

= 16 M Byte of physical memory accessibility

Fig 32.1 Basic Architecture of 80286

Memory Bank

Memory of 80286 is setup as an odd bank and an even bank, just as it is for the 8086. The even bank is

enabled when A 0 is low and the odd bank is enabled when is low. To access an aligned word, both A 0

will be low.


Fig 32.2 Memory banks in 80286

Memory Addressing in 80286

1. Real Addressing Mode – It is just like as in 8086. Address is 20 bit with 16 bit segment and 16 bit

offset. When 80286 is hardware reset, it automatically enters real address mode.

2. Protected Virtual Addressing Mode (PVAM) – In this we have 1 GByte of virtual memory and 16

Mbyte of physical memory. The address is 24 bit. To enter PVAM mode, Processor Status Word

(PSW) is loaded by the instruction LPSW.

Fig 32.3 Load Processor Status Word

PE – Protection Enable

MP – Monitor Processor Extension

EM – Emulate Processor Extension

TS – Task Switch

Hardware reset is the only way to come out of protected mode.

80286 Memory Management Scheme

Memory is organized into logical segments. Segment size can be anywhere between 1 Byte to 16 KByte. All

24 address pins are active and 16 MByte of physical memory is available.

Descriptor

It is 8-byte quantity. Each segment has a descriptor. There are two main types of descriptor –

Segment Descriptor

System control Descriptor

Format of a Descriptor


Fig 32.4 Descriptor Format

Access Right byte definition

7 Present (P) 1 – Yes

0 – No

6-5 Descriptor Privilege level (DPL) 0 to 3

4 Segment Descriptor 1 – Segment

0 – Control

For segment descriptor, i.e. for S = 1, bits 3-0 have the following meaning –

3 E 0 – Data

1 – Code

2 Expansion/

Confirming

If code, Confirming: 1 means „Yes', 0 means

„No'

If data, Expand down: 1 - Yes, 0 - No (normal

case)

1 R / W If code, Readable: 1 - Yes, 0 – Not

If data, Writeable: 1 – Yes, 0 – Not

0 Accessed (A) A = 0, Not accessed

A = 1, Accessed

Descriptors are contained in a descriptor table. There are two categories of descriptor table – global and local.

A system has only one global descriptor table or GDT. A local descriptor table or LDT is set up in the system

for each task or closely related group of tasks. Each task can have its own descriptor table and memory area

defined by the descriptors in it.

Accessing Segments

The 80286 microprocessor keeps the base address and limits for the descriptor tables currently in use in

internal registers. These registers are load descriptor table register (LDTR) and global descriptor table register

(GDTR). Descriptor in memory is addressed by adding segment selector to these registers. The descriptors

contain the base address of segments, which when added with the offset in the virtual address points to the

required memory location.

Accessing a Segment of Higher Privilege Level


Tasks operate at the lowest privilege level. Usually, segments at a lower privilege level are not allowed to

access segments at a higher privilege level directly. However, a lower level segment can access a higher level

segment indirectly by a Gate Descriptor. The details of a gate descriptor are given herewith.

Fig 32.5 Privilege Level

Gate Description Format

Fig 32.6 Gate Descriptor Format

Name Value Description

Type 4 Call gate

. 5 Task gate

. 6 Interrupt gate

. 7 Trap gate

P 0 Descriptor contents are NOT valid

. 1 Descriptor contents are valid

DPL 0-3 Descriptor privilege level

Word Count 0-31

Number of words to copy from callers stack to

called procedures stack. Only used with called

gates.

Destination Selector 16-bit Selector

Selector to target code segment (call, interrupt,

task gates)


Selector to target task state segment (task gate)

Destination Offset 16-bit Offset Entry point within the target code segment

Task Switching and Task gates

Each task in a PVAM system has a 22-word task state segment (TSS) associated with it. A TSS holds copies

of all registers and flags, the selector for the tasks' LDT, and a link to the TSS of the previously executing

task.

Descriptors for each task state segment are kept in the global descriptor table. A task register (TR) in the

80286 holds the selector and the task state segment descriptor for the currently executing task. The load task

register (LTR) instruction can be used to initialize the task register to the task state segment for a particular

task. During a task switch the task register is automatically loaded with the selector and descriptor for the new

task.

Method of Task Switching

1. Long jump or call instructions that contain a selector which points to the Task State segment

descriptor

2. IRET

3. Selectors in a long jump or call points to a task gate

4. Interrupt occurs and the vectors point to a task gate descriptor

80286 Interrupt Handling

Real addressing mode has 256 interrupts with types 0-255. Each interrupt takes 4 bytes, so we have to reserve

1KByte of memory for interrupt.

In PVAM mode also we have 256 interrupts but it is not assigned a fixed memory. The interrupt descriptor

table can be anywhere in the physical memory. Base address of interrupt descriptor table is stored in interrupt

descriptor table register (IDTR). The particular descriptor is accessed as follows –

(Interrupt Type * 8) + IDTR Descriptor

Memory Management

In advanced microprocessor, memory management becomes extremely important. Memory management is

required due to the following two reasons.

1. Limitation of physical memory

A microprocessor has limited number of address lines. Hence the physical memory addressability is

limited. Increasing the number of address lines is not attractive as it makes the architecture and design

complex without significant gain. Packaging becomes difficult and expensive. Memory Management

Unit (MMU) solves this problem by translating the virtual memory address into the physical memory

address. Virtual memory can be many times larger than the physical memory. Only the programs

currently required are brought from the secondary storage such as a hard disk to, the physical memory

(RAM) for execution.

2. Need for Protection

In a multi-user operating system, there is a possibility that a user program can corrupt the operating

system area or the area of some other user unless a protection mechanism is built. Hence each user

should be protected from other users and the operating system should be protected from other user


(task). The user (task) should be allowed to have a controlled access to the operating system resources.

Hence various privilege levels are defined. For example, in a situation having 4 privilege levels, 0 is

the highest privilege and 3 has the lowest privilege as shown in the figure. The figure shows a typical

Unix operating system layout.

It has to be noted that the user is at the lowest privilege level, i.e., privilege level 3 and the operating

system Kernel is at the highest privilege level, i.e., privilege level 0.

Fig. 31.1 Protection mechanism and privilege levels

Kernel, System services and Application services constitute the operating system. The user or task sits at the

lowest privilege level and can not access the resource available at higher privilege levels directly. Similarly,

Task-1, Task-2 and Task-3 occupy different memory blocks and they are protected from each other.

A microprocessor such as 8086 does not provide this kind of protection. The Memory Management Unit

(MMU) of advanced microprocessors such as 80286 incorporates this kind of protection for a multi-user

operating system.

Role of Memory Management Unit (MMU):

The virtual address space of a microprocessor may be many times larger than the actual physical address

space. This is desirable as a microprocessor is supposed to store large programs and data which can not be

accommodated in the physical memory space. Usually programs and data are stored in a secondary storage

such as a hard disk. The hard disk is in the virtual or logical address space but not in the physical address

space. Faster memory such as RAM is used as the physical memory (Primary Storage).


Fig.31.2 Microprocessor interfacing with primary storage and secondary storage

When a microprocessor is to execute a program, it checks whether the program is available in the physical

memory (RAM). If the program is not available in the physical memory, it is brought from the secondary

memory to the physical memory for execution. If available space is inadequate in the physical memory, some

less important or unused program can be swapped back to the secondary memory to create space.

Memory Management Unit (MMU)

Memory Management Unit within a microprocessor converts the virtual memory address into a physical

memory address. Virtual memory address is sometimes referred as logical memory address.

MMU can convert logical address into physical address in two ways.

1. Segment oriented approach:

In this case, the logical memory space consists of memory segments of variable length. Each segment

contains some data/ program as is described by a “descriptor”. The segment “descriptor” contains the

base address of the segment, segment size and other attributes. The descriptors of all segments are

stored in a “descriptor table” located in the physical memory.

The logical address of a memory location contains two parts, viz, segment selector and offset. The

segment selector points to the segment “descriptor” in the descriptor table. From the “descriptor”, the

base address of the segment is obtained. The offset part of the logical address is added to the segment

base to generate physical address of the memory.


2. Page oriented approach:

In page oriented approach, the logical address space is divided into pages of fixed length. A page has 4

Kbytes. Since the MMU deals with smaller chunk of memory (4 Kbytes), it is easier and faster to swap back

and forth between the secondary storage and the physical memory.

prepared by s.ravindrakumar,senior assistant...

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