presented by: nivya papakannu ece department, umass amherst
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Temperature-Aware Resource Allocation and Binding in High Level Synthesis Authors : Rajarshi Mukherjee, Seda Ogrenci Memik, and Gokhan Memik. Presented by: Nivya Papakannu ECE Department, UMASS Amherst. Overview:. Introduction Temperature-Aware High Level Synthesis - PowerPoint PPT PresentationTRANSCRIPT
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Temperature-Aware Resource Allocation and Binding in High Level Synthesis
Authors: Rajarshi Mukherjee, Seda Ogrenci Memik, and Gokhan Memik
Presented by:Nivya Papakannu
ECE Department, UMASS Amherst
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Overview:
• Introduction• Temperature-Aware High Level Synthesis
– Temperature Model and Assumptions– Resource Allocation and Binding
• Experimental Setup & Results• Conclusions
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Introduction:
• Continuous technology scaling following Moore’s Law• Billion transistor IC• Massive computational power • Increase in power density
– Increase in temperature• One of the biggest challenges in VLSI design
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Need for thermal Awareness:• Functional Incorrectness
– Carrier mobility decrease– Interconnect resistance increase
• Reliability Issues– Electro-migration– Transient and Permanent faults
• Thermal Considerations– 10C rise – component failure rate doubles
• Non-uniform distribution
– “HOTSPOTS”• Leakage Power
– Dominant in current technologies– Increasing with future technologies– Exponential dependence on temperature
• Higher Temperature Higher Temperature Higher Power Higher Power
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Thermal Awareness in HLS:
• Can we prevent high temperatures in the first place?• Will power optimization help?
– Not always – No individual consideration
• Incorporate physical phenomenon in all stages of design flow– Thermal driven floor planning and placement– Thermal Aware High Level Synthesis
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Temperature Model & Leakage Model:• Thermal Model
– Analogy between heat transfer and RC circuits
Ttot is the temperature contribution due to power dissipation
– Ptot = Pswitch + Pleakage t = one clock cycle duration
• Temperature Variation – Modeled as exponential
transient behavior analogous to electrical time constant RC
– R : thermal resistance, C: thermal capacitance
• Leakage Model• Leakage has exponential
dependence– Threshold voltage Vth
– Temperature T
• 4th order polynomial to represent Pleakage
• At 180nm– 15% of dynamic power at
ambient temperature– Doubles every 25C
totRC
d
AiAj TeTTTTji
,
)(
C
tPT tottot
)),(exp( TVfP thleakage
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Temperature Aware Resource Allocation and Binding:
• Scheduled Data Flow Graph– Allocation and Binding
• Compatibility graph for each operation type– Operations are vertices– Edges labeled with switched capacitance
• Two Modes for optimizing temperature– Temperature constrained resource minimization (TC)– Resource constrained temperature minimization (RC)
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DFG & Compatibility Graph:
For k resources – finds k paths s.t. sum of edge weights is min.
1+ 2+
3+
4+ 5+
1+ 2+
3+
4+
5+6+
6+
1
2
3
4
Data Flow Graph Compatibility Graph
R1 R2
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Relaxation:• Relaxation
– Determine the predecessor or parent of each vertex– Relaxation idea based on Dijkstra’s shortest path algorithm – For each vertex the best parent is determined through which we could
reach the vertex by relaxing the vertices based on the constraint criteria.
• Temperature Constrained (TC)– Relax vertices that do not violate temperature constraint
• Resource Constrained (RC)– Relax vertex with minimum rise in temperature.
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Temperature Aware Resource Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab swbc swde swef swfg
gfedcbswcd
a
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Temperature Constrained Resource Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab swbc swde swef swfg
gfedcbswcd
a
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Temperature Constrained Resource Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab swbc swde swef swfg
gfedcbswcd
a
T1
aCandidates
Temperature of R1 Ta
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Temperature Constrained Resource Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab
T2
swbc swde swef swfg
gfedcbswcd
a
T2 T2 T2 T2 T2
(a) (a) (a) (a) (a)(a)
a b a c a g
Temperature of R1 Tab Tac Tag
T1
Candidates
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Temperature Constrained Resource Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab
T2
swbc swde swef swfg
gfedcbswcd
a
T2 T3 T3 T2 T3
(a) (a) (b) (b) (a) (b)
a b a cd a b e
a b c X
Temperature of R1 Tabd Tabe Tac
T1
Candidates
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Temperature Constrained Resource Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab
T2
swbc swde swef swfg
gfedcbswcd
a
T2 T3 T3 T2 T4
(a) (a) (b) (b) (a) (d)
a b d e
a b d g
X
T1
Candidates
Temperature of R1 Tabdg
a b e
Tabe
a c
Tac
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Temperature Constrained Resource Allocation and Binding
• Determine the parent of each vertex– Relaxation
– Select the longest path– Bind to a resource– Shown for temperature constrained binding
swab
T2
gfedcba
T2 T3 T3T2 T4
(a)(a) (b) (b) (a) (d)
Resource 1
swdg
swbd
a b d gR1
T1
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Resource Constrained Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab swbc swde swef swfg
gfedcbswcd
a
a
T1
TaTemperature on R1
Candidate
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Resource Constrained Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab
T2
swbc swde swef swfg
gfedcbswcd
a
(a)
T1
Tab
a b
Temperature on R1
Candidate
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Resource Constrained Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab
T2
swbc swde swef swfg
gfedcbswcd
a
T3
(a)
a b
(b)
d
T1
Temperature on R1 Tabd
Candidate
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Resource Constrained Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab
T2
swbc swde swef swfg
gfedcbswcd
a
T3 T4
(a)
a b
R1
(b)
d
(d)
f
T1
Temperature on R1 Tabdf
Candidate
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Resource Constrained Allocation and Binding
• Determine the parent of each vertex
– Relaxation
swab
T2
swbc swde swef swfg
gfedcbswcd
a
T3 T4 T5
(a)
a b
R1
(b)
d
(d)
f
(f)
g
T1
Temperature on R1 Tabdfg
Candidate
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Resource Constrained Allocation and Binding
• Determine the parent of each vertex– Relaxation
– Returns the longest path– Bind to a resource– Shown for resource constrained binding
swab
gfedcba
(a)(b) (d) (f)
Resource 1 swfd
swbd
a bR1 d f g
swfg
T2 T3 T4 T5T1
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Temperature Aware Resource Allocation and Binding
• Determine the parent of each vertex– Relaxation
– Select the longest path– Bind to operations a resource– Remove operations from comparability graph– Build new comparability graph– Continue until all operations are bound to a resource
swef
fecswce
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Temperature Aware Resource Allocation and Binding
• Successive paths from relaxation represent binding of the operations to a new resource
• Post-Processing– Merging/dividing resources
swab
Ti+1
swef
gfedcba
Ti+1 Ti+1 Ti+1Ti+1 Ti+1
(a)(c) (d)
Resource 1 Resource 2
swdg
swbd
swcf
(b)
a b d g
c f
R1
R2
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Experimental Flow:
Applications in C
SUIF
Scheduler
DFGs of PopularDSP Algorithms
Min-Cost Flow Binding
Temperature-AwareAllocation & Binding
Min Resource Binding under TC
Binding with optimal
switching
Min Temperature Binding under RC
Temperature-Aware Binding
DFGs
RC TC
Synopsys DC for Capacitance Extraction
ModelSim Simulation for Switching Activity
Compare w
ith lo
w
power binding
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Resource Overhead
Benchmarks SW_OPT
[MUL, ALU]
TC_R_MIN
[MUL, ALU]
ewf 3, 5 4, 8
arf 4, 2 5, 4
jctrans_1 2, 3 2, 7
jctrans_2 0, 4 0, 6
jdmerge1 3, 6 3, 7
jdmerge2 3, 6 3, 9
jdmerge3 3, 6 3, 9
jdmerge4 3, 5 5, 9
motion_2 4, 6 6, 8
motion_3 4, 6 6, 8
noise_est_2 3, 4 4, 7
28% increase in MULs54% increase in ALUs
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Experimental Results – Temperature
Maximum Temperature Reached by ALUs
70
75
80
85
90
95
100
105
110
Ma
x. T
em
p [C
]
TC_R_MIN RC_TEMP_MIN SW_OPT
70
75
80
85
90
95
100
105
110
Ma
x. T
em
p [C
]
TC_R_MIN RC_TEMP_MIN SW_OPT 11.9C3.6C19.2C11.2C
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Experimental Results – Temperature
Maximum Temperature Reached by Multipliers
70
75
80
85
90
95
100
105
110
Ma
x. T
em
p [C
]
TC_R_MIN RC_TEMP_MIN SW_OPT
70
75
80
85
90
95
100
105
110
Ma
x. T
em
p [C
]
TC_R_MIN RC_TEMP_MIN SW_OPT7.6C2.7C
10.3C 18.9C
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Experimental Results – Leakage Power
0.85
0.9
0.95
1
1.05
1.1
Po
we
r C
on
su
mp
tio
n
TC_R_MIN RC_TEMP_MIN SW_OPT
0.85
0.9
0.95
1
1.05
1.1
Po
we
r C
on
su
mp
tio
n
TC_R_MIN RC_TEMP_MIN SW_OPT
Normalized leakage power consumption of the three techniques at 180nm
9%
2%
2.18
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Experimental Results – Total Power
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
Po
we
r C
on
su
mp
tio
n
TC_R_MIN RC_TEMP_MIN SW_OPT
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
1.4
1.45
1.5
Po
we
r C
on
su
mp
tio
n
TC_R_MIN RC_TEMP_MIN SW_OPT
Normalized total power consumption of the three techniques at 180nm
34%
5%
2.38
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Conclusions:
• Introduced Resource binding Techniques to create temperature-awareness in HLS
• Temperature-aware resource allocation and binding
• Effectively minimized the maximum temperature reached by a module
– Temperature constrained
– Resource constrained
• Leakage and total power savings in future technologies
• A reliability driven methodology can leverageon this mechanism to prevent or reduce likelihood of hotspots on a chip