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A Block Based Test Methodology (BBTM) for Verigy 93K Platform Subbarao Jaldu, Cypress, [email protected] Albert Alcorn, Cypress, [email protected] 1 Silicon Valley Test Conference 2010

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A Block Based Test Methodology (BBTM) 

for Verigy 93K Platform

‐ Subbarao Jaldu, Cypress, [email protected]‐ Albert Alcorn, Cypress, [email protected]

1Silicon Valley Test Conference 2010

PresentersLogo

• PROBLEM STATEMENT• OBJECTIVE• BENEFIT• OLD METHOD VS. NEW METHOD• BBTM COMPONENTS• MONEY SAVINGS

AGENDA

2Silicon Valley Test Conference 2010

PROBLEM STATEMENT

– Long lead times in test program development

– Complex interface

– Minimal reuse of tIP© (Test IP blocks)

– Personalized coding and localized best practices

– Flex resource allocation not possible

– Redundant learning (different flavors of the same 

test)

3Silicon Valley Test Conference 2010

OBJECTIVE

– Develop tIP© reuse system

– Create generic interface for any device

4Silicon Valley Test Conference 2010

BENEFITS

– Faster development cycle• Code re‐use and corporate‐wide tIP development

– Standardized coding and global best practices

– True flex resource allocation

– Portability

– Efficient knowledge base• Example: need to understand only one leakage tIP block

– Standardized production and char functions

– Standardized output format

– Simple, flexible interface

5Silicon Valley Test Conference 2010

Primaries• Pin Definitions• Timing• Levels• Test Patterns

Test Suite• Test Setup Definition : Basic building block that defines all the setup conditions for a test : Primaries

Test Flow• Multiple test suites from Continuity to Binning combine to make a comprehensive Test Flow

Background : 93k Test Program Requirements

6Silicon Valley Test Conference 2010

Timing

Levels

Pattern

Test Function

Background : Test Suite

7Silicon Valley Test Conference 2010

Old Method : Device1

Primary Setups

Char Functions

Char Flow

New Method : Device2

Primary Setups

Char Functions

Char Flow

Device1 Device2

PARAMETERS 30 150

VDD COMBINATIONS 6 25

PATTERNS 50 200

Device1 Device2 Latest Version

File Size (Bytes) 6256459 56163 7596

Total Pages 2429 40 5

No. of Lines 69854 1814 263

No. of Words 164825 4633 655

OLD METHOD VS. NEW METHOD : Complexity

8Silicon Valley Test Conference 2010

Presenter
Presentation Notes
In reality, What does this mean ? Old Flow: 4-5 reams of paper. BBTM flow takes less than 100 pages including the test IP

DEVICE-SPECIFIC TESTFLOW• No reuse of code: flow,

testfunctions• Lack of standardization

BBTM• Modular testflow• Standard char testfunctions• Databrowser-friendly datalogs• tIP sharing

Old Method : DSP

Primary Setups

All Char Functions

Char Flow

Device Specific ProgramShared tIP

New Method : BBTM

Primary Setups

New Char Functions

tIP Char Functions

Char Flow

OLD METHOD VS. NEW METHOD :      Development Cycle

9Silicon Valley Test Conference 2010

Old Method

TE1 TE2 tIP (BBTM)TE3 PE

Development Cycle

Device1 : TE1

Device2 : TE2

Device3 : TE3

OLD METHOD VS. NEW METHOD : Flexibility

10Silicon Valley Test Conference 2010

Presenter
Presentation Notes
Old Method - Dedicated TE to a Device - No PE involvement - No Standardization

New Method

TE1 TE2 tIP (BBTM)TE3 PE

Development Cycle

Device1 : TE1

Device2 : TE2

Device3 : TE3

OLD METHOD VS. NEW METHOD : Flexibility

11Silicon Valley Test Conference 2010

Presenter
Presentation Notes
New Method - Multiple TE to Multiple Device - Active PE involvement - All tIP Standardized

BBTM  Implementation

ITERATORTRD• Testlist• Params• Setup

TIMING

LEVELS

PINSDUT

tIP1

tIP2

tIP3

tIP4

BBTM Shell

Device Specific

12Silicon Valley Test Conference 2010

Presenter
Presentation Notes
BBTM shell is standardized tIP is efficient and standardized Develop only Device Specific modules

TRD Components : Test List

• Flow Control

• Single line Test Suite Setups

• Multiple Insert Control

• High Level Documentation

13Silicon Valley Test Conference 2010

Presenter
Presentation Notes
Supports VDD Loops Production Binning Production & Char Versions (flip of a switch) Human Readable Simple Flow

TRD Components : Test Param

• Parameter Definitions

• Search Control

• Granularity Control (Pins, Resolution)   

14Silicon Valley Test Conference 2010

Presenter
Presentation Notes
Supports AC,DC and Analog parameters Multiple Search options Per Pin Searches Specific PMUs Specify Units Search Windows & Resolustion

Test IP (tIP)

DC 19AC 9Analog 8Misc 9Search 2Functional 1Total 48

• Independent IP blocks

• Perform Standard Functions

• Standard Coding (Easy to Read)

15Silicon Valley Test Conference 2010

Presenter
Presentation Notes
We are at 48 tIP blocks and still growing !!

tIP Level Definition

Number Status Definition Deliverable

Level1 IdentifiedIdentify a tIP that is required to test a Device or a Utility Function

None

Level2 DefinedDefine the actual test procedure.   This should include the definition of a generic test methodology (similar to bench setup) and 93k approach

Memo

Level3 Developed Actual CPP Code developed and ready to be tested None

Level4 Verified Verify on a Real Silicon using the latest Iterator Memo

Level5 DocumentedDocument using tIP doc template.  Need to pass the review board.

tIP training module

Level6 Checked In Check in tIP code, tIP documentation in Subversion

16Silicon Valley Test Conference 2010

Presenter
Presentation Notes
Definitions of Stages of tIP development

BBTM 93k IP Status

0

1

2

3

4

5

6

7

Spec_

Search

Functi

onal T

est

Leak

ageLe

vels

Operat

ing C

urren

tStand

by

Echo C

lock M

easShm

ooID

DQResis

tance

Continuit

yVDD S

horts

IP Name

IP L

evel

(6)

051015202530354045

Usag

e %

in D

evic

e2

IP Level Usage %

tIP Reuse Status

Level IP Status1 Identified2 Defined3 Developed4 Verified5 Documented6 CheckedIn

• Total Tests : 325

• tIP Used : 12

17Silicon Valley Test Conference 2010

Presenter
Presentation Notes
Device2 : Status of different tIP Almost 325 test suites but only 12 tIPs required

ESTIMATED SAVINGS

0.0

2.0

4.0

6.0

8.0

10.0

MW

Pre/Post Si Ip Dev.

PatternValidation

DataCollection

Data Analysis

Char Task

Char Cycle Time

Old MethodNew Method

BBTM $aving$

18Silicon Valley Test Conference 2010

Presenter
Presentation Notes
Typical cycle time fro 1st Si to Char Closure 4 major tasks 2 tasks are addressed by this.

Task MW COST ($K)

Old char development cycle time  6 24

BBTM development cycle time1 1 4

Savings per device 5 20

Total savings for 5 projects using BBTM  25 100

Note1 : Estimate for existing tIP. New tIP require more time.

ESTIMATED SAVINGS

19Silicon Valley Test Conference 2010

Presenter
Presentation Notes
Savings are Significant. Development is efficient. Developed programs for 4 chips in 2 quarters by 2 engineers (lka,jbh)