prestigio 159w

PRESTIGIO NOBILE 159W

TECHNICAL SERVICEMANUAL

2

1.1. Hardware Specification……………………………………………………. 3 1.2. Software Specification…………………………………………………….. 17

TECHNICAL SERVICE MANUAL Prestigio Nobile 159W

1-2

1.1 Hardware Specification.

A. CPU

The Intel® Pentium® M processor is a high performance, low power mobile processor with

several micro-architectural enhancements over existing Intel mobile processors.

The following list provides some of the key features on this processor:

Supports Intel® Architecture with Dynamic Execution

High performance, low-power core

On-die, primary 32-kbyte instruction cache and 32-kbyte write-back data cache

On-die, 1-MByte second level cache with Advanced Transfer Cache Architecture

Advanced Branch Prediction and Data Prefetch Logic

Streaming SIMD Extensions 2 (SSE2)

400-MHz, Source-Synchronous processor system bus

Advanced Power Management features including Enhanced Intel SpeedStep® technology

Micro-FCPGA and Micro-FCBGA packaging technologies

The Intel Pentium M processor is manufactured on Intel’s advanced 0.13 micron process

technology with copper interconnect. The processor maintains support for MMX™ technology and

Internet Streaming SIMD instructions and full compatibility with IA-32 software. The high

performance core features architectural innovations hlike Micro-op Fusion and Advanced Stack

Management that reduce the number of micro-ops handled by the processor. These results in more

efficient scheduling and better performance at lower power. The on-die 32-kB Level 1 instruction

and data caches and the 1-MB Level 2 cache with Advanced Transfer Cache Architecture enable

significant performance improvement over existing mobile processors. The processor also features a

very advanced branch prediction architecture that significantly reduces the number of mispredicted

branches. The processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before an

L1 cache requests occurs, resulting in reduced bus cycle penalties and improved performance.

The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in

multimedia applications including 3-D graphics, video decoding /encoding, and speech recognition.

The new packed double-precision floating-point instructions enhance performance for applications

that require greater range and precision, including scientific and engineering applications and

advanced 3-D geometry techniques, such as ray tracing.

The Intel Pentium M processor’s 400-MHz processor system bus utilizes a split-transaction,

TECHNICAL SERVICE MANUALPrestigio Nobile 159W

1-3

deferred reply protocol. The 400-MHz processor system bus uses Source-Synchronous Transfer

(SST) of address and data to improve performance by transferring data four times per bus clock (4X

data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses

two times per bus clock and is referred to as a “double-clocked” or 2X address bus. Working

together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 3.2

Gbytes/second. The processor system bus uses Advanced Gunning Transceiver Logic (AGTL+)

signal technology, a variant of GTL+ signalling technology with low power enhancements.

Note: The term AGTL+ has been used for Assisted Gunning Transceiver Logic technology on other

Intel products.

The processor features Enhanced Intel SpeedStep technology, which enables real-time dynamic

switching between multiple voltage and frequency points instead of two points supported on

previous versions of Intel SpeedStep technology. This results in optimal performance without

compromising low power. The processor features the Auto Halt, Stop-Grant, Deep Sleep, and

Deeper Sleep low power states.

The Intel Pentium M processor utilizes socketable Micro Flip-Chip Pin Grid Array

(Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package

technology. The Micro-FCPGA package plugs into a 479-hole,surface-mount, Zero Insertion Force

(ZIF) socket, which is referred to as the mPGA479M socket.

This document includes specifications for the Intel Pentium M processor at Highest Frequency

Mode (HFM) core frequencies of 1.30, 1.40, 1.50, 1.60 and 1.70 GHz, the Low Voltage Intel

Pentium M processor at HFM core frequency of 1.10 and 1.20 GHz and the Ultra Low Voltage Intel

Pentium M processor at HFM core frequency of 900MHz and 1.00 GHz.

B. North Bridge – MCH 855PM

Intel® Centrino™ mobile technology with integrated wireless LAN capabilities was designed

specifically for wireless notebook PCs – delivering outstanding mobile performance and enabling

extended battery life and thinner, lighter designs.

The Intel® 855PM Memory Controller Hub (MCH) is an Intel® Centrino™ mobile technology

component. The MCH manages the flow of information between its four interfaces: the processor

side bus (communication with the Intel® Pentium® M processor), memory interface, AGP interface,


1-4

and hub interface. The MCH arbitrates between the four interfaces when each initiates an operation.

The Intel® 855PM memory controller hub (MCH) is designed for use with the Intel® Pentium® M

processor. The MCH supports data coherency via snooping and must perform address translation for

access to AGP Aperture memory. To increase system performance, the MCH incorporates several

queues.

The Intel® 855PM MCH may contain design defects or errors known as errata, which may cause

the product to deviate from published specifications. This information will be available in

Specification Updates.

Features Processor/Host Bus Support

Supports the Intel® Pentium® M processor

2x Address, 4x Data

Supports system bus at 400 MT/s

Supports host bus Dynamic Bus Inversion (DBI)

Supports 32-bit host bus addressing

12 deep In-Order Queue

AGTL+ bus driver technology with integrated GTL termination resistors and low voltage

operation (1.05 V)

Support for DPWR# signal to Intel® Pentium® M processor for PSB power

management

Memory System

Directly supports one DDR channel, 64b wide (72b with ECC)

Supports 200-MHz and 266-MHz DDR devices

Supports 64-Mb, 128-Mb, 256-Mb, and 512-Mb technologies for x16 devices and x8 devices.

All supported devices have four banks

Configurable optional ECC operation (single bit Error Correction and multiple bit Error

Detection)

Supports up to 16 simultaneous open pages

Supports page sizes of 2 kB, 4 kB, 8 kB, and 16 kB. Page size is individually selected for every

row.

Thermal throttling scheme to selectively throttle reads and/or writes. Throttling can be

triggered by preset read/write bandwidth limits.

For DDR, Max of two, double-sided SODIMMs (four rows populated) with unbuffered

PC1600/PC2100 DDR (with or without ECC)

By using stacked 512-Mb technology, the largest memory capacity possible is 2.0 GB


1-5

System Interrupts

Supports 8259 and processor system bus interrupt delivery mechanism

Supports interrupts signaled as upstream Memory Writes from AGP/PCI (PCI semantics only)

and hub interface

MSI sent to the CPU through the System Bus

From IOxAPIC in ICH4-M

Supports peer MSI between hub interface and AGP

Provides redirection for upstream interrupts to the System Bus

Accelerated Graphics Port (AGP) Interface

Supports a single AGP device (either through a connector or on the motherboard)

AGP Support

Supports AGP 2.0 including 1x, 2x, and 4x AGP data transfers and 2x/4x Fast Write protocol

Supports only 1.5-V AGP electricals

32 deep AGP request queue

PCI semantic (FRAME# initiated) accesses to DRAM are snooped

AGP semantic (PIPE# and SBA) accesses to DRAM are not snooped

High priority access support

Hierarchical PCI configuration mechanism

Delayed transaction support for AGP-to- DRAM FRAME# semantic reads that can not be

serviced immediately

32-bit upstream address support for inbound AGP and PCI cycles

32-bit downstream address support for outbound PCI and Fast Write cycles

AGP Busy/Stop Protocol

AGP Clamping and Sense Amp Control

Hub Interface to ICH4-M

266 MB/s point-to-point hub interface to ICH4-M

66-MHz base clock

Supports the following traffic types to the ICH4-M

1 Hub interface-to-AGP memory writes

2 Hub interface-to-DRAM

3 CPU-to-hub interface

4 Messaging

-MSI Interrupt messages

-Power Management state change

-SMI, SCI, and SERR error indication


1-6

Power Management

SMRAM space remapping to A0000h (128 kB)

Supports extended SMRAM space above 256 MB, additional 128k/256k/512k/1 MB TSEG

from Top of Memory, cacheable (cacheability controlled by CPU)

APM Rev 1.2 compliant power management

Suspend to System Memory

ACPI 1.0b, 2.0 Support

Enhanced Intel SpeedStep® Technology Support

Cache coherency with CPU in sleep mode

Dynamic Memory Power-down

Package

Package options

593-pin Micro-FCBGA (37.5 x 37.5 mm)

C. South Bridge – ICH4-M

The ICH4 provides extensive I/O support. Functions and capabilities include:

PCI Local Bus Specification, Revision 2.2-compliant with support for 33-MHz PCI operations.

PCI slots (supports up to 6 Req/Gnt pairs)

ACPI Power Management Logic Support

Enhanced DMA Controller, Interrupt Controller, and Timer Functions

Integrated IDE controller supports Ultra ATA100/66/33

USB host interface with support for 6 USB ports; 3 UHCI host controllers; 1 EHCI high-speed

USB 2.0 Host Controller

Integrated LAN Controller

System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C

devices

Supports Audio Codec ’97, Revision 2.3 specification (a.k.a., AC ’97 Component Specification,

Revision 2.3). Link for Audio and Telephony codecs (up to 7 channels)

Low Pin Count (LPC) interface

Firmware Hub (FWH) interface support

Alert On LAN* (AOL) and Alert On LAN 2* (AOL2)


1-7

The ICH4 incorporates a variety of PCI functions that are divided into three logical devices (29, 30,

and 31) on PCI Bus 0 and one device on Bus 1. Device 30 is the Hub Interface-To-PCI bridge.

Device 31 contains all the other PCI functions, except the USB Controllers and the LAN Controller,

as shown in Table 1-2. The LAN controller is located on Bus 1.

PCI Devices and Functions

Feature PCI Bus Interface

Ø Supports PCI Revision 2.2 Specification at 33 MHz

Ø 133 MB/sec maximum throughput

Ø Supports up to 6 master devices on PCI

Ø One PCI REQ/GNT pair can be given higher arbitration priority (intended for external

1394 host controller)

Ø Support for 44-bit addressing on PCI using DAC protocol

Integrated LAN Controller

Ø WfM 2.0 and IEEE 802.3 compliant

Ø LAN Connect Interface (LCI)

Ø 10/100 Mbit/sec ethernet support

Integrated IDE Controller

Ø Supports “Native Mode” register and interrupts

Ø Independent timing of up to 4 drives, with separate primary and secondary IDE cable

connections


1-8

Ø Ultra ATA/100/66/33, BMIDE and PIO modes

Ø Tri-state modes to enable swap bay

USB

Ø Includes 3 UHCI host controllers that support 6 external ports

Ø New: Includes 1 EHCI high-speed USB 2.0 Host Controller that supports all six ports

Ø New: Supports a USB 2.0 high-speed debug port

Ø Supports wake-up from sleeping states S1-M–S5

Ø Supports legacy keyboard/mouse software

AC'97 Link for Audio and Telephony CODECs

Ø New: Third AC_SDATA_IN line for three codec support

Ø Supports AC ’97 2.3

Ø New: Independent bus master logic for 7 channels (PCM In/Out, Mic 1 input, Mic 2 input,

modem in/out, S/PDIF out)

Ø Separate independent PCI functions for audio and modem

Ø Support for up to six channels of PCM audio output (full AC3 decode)

Ø Supports wake-up events

Interrupt Controller

Ø Support up to 8 PCI interrupt pins

Ø Supports PCI 2.2 message signaled interrupts

Ø Two cascaded 82C59 with 15 interrupts

Ø Integrated I/O APIC capability with 24 interrupts

Ø Supports serial interrupt protocol

Ø Supports processor system bus interrupt delivery

New: 1.5 V operation with 3.3 V I/O

Ø 5V tolerant buffers on IDE, PCI, USB over-current and legacy signals

Timers Based on 82C54

Ø System timer, refresh request, speaker tone output

Power Management Logic

Ø ACPI 2.0 compliant

Ø ACPI-defined power states (C1–C4, S1-M, S3–S5)

Ø ACPI power management timer

Ø Support for “Intel® SpeedStepTM technology” processor power control

Ø Support for “Deeper Sleep” power state

Ø PCI CLKRUN# and PME# support

Ø SMI# generation

Ø All registers readable/restorable for proper resume from 0 V suspend states

External Glue Integration


1-9

Ø Integrated pull-up, pull-down and series termination resistors on IDE, processor interface

Ø Integrated Pull-down and Series resistors on USB

Enhanced Hub Interface buffers improve routing flexibility (Not available with all Memory

Controller Hubs)

Firmware Hub (FWH) Interface supports BIOS memory size up to 8 MB

Low Pin Count (LPC) Interface

Ø Supports two Master/DMA devices.

Enhanced DMA Controller

Ø Two cascaded 8237 DMA controllers

Ø PCI DMA: Supports PC/PCI — Includes two PC/PCI REQ#/GNT# pairs

Ø Supports LPC DMA

Ø Supports DMA collection buffer to provide Type-F DMA performance for all DMA

channels

Real-Time Clock

Ø 256-byte battery-backed CMOS RAM

System TCO Reduction Circuits

Ø Timers to generate SMI# and Reset upon detection of system hang

Ø Timers to detect improper processor reset

Ø Supports ability to disable external devices

SMBus

Ø New: Hardware packet error checking

Ø New: Supports SMBus 2.0 Specification

Ø Host interface allows processor to communicate via SMBus

Ø Slave interface allows an external microcontroller to access system resources

Ø Compatible with most 2-wire components that are also I2C compatible

GPIO

Ø TTL, open-drain, inversion

Package 31x31 mm 421 BGA

D. Clock Generator


1-10

The ICS950813 is a single chip clock solution for desktop designs using the

Brookdale/Odem/Montara-GM for P4/Banias processor.

The ICS950813 is part of a whole new line of ICS clock generators and buffers called TCHTM

( Timing Control Hub ). This part incorporates ICS’s newest clock technology with offers more

robust features and functionality. Employing the use of a serially programmable I2C interface, this

device can adjust the output clocks by configuring the frequency setting, the output divider rations,

selecting the ideal spread percentage, the output skew, the output strength, the enabling / disabling

each individual output clock. M/N control can configure output frequency with resolution up to 0.1

MHz increment.

Output Features 3 Differential CPU Clock Pairs @ 3.3V

7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks

3 PCI_F (3.3V) @ 33.3MHz

1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz

1 REF (3.3V) @ 14.318MHz

5 3V66 (3.3V) @ 66.6MHz

1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz

Features / Benefits Provides standard frequencies and additional 3%, 5% and 10% over-clocked frequencies

Supports spread spectrum modulation: No spread, Center Spread (±0.3%, ±0.55%), or Down Spread

(-0.5%, -0.75%)

Offers adjustable PCI early clock via latch inputs

Selectable 1X or 2X strength for REF via I2C interface

Programmable group to group skew

Linear programmable frequency and spreading %

Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#.

Uses external 14.318MHz crystal

Stop clocks and functional control available through I2C interface.


1-11

Key Specifications n CPU Output Jitter <150ps

n 3V66 Output Jitter <250ps

n CPU Output Skew <100ps

E. Video Graphics – ATi M11P

The MOBILITY M11 provides one of the fastest and most advanced 2D, 3D, and multimedia

graphics performance for notebooks. Its architecture introduces the latest achievements in the

graphics industry, which enable the use of the progressive new features in upcoming applications,

but without compromising performance. ATI’s support of DirectX® 9 features, highly optimized

OpenGL® support, and flexible memory configurations allow implementations targeted at the

gaming enthusiast, consumer, business and workstation platforms.

SMARTSHADER™ 2.0 — Advanced Shader Technology

Ø Provides complete hardware-accelerated support for the new DirectX® 9 programmable

shader model, enabling more complex and realistic texture and lighting effects than ever

before.

Ø Significant improvement over first-generation shaders introduced in DirectX® 8, with a

much more powerful and intuitive instruction set.

Ø Offers full support for this feature in OpenGL® applications.

SMOOTHVISION™ 2.0 — Flexible Anti-Aliasing and Anisotropic Filtering

Ø 2x/4x/6x full-scene anti-aliasing modes

Ø Adaptive algorithm with programmable sample patterns

Ø 2x/4x/8x/16x anisotropic filtering modes

Ø Adaptive algorithm with bi-linear (performance) and tri-linear (quality) options

High Performance Memory Support

Ø Incorporates support for DDR SDRAM/SGRAM.

Ø Features key items from ATI’s third generation HYPER Z™ III technology that conserves

memory bandwidth for improved performance in demanding applications.

Dual Display Support

Ø Leading-edge technology, fully optimized with HYDRA VISION™, flexibly supports

multiple combinations of notebook LCD, traditional CRT monitors, flat panel displays and


1-12

TV.

Ø Features Dual Channel DVI support.

Ø 230MHz LVDS transmitter supports LCD panels up to QXGA (2048x1536) resolution.

Ø Integrated 165MHz TMDS transmitter supports external flat panels up to UXGA

(1600x1200) resolution.

Ø High performance DAC speeds of 400MHz.

VIDEO Acceleration

Ø M11 allows the integration of industry leading digital video features, including advanced

de-interlacing algorithms for unprecedented video quality and integrated digital TV

decode capability. Includes programmable, independent gamma control for the video

overlay.

Ø New FULLSTREAM™ technology removes blocky artifacts from streaming and Internet

video and provides sharper image quality.

Ø Integrated general purpose xDCT engine (capable of performing both forward and inverse

discrete cosine transform) and motion compensation (MC) support for the acceleration of

MPEG encoding and decoding as well as DV (digital video) encoding and decoding.

Features In Detail 2D Acceleration Features

Ø A highly optimized 128-bit engine, capable of processing multiple pixels/clock.

Ø Hardware acceleration is provided for Bitblt, line drawing, polygon and rectangle fills, bit

masking, monochrome expansion, panning and scrolling, scissoring, and full ROP support

(including ROP3).

Ø Optimized handling of fonts and text using ATI proprietary techniques.

Ø Game acceleration including support for Microsoft's DirectDraw: Double Buffering,

Virtual Sprites, Transparent Blit, and Masked Blit.

Ø Acceleration in 8/15/16/32 bpp modes.

Ø Support for WIN 2000 & WIN XP GDI extensions: Alpha BLT, Transparent BLT,

Gradient Fill.

Ø Hardware cursor support up to 64x64x32bpp, with alpha channel for direct support of

WIN 2000 & WIN XP alpha cursor standard.

3D Acceleration Features

Ø Four parallel 3D rendering pipelines.

Ø Full DirectX9 Pixel Shader 2.0 support.

Ø Full DX9 conformance, including floating point per component at full speed.

Ø Support for 2xAA, 4xAA and 6xAA subsamples, with little performance loss in most

cases.


1-13

Ø Advanced AA quality algorithms, generating visuals that are superior to other solutions

with an equivalent number of samples.

Ø 2x/4x/8x/16x anisotropic filtering modes. Adaptive algorithm with bi-linear (performance)

and tri-linear (quality) options.

Ø Up to 16 unique textures, sharing 8 texture addresses.

Ø Dedicated geometry acceleration for Direct3D and OpenGL, which incorporates 2 parallel

Vector / Scalar Engines performing HW transformation, clipping and lighting, including:

Texture Coordinate Generation.

Vertex Blending (skinning) with 4 matrices.

6 user defined clip planes.

8 light support. Directional and Local Lighting.

Ø Fully compliant DirectX 9, Shader Model 2.0, Programmable Vertex Shader (full operand

and operation support) with up to 256 instructions and 256 vectors of constant store. This

includes Vertex Shader Loops, Branches, and Subroutines, which allow for vertex shader

programs of around 64,000 instructions in length.

Motion Video Acceleration Features

Ø Video scaling and fully programmable YCrCb to RGB color space conversion for

full-screen / full-speed video playback and fully adjustable color controls.

Ø Hardware I2C.

Ø VIP 2.0 with multi channel DMA transfer.

Ø 16-bit Zoom Video port.

Ø Front end scaler support for 8, 15, 16, and 32 bpp color depths.

Ø Back end overlay/scaler supports up to 8x4 tap filtering, and always ensures at least 4x2

tap filtering even in extreme cases. 4x4 tap is typical. Back-end scaler also supports

upscaling and downscaling, filtered scaling of all supported YUV formats, RGB32 and

RGB15/16, and filtered display of images up to 1536 pixels wide.

Ø Enhanced MPEG-2 hardware encode/decode acceleration, including support for:


1-14

Integrated general purpose xDCT engine (capable of performing

both forward and inverse discrete cosine transform)

Motion compensation (MC) support for the acceleration of MPEG

encoding and decoding as well as DV (digital video) encoding and

decoding.

Parallel operation of the xDCT and MC and high processing rates

with minimal software overhead Ø Provides dramatically reduced CPU utilization without incurring the cost of a full

MPEG-2 decoder.

Ø MPEG-4 simple profile support.

Ø Supports all format DTV/HDTV decode and top quality DVD with lowest CPU usage.

(Note: DTV/HDTV support is through component output, not DVI.)

Ø Adaptive de-interlacing filter eliminates video artifacts caused by displaying interlaced

video on non-interlaced displays, by analyzing image and using optimal de-interlacing

function on a per-pixel basis.

Dual Display Features

General

Ø Hydravision for dual monitor support.

Ø Dual independent displays (LCD/DVI, DVI/CRT, LCD/TV, CRT/TV, etc.)

Ø Two independent CRT controllers to support two asynchronous simultaneous display

paths.

Ø Integrated second DAC for the second CRT (TV) support.

Ø Two triple 10-bit palette DACs with gamma correction for true WYSIWYG color. Pixel

rates up to 400MHz standard.

Ø Resolution, refresh rates and display data can be completely independent.

Ø Primary display path supports VGA and accelerated modes, video overlay, hardware

cursor, and palette gamma correction.

Ø Secondary display path supports accelerated modes, video overlay, hardware cursor, and

palette gamma correction. However, it does not support VGA.


1-15

Ø Single video overlay using back-end scaler is switchable between displays.

Ø Supports two new graphics formats: 16bpp aRGB 4444 and 16bpp alpha and index 88.

Also supports 8/15/16/24/32 bpp graphics formats with gamma correction in all modes.

Ø Support for auxiliary window signal.

Ø Support for up to 4k x 4k resolution display.

Ø Support for DDC1 and DDC2B+ for plug and play monitors, and AppleSense monitor

detection support.

Ø 8-bit alpha blending of graphics and video overlay.

Ø Independent DDC lines for DAC and TMDS connections. Also full AppleSense support

on DAC connection.

Ø Hardware cursor up to 64x64 pixels in 2bpp, full color AND/XOR mix, and full color 8-bit

alpha blend.

Ø Independent h/w icon & h/w cursor on both display paths (simultaneous h/w cursor &

icon).

Ø Virtual desktop support.

TV Out

An integrated TV encoder with on-chip triple DAC allows simultaneous CRT/LCD/TV

output with these outstanding TV-out characteristics:

Ø 10-bit DAC with 8-tap filter producing scaled, flicker removed, artifact suppressed

display on a PAL or NTSC TV with Composite, S-Video, and RGB outputs.

Ø Support for Macrovision 7.02 copy protection standard (required by DVD players) - a

fully programmable timing capability, it will accommodate potential changes in the

Macrovision algorithm without any hardware changes.

Ø YUV Direct/Pass through mode for video/MPEG playback and DVD provides the best

quality movie playback, it also allows titles to be displayed on TV with their original high

quality and without any artifact from the TV-out circuit.

Ø Secondary display support for the RGB mode.

Ø 1024x768 32bpp support. Modes supported include 800x600 and 16:9 modes such as

848x480, with user flexibility for moving and sizing the screen.

Ø Line 21 Closed Caption and Extended Data Service support for encoding in Vertical

Blanking Interval (VBI) of TV signal.

Ø CGMS-A DVD copy management support in VBI through Line-20 and/or Extended Data

Service (Line-21 Field 2).

Ø UV filtering based on color averaging results in a sharper picture as well as reduced

flicker.

Ø ATI's exclusive "Composite Dot Crawl" freeze option for PAL and NTSC to improve

picture quality.

Component output


1-16

Ø Component output (YPbPr) for 480i, 480p, 720p and 1080i (NTSC only).

Ø No support for scaling or flicker removal to component video outputs.

Ø Includes NTSC Macrovision and CGMS.

Digital Display Support

General

Ø Support for fixed resolution displays (e.g. panels) from VGA (640x480) to wide UXGA

(1600x1200) resolution with full ratiometric expansion ability for source modes up to

1280x1024. Higher resolution panels and digital CRTs may be possibly supported -

contact ATI for details.

Ø Improved auto expansion.

Ø Optional auto-centering mode to display desktop at native size without ratiometric

expansion.

Ø Support for VGA text modes in centering panel modes (up to approximately 165 MHz

pixel frequency).

Ø Support for reduced blanking intervals, as defined by VESA.

Ø HDCP ready.

LVDS

An integrated LVDS transmitter for excellent LCD image quality:

Ø Single and dual pixel per clock, up to 230MHz dual-channel (115MHz per channel)

Ø Supports LCD panels up to QXGA (2048x1536) 60Hz resolution.

Ø General purpose I/O pins that allows support of LCD panel detection.

Ø Conformance with OpenLDI and VESA FPDI specifications.

Ø Common Panel Interface Specification (CPIS) compliant.

Ø Ratiometric expansion with improved sharpness for top image quality when scaling up

from a non-native resolution.

TMDS

Ø Integrated TMDS transmitter running up to 165MHz (supports both coherent and

non-coherent clocking systems) for support up to 1600x1200 at 60Hz. Fully Compliant

with DVI and DFP connection standards. Ratiometric expansion.

Ø Support for external TMDS transmitter via digital output (configurable as a 12 bit or 24 bit

DDR bus) to drive most popular TMDS transmitters up to 165MHz frequency.

Ø Supports DVI, DFP and VESA P&D interfaces with integrated TMDS transmitter.

Ø TMDS transmitter fully supports reduced blanking.

Bus Support Features

Ø Comprehensive AGP support:


1-17

AGP3.0 mode: 4X and 8X operation.

AGP2.0 mode (1.5V signaling only)

Sideband Addressing.

AGP Texturing (Execute mode).

Both AGP reads and writes (with support for the ‘fast write’

capability defined in revision 2.0 of the AGP specification). Ø PCI 2.3 compliance (using AGP electrical interface).

Memory Support Features

Ø 128/64-bit memory interface using DDR SGRAM, SDRAM or DDRII SDRAM to build

16/32/64/128/256 MB configurations.

Ø Support for SSTL-2, and SSTL-1.8 (1.8V self-terminated) memory interfaces.

Ø Supports Elpida DDR SDRAM, which is similar to the DDR protocol with the following

exceptions:

Lower power through the use of data inversion signals for both

writes and reads

Higher clock speeds with no external termination required

Power Management Features

Ø Single chip solution in 0.13 micron, 1.0V-1.2V CMOS technology

Ø Full ACPI 1.0b, OnNow, and IAPC (Instantly Available PC) power management.

Ø PCI bus power management 1.1 and AGP Busy and Stop signals Rev 1.61 and Solano

2-M.

Ø Static and dynamic Power Management support (APM as well as ACPI) with full VESA

DPM and Energy Star compliance.

Ø AGP_BUSY/STP_AGP power management.

Ø Full POWERPLAYTM, including enhanced POWER ON DEMAND support.

Ø The Chip Power Management Support logic supports four device power states - On,

Standby, Suspend and Off - defined for the OnNow Architecture. Each power state can be


1-18

achieved by software control bits.

Ø Clocks to every major functional block are controlled by a unique dynamic clock

switching technique which is completely transparent to the software. By turning off the

clock to the block that is idle or not used at that point, the power consumption is

significantly reduced during normal operation.

Internal LVDS Spread Spectrum Support

Ø The MOBILITY M11 Spread Spectrum controller is capable of generating a triangular

frequency modulation profile. The amount of spread and the modulation frequency is fully

programmable.

Ø Only the LVDS display is available to be spread (i.e., 1 PLL).

External Spread Spectrum Support

Ø Memory and/or core clock spread spectrum support via the GPIO16 pin.

Ø External spread spectrum supported for TMDS or LVDS transmitters via the

SSIN/SSOUT pin.

PC Design Guide Compliance

MOBILITY M11 complies with all relevant sections of the current PC design guide specifications

from Intel/Microsoft.

Ø Fully compliant with PC99, PC99a, and PC 2001 requirements.

Ø Fully compliant with Mobile PCI rev 1.0.

Ø Bi-endian support for compliance on a variety of processor platforms.

Test Capability Features

The MOBILITY M11 has a variety of test modes and capabilities that provide a very high fault

coverage and low DPM (defect per million) ratio:

Ø Full scan implementation on the digital core logic which provides high fault coverage

through ATPG (Automatic Test Pattern Generation Vectors).

Ø Dedicated test logic for the on-chip custom memory macros to provide complete coverage

on these modules.

Ø A JTAG test mode (which is not entirely compliant to the IEEE 1149.1 standard) for access

to chip-level test functions and for board level connectivity testing.

Ø Integrated hardware diagnostic tests performed automatically upon initialization.

Ø High quality components through at-speed testing, built-in Scan, Iddq, CRC, chip


1-19

diagnostics, and XOR tree.

Ø IEEE 1149.1 Scan path interface.

Ø An XORTREE test mode on all the digital I/O's to allow for proper soldering verification

at the board level.

Ø Improved access to the analog modules and PLLs in the MOBILITY M11 in order to allow

full evaluation and characterization of these modules.

Ø Improved IDDQ mode support to allow chip evaluation through current leakage

measurements.

Other Features

Ø Support for ROM or Flash RAM parallel or serial video BIOS.

Ø Includes patent pending hardware support for the Windows 2000 and Windows XP alpha

cursor, as well as acceleration of new GDI extensions such as Alpha BLTs, Transparent

BLTs, and Gradient Fills.

Compliance with Wassenaar Agreement

Ø 3D vector rate (as defined by the Wassenaar Agreement) is 18 - 23 M 10-pixel

vectors/sec for all of M11-CSP64, M11-CSP128.

F. PCMCIA OZ711MC1

Feature

Ø Single-Slot CardBus Controller

Ø Integrated Smart Card Reader (SCR) Controllers

Ø Integrated Flash Media Reader (FMR) Controllers

Ø One Optional Dedicated Reader (ODR) Port

PC Card/PCI Features

Ø Pin Compatible with OZ6912, OZ711EC1, and

OZ711M1 Single Socket Controllers

Ø Pin Upgradeable to OZ711MP1, Adding 1394

Ø PC Card Standard Release 8.1 Compliant

Ø Supports USB PC Cards with NewSwitch™ Device


1-20

Ø Compliant with PCI Local Bus Specification Version 2.3

Ø Provides Pipelined PCI/CardBus burst data transfers

Ø Supports Parallel and Serial Interfaces to O2Micro’s

OZ2211, OZ2216, and NewSwitch™ Power Switches

Smart Card Features

Ø Supports Patented SmartCardBus® Operating Mode

Ø Provides Optional Dedicated Smart Card Reader

Ø Supports SmartCardBus® PC Card Passive Adapters

Ø EMV Certified Smart Card Reader Core

Ø Supports Asynchronous and Synchronous Cards

Ø ODR Interface Supports USB Smart Cards

Ø Complies to ISO7816, PC/SC, EMV, and CT-API (B1)

Flash Media Features

Ø Host Controller Supports MultiMediaCard (MMC), and SD Memory Cards

Ø MS/MSPro Host Controller Supports 1-bit Memory Stick™ and 4-bit Memory Stick™ PRO

Media Cards

Ø PC Card Socket Supports MMC/SD/MS/MSPro Using O2Micro’s MemoryCardBus™ Passive

Adapters

Ø MultiMediaCard (MMC) Version 2.2 Compliant

Ø Supports SD Memory Card CPRM Security Mode

Power Management Features

Ø Auxiliary Power Supply (VAUX) For D3COLD Standby

Ø ACPI-PCI Bus Power Management Rev 1.1 Compliant

Ø Supports OnNow LAN Wake-up, Ring Indicate,

CardBus Wake Signaling via PME#, and CLKRUN#

OZ2216

The OZ2216 is a dual slot PCMCIA (Personal Computer Memory Card International Association)

PC Card and CardBus power controller. It is used in conjunction with a serial data output, CardBus

controller to control and distribute VCC and VPP voltages to two PC Card slots. When connected to

3.3V, 5V, and 12V system power supplies, the OZ2216 can switch its VCC and VPP outputs between

0V, 3.3V, and 5.0V, in accordance with the control commands from the three-wire serial interface.

The OZ2216 also features low on-resistance MOSFET switches for 5V and 3.3V VCC.

The OZ2216 operation does not require 12V and 5V supplies, making it possible to operate the PC

cards in lowpower 3.3V modes. The internal logic and the MOSFET


1-21

drive circuitry are powered by the 3V supply input. The OZ2216 also features a standby mode that

changes all the output-current limits to 50mA (typical).

The OZ2216 is protected by over temperature shutdown, and it protects itself and the system with

current limiting and cross-conduction lockout.

The OZ2216 is designed for full compatibility with the PCMCIA PC Card Specification,

including the CardBus and Zoomed Video (ZV) options, and is pin-to-pin compatible with

O2Micro’s OZ2206 and Texas Instrument’s

TPS2206/2216.

Feature

Ø Complete VCC and VPP switch for dual-slot PC Card interface

Ø Standard 3-wire serial interface compatible with CardBus Controllers

Ø High-efficiency, low-resistance switches

Ø Meets PC Card standard

Ø Compatible with 3.3V, 5V and 12V PC Cards

Ø Operates in 3.3V low voltage mode when 3.3V is the only available input voltage

Ø Standby Mode: 50-mA Current Limit (Typical)

Ø Current limit and over temperature shutdown

Ø 12V supply can be disabled except during 12V Flash memory programming

Ø Break-before-make switching

Ø Low on-resistance for 5V VCC

Ø Low on-resistance for 3.3V VCC

G. IEEE 1394 – TSB43AB22A

The Texas Instruments TSB43AB22A device is an integrated 1394a-2000 OHCI PHY/link-layer

controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus

Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the

1394 Open Host Controller Interface

Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at

100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB22A device provides two 1394 ports that

have separate cable bias (TPBIAS). The TSB43AB22A device also supports the IEEE Std

1394a-2000 power-down features for battery-operated applications and arbitration enhancements.


1-22

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std

1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI

configuration header is accessed through configuration cycles specified by PCI, and it provides

plug-and-play (PnP) compatibility. Furthermore, the TSB43AB22A device is compliant with the

PCI Bus Power Management Interface Specification as specified by the PC 2001 Design Guide

requirements. The TSB43AB22A device supports the D0, D1, D2, and D3 power states.

The TSB43AB22A design provides PCI bus master bursting, and it is capable of transferring a

cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency

can be large, deep FIFOs are provided to buffer the 1394 data. The TSB43AB22A device provides

physical write posting buffers and a highly-tuned physical data path for SBP-2 performance. The

TSB43AB22A device also provides multiple isochronous contexts, multiple cacheline burst

transfers, advanced internal arbitration, and bus-holding buffers.

An advanced CMOS process achieves low power consumption and allows the TSB43AB22A

device to operate at PCI clock rates up to 33 MHz.

The TSB43AB22A PHY-layer provides the digital and analog transceiver functions needed to

implement a two-port node in a cable-based 1394 network. Each cable port incorporates two

differential line transceivers. The transceivers include circuitry to monitor the line conditions as

needed for determining connection status, for initialization and arbitration, and for packet reception

and transmission.

The TSB43AB22A PHY-layer requires only an external 24.576-MHz crystal as a reference for

the cable ports. An external clock may be provided instead of a crystal. An internal oscillator drives

an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal.

This reference signal is internally divided to provide the clock signals that control transmission of

the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the

integrated LLC for synchronization and is used for resynchronization of the received data.

Data bits to be transmitted through the cable ports are received from the integrated LLC and are

latched internally in synchronization with the 49.152-MHz system clock. These bits are combined

serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100,

S200, or S400 speeds, respectively) as the outbound data-strobe information stream. During

transmission, the encoded data information is transmitted differentially on the twisted-pair B (TPB)

cable pair(s), and the encoded strobe information is transmitted differentially on the twisted-pair A

(TPA) cable pair(s).


1-23

During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled,

and the receivers for that port are enabled. The encoded data information is received on the TPA

cable pair, and the encoded strobe information is received on the TPB cable pair. The received

data-strobe information is decoded to recover the receive clock signal and the serial data bits. The

serial data bits are resynchronized to the local 49.152-MHz system clock and sent to the integrated

LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports.

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line

states during initialization and arbitration. The outputs of these comparators are used by the internal

logic to determine the arbitration status. The TPA channel monitors the incoming cable

common-mode voltage. The value of this

common-mode voltage is used during arbitration to set the speed of the next packet transmission. In

addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for

the presence of the remotely supplied twisted-pair bias voltage.

The TSB43AB22A device provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port

termination. The PHY layer contains two independent TPBIAS circuits. This bias voltage, when

seen through a cable by a remote receiver, indicates the presence of an active connection. This bias

voltage source must be stabilized by an external filter capacitor of 1.0 μF.

The line drivers in the TSB43AB22A device operate in a high-impedance current mode and are

designed to work with external 112-Ω line-termination resistor networks in order to match the 110-Ω

cable impedance. One network is provided at each end of a twisted-pair cable. Each network is

composed of a pair of series-connected 56-Ω resistors. The midpoint of the pair of resistors that is

directly connected to the TPA terminals is connected to its corresponding TPBIAS voltage terminal.

The midpoint of the pair of resistors that is directly connected to the TPB terminals is coupled to

ground through a parallel R-C network with recommended values of 5 kΩ and 220 pF. The values of

the external line-termination resistors are designed to meet the standard specifications when

connected in parallel with the internal receiver circuits. An external resistor connected between the

R0 and R1 terminals sets the driver output current and other internal operating currents. This

current-setting resistor has a value of 6.34 kΩ ±1%.

When the power supply of the TSB43AB22A device is off and the twisted-pair cables are

connected, the TSB43AB22A transmitter and receiver circuitry present a high impedance to the

cable and do not load the TPBIAS voltage at the other end of the cable.

When the device is in a low-power state (for example, D2 or D3) the TSB43AB22A device

automatically enters a low-power mode if all ports are inactive (disconnected, disabled, or


1-24

suspended). In this low-power mode, the TSB43AB22A device disables its internal clock generators

and also disables various voltage and current reference circuits, depending on the state of the ports

(some reference circuitry must remain active in order to detect new cable connections,

disconnections, or incoming TPBIAS, for example). The lowest power consumption (the

ultralow-power sleep mode) is attained when all ports are either disconnected or disabled with the

port interrupt enable bit cleared.

The TSB43AB22A device exits the low-power mode when bit 19 (LPS) in the host controller

control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to

1 or when a port event occurs which requires that the TSB43AB22A device to become active in

order to respond to the event or to notify the LLC of the event (for example, incoming bias is

detected on a suspended port, a disconnection is detected on a suspended port, or a new connection is

detected on a nondisabled port). When the TSB43AB22A device is in the low-power mode, the

internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within

2 ms after bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section

4.16, Host Controller Control Register) is set to 1.

The TSB43AB22A device supports hardware enhancements to better support digital video (DV)

and MPEG data stream reception and transmission. These enhancements are enabled through the

isochronous receive digital video

enhancements register at OHCI offset A88h (see Chapter 5, TI Extension Registers). The

enhancements include automatic timestamp insertion for transmitted DV and MPEG-formatted

streams and common isochronous packet (CIP) header stripping for received DV streams.

The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the

isochronous data contexts are implemented as hardware support for the synchronization timestamp

for both DV and MPEG CIP formats. The TSB43AB22A device supports modification of the

synchronization timestamp field to ensure that the value inserted via software is not stale—that is,

the value is less than the current cycle timer when the packet is transmitted.

1.1.1.Features Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus† and

IEEE Std 1394a-2000

Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394

Compliant with Intel Mobile Power Guideline 2000

Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset,

multispeed concatenation, arbitration acceleration, fly-by concatenation, and port

disable/suspend/resume

Power-down features to conserve energy in battery-powered applications include: automatic device


1-25

power down during suspend, PCI power management for link-layer, and inactive ports powered

down

Ultralow-power sleep mode

Two IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s

Cable ports monitor line conditions for active connection to remote node

Cable power presence monitoring

Separate cable bias (TPBIAS) for each port

1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling

environments

Physical write posting of up to three outstanding transactions

PCI burst transfers and deep FIFOs to tolerate large host latency

PCI_CLKRUN# protocol

External cycle timer control for customized synchronization

Extended resume signaling for compatibility with legacy DV components

PHY-Link logic performs system initialization and arbitration functions

PHY-Link encode and decode functions included for data-strobe bit level encoding

PHY-Link incoming data resynchronized to local clock

Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and

400M bits/s

Node power class information signaling for system power management

Serial ROM interface supports 2-wire serial EEPROM devices

Two general-purpose I/Os

Register bits give software control of contender bit, power class bits, link active control bit, and

IEEE Std 1394a-2000 features

Fabricated in advanced low-power CMOS process

PCI and CardBus register support

Isochronous receive dual-buffer mode

Out-of-order pipelining for asynchronous transmit requests

Register access fail interrupt when the PHY SCLK is not active

H. LAN – Ethernet Controller – RTL8100C


1-26

The Realtek RTL8100C(L) is a highly integrated, cost-effective single-chip Fast Ethernet controller

that provides 32-bit performance,

PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and

IEEE 802.3x Full Duplex Flow Control. It also supports the Advanced Configuration Power

management Interface (ACPI), PCI power management for modern operating systems that are

capable of Operating System Directed Power Management (OSPM) to achieve the most efficient

power

management possible. The RTL8100C(L) does not support CardBus mode as the RTL8139C does.

In addition to the ACPI feature, the RTL8100C(L) also supports remote wake-up (including AMD

Magic Packet, LinkChg, and Microsoft® wake-up frame) in both ACPI and APM environments.

The RTL8100C(L) is capable of performing an internal reset through the application of auxiliary

power. When auxiliary power is applied and the main power remains off, the RTL8100C(L) is ready

and waiting for the Magic Packet or Link Change to wake the system up. Also, the LWAKE pin

provides 4 different output signals including active high, active low, positive pulse, and negative

pulse. The versatility of the RTL8100C(L) LWAKE pin provides motherboards with

Wake-On-LAN (WOL) functionality.

The RTL8100C(L) also supports Analog Auto-Power-down, that is, the analog part of the

RTL8100C(L) can be shut down temporarily according to user requirements or when the

RTL8100C(L) is in a power down state with the wakeup function disabled.

In addition, when the analog part is shut down and the IsolateB pin is low (i.e. the main power is off),

then both the analog and digital parts stop functioning and the power consumption of the

RTL8100C(L) will be negligible. The RTL8100C(L) also

supports an auxiliary power auto-detect function, and will auto-configure related bits of their own

PCI power management registers in PCI configuration space.

The PCI Vital Product Data(VPD) is also supported to provide the information that uniquely

identifies hardware (i.e., the OEM brand name of RTL8100C(L) LAN card). The information may

consist of part number, serial number, and other detailed

information.

To provide cost down support, the RTL8100C(L) is capable of using a 25MHz crystal or OSC as

its internal clock source.

The RTL8100C(L) keeps network maintenance costs low and eliminates usage barriers. It is the

easiest way to upgrade a network

from 10 to 100Mbps. It also supports full-duplex operation, making 200Mbps bandwidth possible at

no additional cost. To improve compatibility with other brands. products, the RTL8100C(L) is also

capable of receiving packets with InterFrameGap no less than 40 Bit-Time. The RTL8100C(L) is

highly integrated and requires no .glue. logic or external memory.


1-27

1.1.2.Feature Ø 128 pin QFP/LQFP

Ø Integrated Fast Ethernet MAC, Physical chip and transceiver in one chip

Ø 10 Mb/s and 100 Mb/s operation

Ø Supports 10 Mb/s and 100 Mb/s N-way

Auto-negotiation operation

Ø PCI local bus single-chip Fast Ethernet controller

Ø Compliant to PCI Revision 2.2

Ø Supports PCI clock 16.75MHz-40MHz

Ø Supports PCI target fast back-to-back transaction

Ø Provides PCI bus master data transfers and PCI memory space or I/O space mapped data

transfers of RTL8100C(L)’s operational registers

Ø Supports PCI VPD (Vital Product Data)

Ø Supports ACPI, PCI power management

Ø Supports 25MHz crystal or 25MHz OSC as the internal clock source. The frequency deviation

of either crystal or OSC must be within 50 PPM.

Ø Compliant to PC99/PC2001 standard

Ø Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and

Microsoft® wake-up frame)

Ø Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative

pulse)

Ø Supports auxiliary power-on internal reset, to be readyfor remote wake-up when main power

still remains off

Ø Supports auxiliary power auto-detect, and sets the related capability of power management

registers in PCI configuration space.

Ø Includes a programmable, PCI burst size and early Tx/Rx threshold.

Ø Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate

timer-interrupt

Ø Contains two large (2Kbyte) independent receive and transmit FIFOs

Ø Advanced power saving mode when LAN function or wakeup function is not used

Ø Uses 93C46 (64*16-bit EEPROM) to store resource configuration, ID parameter, and VPD

data.

Ø Supports LED pins for various network activity indications

Ø Supports loop back capability

Ø Half/Full duplex capability

Ø Supports Full Duplex Flow Control (IEEE 802.3x)

Ø 2.5/3.3V power supply with 5V tolerant I/Os.


1-28

Ø 0.25u CMOS process

I. Audio

AC97 Controller – VIA: VT1612A

VIA Technologies’ VT1612ATM 18-bit ∑∆ audio codec conforms to the AC’97 2.2 and the S/PDIF

specification. The VT1612A integrates Sample Rate Converters and can be adjusted in 1Hz

increments. The analog mixer circuitry integrates a stereo enhancement to provide a pleasing 3D

surround sound effect for stereo media.

Furthermore, an integrated headphone amplifier with thermal shutdown adds signal value by

reducing the BOM. This codec is designed with aggressive power management to achieve low

power consumption. When used with 3.3V analog

supply, power consumption is further reduced. The primary applications for this part are desktop and

portable personal computers multimedia subsystems. However, it is suitable for any audio

subsystem requiring stereo audio input/output with S/PDIF digital output at competitive prices.

Feature

Ø AC’97 2.2 S/PDIF extension compliant codec

Ø 18-bit stereo full duplex SD codec

Ø 1Hz resolution VSR (Variable Sampling Rate)

Ø Integrated IEC958 line driver for S/PDIF

Ø S/PDIF compressed digital or LPCM audio out

Ø 3D stereo expansion for simulated surround

Ø 18-bit independent rate stereo ADC/DAC

Ø Hardware VU peak meters for PCM streams

Ø 4 stereo, 2 mono analog line-level inputs

Ø Alt. line-level output with volume control, or

Ø Headphone Amplifier with Thermal Protection

Ø Low Power consumption mode

Ø Exceeds Microsoft® WHQL logo requirements

Ø 3.3V digital, 3.3 or 5V analog power supply

Ø 48-pin LQFP small footprint package.

Amplifier – TI : TPA6011A


1-29

The TPA6011A4 is a stereo audio power amplifier that drives 2 W/channel of continuous RMS

power into a 3-Ω load. Advanced dc volume control minimizes external components and allows

BTL (speaker) volume control and SE (headphone) volume control. Notebook and pocket PCs

benefit from the integrated feature set that

minimizes external components without sacrificing functionality.

To simplify design, the speaker volume level is adjusted by applying a dc voltage to the VOLUME

terminal. Likewise, the delta between speaker volume and headphone volume can be adjusted by

applying a dc voltage to the SEDIFF terminal. To avoid an unexpected high volume level through

the headphones, a third terminal, SEMAX, limits the headphone volume level when a dc voltage is

applied. Finally, to ensure a smooth transition between active and shutdown modes, a fade mode

ramps the volume up and down.

Feature

Ø Advanced DC Volume Control With 2-dB Steps From –40 dB to 20 dB

Ø Fade Mode

Ø Maximum Volume Setting for SE Mode

Ø Adjustable SE Volume Control Referenced to BTL Volume Control

Ø 2 W Into 3-Ω Speakers

Ø Stereo Input MUX

Ø Differential Inputs APPLICATIONS

Ø Notebook PC

Ø LCD Monitors

Ø Pocket PC

Woofer LM4871

The LM4871 is a mono bridged audio power amplifier capable of delivering 3W of continuous

average power into a 3W load with less than 10% THD when powered by a 5V power supply (Note

1). To conserve power in portable applications, the LM4871’s micropower shutdown mode (IQ =

0.6µA, typ) is activated when VDD is applied to the SHUTDOWN pin.

Boomer audio power amplifiers are designed specifically to provide high power, high fidelity audio

output. They require few external components and operate on low supply voltages from 2.0V to

5.5V. Since the LM4871 does not require output coupling capacitors, bootstrap capacitors, or

snubber networks, it is ideally suited for low-power portable systems that require minimum volume

and weight.

Additional LM4871 features include thermal shutdown protection, unity-gain stability, and external


1-30

gain set.

Note 1: An LM4871LD that has been properly mounted to a circuit board will deliver 3W into 3W

(at 10% THD). The other package options for the LM4871 will deliver 1.5W into 8W (at 10% THD).

See the Application Information sections for further information concerning the LM4871LD,

LM4871MM, LM4871M, and the LM4871N.

Key Specifications

PO at 10% THD+N, 1kHz

LM4871LD: 3W , 4W loads 3W (typ), 2.5W (typ)

All other LM4871 packages: 8W load 1.5W (typ)

Shutdown current 0.6µA (typ)

Supply voltage range 2.0V to 5.5V

THD at 1kHz at 1W continuous average output power into 8W 0.5% (max)

Features

No output coupling capacitors, bootstrap capacitors, or snubber circuits required Unity-gain

stable

LLP, MSOP, SO, or DIP packaging

External gain configuration capability

Pin compatible with the LM4861

Applications

Ø Portable computers

Ø Desktop computers

Ø Low voltage audio systems

LMV821

The LMV821/LMV822/LMV824 bring performance and economy to low voltage low power

systems. With a 5 MHz unity-gain frequency and a guaranteed 1.4 V/µs slew rate, the quiescent

current is only 220 µA/amplifier (2.7 V). They provide rail-to-rail (R-to-R) output swing into heavy

loads (600 Ω Guarantees). The input common-mode voltage range includes ground, and the

maximum input offset voltage is 3.5mV (Guaranteed). They are also capable of comfortably driving

large capacitive loads (refer to the application notes section).

The LMV821 (single) is available in the ultra tiny SC70-5 package, which is about half the size of

the previous title holder, the SOT23-5.

Overall, the LMV821/LMV822/LMV824 (Single/Dual/Quad) are low voltage, low power,

performance op amps, that can be designed into a wide range of applications, at an economical price.


1-31

Features

(For Typical, 5 V Supply Values; Unless Otherwise Noted)

Ultra Tiny, SC70-5 Package 2.0 x 2.0 x 1.0 mm

Guaranteed 2.5 V, 2.7 V and 5 V Performance

Maximum VOS 3.5 mV (Guaranteed)

VOS Temp. Drift 1 uV/° C

GBW product @ 2.7 V 5 MHz

ISupply @ 2.7 V 220 µA/Amplifier

Minimum SR 1.4 V/us (Guaranteed)

CMRR 90 dB

PSRR 85 dB

VCM @ 5V -0.3V to 4.3V

Rail-to-Rail (R-to-R) Output Swing

Ø @600 Ω Load 160 mV from rail

Ø @10 kΩ Load 55 mV from rail

Stable with High Capacitive Loads (Refer to Application Section)

J. Embedded Controller IT8510E

The bridge provides the host to access the shared memory. It also provides EC code address space

mapped into host domain address space, and locking mechanism for read/write protection.

“Read Cycle Time” and “Write Cycle Time” of the flash/EPROM have to be faster than or equal to

tFRDD (Refer to Table 9-8. Flash Read Cycle AC Table).

Host to M Bus Translation

The SMFI provides an interface between the host bus and the M bus, the flash is mapped into the

host memory address space for host accesses, the flash is also mapped into the EC memory address

space for EC accesses.

An M bus transaction is generated by the host bus translations and has the following thee types:

Ø 8-bit LPC Memory Read/Write

Ø 8-bit FWH Read/Write

Ø 8-bit Indirect Memory Read/Write

After the LPC address translation is done, the host memory transaction is forwarded to M-bus

(flash interface) if it is accessing an unprotected region. The host side can’t issue a write transaction

until the firmware write 1 to HOSTWA bit SMECCS register. See also Table 3-3 on page 8 and

Table 3-4 on page 8.


1-32

Note: The flash bus doesn’t have the highest performance until writing 00h to MZCFG register and

08h to SMZCFG register.

Memory Mapping

The host memory addresses are mapped into the following regions shown in the following table.

Some regions are always mapped and some are mapped only when the corresponding register is

active. And these regions may be mapped into the same range in the flash space

Features Ø Supports memory mapping between host domain and EC domain

Ø Supports read/write/erase flash operations and locking mechanism

Ø Supports two shared memory access paths: host and EC

Ø Supports two flash contents protection: different access paths and different memory block

Ø Supports timing control for memory device (flash)

1.2 Software Specification

A. System Memory The System consists of DDR SDRAM memory on 64-bit bus and the size options are

8/16/32/64/128/256/512MB on each DIMM slot. The BIOS will automatically detect the amount of

memory during the POST. But the total RAM size can be used by user must be substrated by the size

of the video shared memory.

4.2

Enhanced IDE

The enhanced IDE specification has defined many data transfer modes as following:

1. PIO Mode 0, 1, 2, 3, 4

2. Multiword DMA Mode 0, 1, 2, 3, 4 ,5

3. Ultra DMA-33/66/100/133

4. Which transfer mode will be set depend on the used devices, core chip IDE interface

and BIOS supported. This model’s BIOS support all the data transfer modes above,

and it will auto detect and initialize it during POST. The Ultra DMA-33/66/100/133 is

a new physical protocol used to transfer data between an Ultra DMA-33/66 capable

IDE controller and one or more Ultra DMA-33/66 capable IDE devices.


1-33

B. Audio The audio controller is integrated in south bridge ICH4 and through the AC97 data line to external

CODEC to reduce the noise caused by PCB’s layout. However the H/W architecture is, the BIOS

will recognize it as a PCI device and initialize it in PCI bus initialization. The PCI legacy audio mode

is not to be supported.

C. Modem

The system can use all of the modem that is AC97’ compliance and the MDC form factor. During

POST need to detect the existence and setting proper registers in south bridge ICH4.

D. PCMCIA

The system BIOS need to support some devices (especially the LAN card) need to work in

Pure-DOS, such as MS-DOS 6.22.

E. LED Indicator

In the system has some LED and listed below:

Indicator Function Description HDD LED The LED will turn on when the hard disk drive is activated or accessed CDROM LED The LED will turn on when the CDROM drive is activated or accessed NumLock LED The LED will turn on when the function of NumLock is active CapsLock LED The LED will turn on when the function of CapsLock is active. ScrollLock LED The LED will turn on when the function of ScrollLock is active.

Additionally, there are two LEDs more complicate than above, they have compound status and

style to indicate the system state and battery status. So that will be listed in below table: System Off (w/o charging) Off Off System Off (w/ charging) Off Orange Blinking System On (w/o charging) Off Green System On (w/ charging) Off Orange Blinking


1-34

Suspend Mode (w/o charging) Green Blinking Green Suspend Mode (w/ charging) Green Blinking Orange Blinking System State (Battery Status) Suspend LED Adapter LED

F. Keyboard Controller The system uses the NS 87591 as the keyboard controller and ACPI embedded controller. Following will summarize all

the features of keyboard firmware.

l External Keyboard and Auxiliary Device Support Standard AT or OADG Support

l IBM PS/44 Numeric Keypad Support and PS/2 Style Auxiliary Device Support.

l Internal Keyboard and Auxiliary Device Support and Internal Pointing Device Support.

l Internal Keyboard Scan Code Controller Support and Internal Numeric Keypad Support.

l Simultaneous Operation of Internal and External Devices

l Simultaneous Operation of internal and External Keyboards

l Simultaneous Operation of Internal and External Auxiliary

l Device Hot Pluggability

l Hot Pluggability of External PS/2 Devices (Keyboard or Mouse) and Hot Port Swapping

l Embedded Controller PC87591E 176-Pin LQFP package (share BIOS )

l LPC System Interface

l ACPI Embedded Controller Power Management Event Control.

l Internal 8 x 16 Keys Matrix Scanning.

l Single Pin Keys Support .

l PS/2 Interface External 2 Ports Support and one internal PS/2 Touch-PAD support.

l On-Board Keyboard LEDs NumLock,CapsLock, ScrollLock Support.

l System Power On/Off ATX Power Sequence Control.

l System BIOS ROM Flash Protect.

l FAN DAC or PWM Control.

l Battery Low/Very Low Beep Control

l LID Function Support.

l Function Hotkey and Quick Keys Support.

l LCD Backlight Brightness Adjust.

l System SmartBattery Li-Ion Charger Control.

l Direct LEDs Support.

G. Power Management Mode Definitions

PM Mode Definitions


1-35

Full-On The CPU run in full speed and all the devices are power on. The system can respond to all applications with maximum performance.

1. The system in the state S0.

2. The CPU in the state C0.

3. All the devices in the state D0. Idle This mode is similar to Full-On except the CPU will change to C1 or C2 state depend on the OS, to

save CPU power consumption.


2. The CPU in the state C1 or C2.

3. All the devices in the state D0. Suspend The state is more power saving than above, the CPU will change to C3 state and most of power

consumption parts will enter to suspend or idle mode.


2. The CPU in the state C3.

3. HDD, CDROM and LCD enter to suspend mode, otherwise in state D0. SOFF/STD The state is the most power saving mode, all of the parts in the system will power off, except the

keyboard controller enter to idle mode continuously to control the battery charging and monitor power button. Note: Before enter to S4, the OS or BIOS will save all of data or registers in the parts.

1. The system in the state S5 or S4.

2. The CPU and all of devices power off.

When system in suspend mode (S3 state ), external keyboard/mouse and touch pad can’t be the wake up event source.

H. The backlight control of LCD

The LCD panel is another key parts that will consume more power of the notebook system, so there

is a way to reduce the power consumption on battery only, e.i. reduce the brightness of backlight

when end-user plug out the AC adaptor.

The backlight is controled through the KBC controller, and it is divide into 5 levels from

darkest to brightest. The KBC bios know the status of power source and the current backlight’s

brightness any time. When the AC adaptor plug out, the KBC will reduce the brightness one or two

level automatically.

There is another approach to control the backlight, it will be turn off when LCD cover

close(LID switch), conversly, it will be turn on when LCD cover open


1-36

2.1. System Block Diagram …………………………………………………... 3 2.2. Major Component Definition.……..……………………………….…… 4 2.3. Connector Definition…….……………………………………………….. 35


2-2

2.1 System Block Diagram

RJ11 Con.

LAN

IDE

Pentium M Processor

PCMCIA

USB_Port X 4

LPC I/F

MCH

( Primary )

PCI 33 MHz

ITE : IT8510E Touch Pad

Page 14Page 8,9

Page 11,12,13

IEEE 1394

IDE

Hub Interface 66MHz

OZ 711MC1TI:TSB43AB22

ATI M11P

VIA : VT1612A

AC97

MINI PCI

DDR SO-DIMM

EC

MDC

P age 3 , 4

MINI PCIAudio Codec

593 uFCBGA

Page 5 , 6 , 7

RTL8100CL

CD-ROM

PSB

LED

1.5V AGP 66MHz

BIOS

ICH4M

Intel 855PM

478 uFCPGA

( Secondary )

HDD

Amplifier

CPU Pentium M (U2A)


2-3

PSI#

CLK_CPU_BCLK

IERR#

H_TMS

H_TEST1

COMP3

H_TDO

TP_NC_1

COMP0

H_THERMDC

H_BPM5_PREQ#

TP_NC_3

COMP1

CLK_CPU_BCLK#

TZ0301

GTL_REF0

H_BPM1_ITP#

CLK_ITP_CLK

PM_THRMTRIP#

H_CPURST#

H_BPM0_ITP#

CLK_ITP_CLK#

H_TRST#

TP_GTLREF3

H_PWRGD

Centrino CPUPentium M 1/3

MIS

CC

ON

TRO

LA

DD

R G

RO

UP

ITP

SIG

NA

LSTH

ERM

H C

LKD

ATA

GR

OU

P

Lega

cy

U2A

MOLEX_500210-4782Pentium-M

P4U4V3R3V2

W1T4

W2Y4Y1U1

AA3Y3

AA2AF4AC4AC7AC3AD3AE4AD2AB4AC6AD5AE2AD6AF3AE1AF1

U3AE5

R2P3T2P1T1

A19A25A22B21A24B26A21B20C20B24D24E24C26B23E23C25H23G25L23M26H24F25G24J23M23J25L26N24M25H26N25K25Y 26

AA24T25U23V23R24R26R23

AA23U26V24U25V26Y 23

AA26Y 25

AB25AC23AB24AC20AC22AC25AD23AE22AF23AD24AF20AE21AD21AF25AF22AF26

C2D3A3

C6D1D4B4

N2L1J3

L4H2M2

N4

A4B5

J2

B11H1K1L2M3

K3K4

C8B8A9C9

A10B10

A13C12A12C11B13A7

B17B18A18

C17

P25P26AB2AB1

B7C19E4A6

C5F23

AD26

AC1G1E26

C23C22K24L24W25W24AE24AE25

D25J26T24AD20

A1B2

C14C3AF7C16E1

A15A16B14B15

A3#A4#A5#A6#A7#A8#A9#A10#A11#A12#A13#A14#A15#A16#A17#A18#A19#A20#A21#A22#A23#A24#A25#A26#A27#A28#A29#A30#A31#

ADSTB#0ADSTB#1

REQ0#REQ1#REQ2#REQ3#REQ4#

D0#D1#D2#D3#D4#D5#D6#D7#D8#D9#D10#D11#D12#D13#D14#D15#D16#D17#D18#D19#D20#D21#D22#D23#D24#D25#D26#D27#D28#D29#D30#D31#D32#D33#D34#D35#D36#D37#D38#D39#D40#D41#D42#D43#D44#D45#D46#D47#D48#D49#D50#D51#D52#D53#D54#D55#D56#D57#D58#D59#D60#D61#D62#D63#

A20M#FERR#

IGNNE#

STPCLK#LINT0LINT1SMI#

ADS#BNR#BPRI#

DEFER#DRDY#DBSY#

BR0#

IERR#INIT#

LOCK#

RESET#RS0#RS1#RS2#

TRDY#

HIT#HITM#

BPM#0BPM#1BPM#2BPM#3

PRDY#PREQ#

TCKTDI

TDOTMS

TRST#DBR#

PROCHOT#THERMDATHERMDC

THERMTRIP#

COMP0COMP1COMP2COMP3

DPSLP#DPWR#

PWRGOODSLP#

TEST1TEST2

GTLREF0

GTLREF3GTLREF2GTLREF1

DSTBN0#DSTBP0#DSTBN1#DSTBP1#DSTBN2#DSTBP2#DSTBN3#DSTBP3#

DINV0#DINV1#DINV2#DINV3#

NC0NC1

RSVD1RSVD2RSVD3RSVD4RSVD5

ITP_CLK1ITP_CLK0

BCLK1BCLK0

COMP2

TP_GTLREF2

H_BPM4_PRDY#

TP_NC_2

TP_NC_4

H_TDI

H_BPM3_ITP#

H_TEST2

ITP_DBRESET#

H_PROCHOT_S#

TP_GTLREF1

H_DPSLP#

H_TCK

H_BPM2_ITP#

H_THERMDA

CPU Pentium M (U2B)


2-4

+VCC_CORE

H_VID2 23,34

POW

ERPentium

M 2/3

U2B


AA11AA13AA15AA17AA19AA21AA5AA7AA9

AB10AB12AB14AB16AB18AB20AB22AB6AB8

AC11AC13AC15AC17AC19AC9

AD10AD12AD14AD16AD18AD8

AE11AE13AE15AE17AE19AE9

AF10AF12AF14AF16AF18AF8D18D20D22D6D8

E17E19E21E5E7E9

F18F20F22F6F8

G21

G5H22H6J21J5K22U5V22V6W21W5Y22Y6

F26B1N1AC26

D10D12D14D16E11E13E15F10F12F14F16K6L21L5M22M6N21N5P22P6R21R5T22T6U21

P23W4

E2F2F3G3G4H4

AE7AF6

VCC0VCC1VCC2VCC3VCC4VCC5VCC6VCC7VCC8VCC9VCC10VCC11VCC12VCC13VCC14VCC15VCC16VCC17VCC18VCC19VCC20VCC21VCC22VCC23VCC24VCC25VCC26VCC27VCC28VCC29VCC30VCC31VCC32VCC33VCC34VCC35VCC36VCC37VCC38VCC39VCC40VCC41VCC42VCC43VCC44VCC45VCC46VCC47VCC48VCC49VCC50VCC51VCC52VCC53VCC54VCC55VCC56VCC57VCC58

VCC59VCC60VCC61VCC62VCC63VCC64VCC65VCC66VCC67VCC68VCC69VCC70VCC71

VCCA0VCCA1VCCA2VCCA3

VCCP0VCCP1VCCP2VCCP3VCCP4VCCP5VCCP6VCCP7VCCP8VCCP9

VCCP10VCCP11VCCP12VCCP13VCCP14VCCP15VCCP16VCCP17VCCP18VCCP19VCCP20VCCP21VCCP22VCCP23VCCP24

VCCQ0VCCQ1

VID0VID1VID2VID3VID4VID5

VCCSENSEVSSSENSE

H_VID3 23,34

H_VID5 23,34

VSSSENSE 37

+VCC_CORE

+VCCP

H_VID0 23,34

VCCSENSE 37

+V1.8S_PROC

H_VID4 23,34

H_VID1 23,34

CPU Pentium M (U2C)


2-5

VSSPentium

M 3/3

U2C


A2A5A8

A11A14A17A20A23A26AA1AA4AA6AA8

AA10AA12AA14AA16AA18AA20AA22AA25

AB3AB5AB7AB9

AB11AB13AB15AB17AB19AB21AB23AB26AC2AC5AC8

AC10AC12AC14AC16AC18AC21AC24

AD1AD4AD7AD9

AD11AD13AD15AD17AD19AD22AD25

AE3AE6AE8

AE10AE12AE14AE16AE18AE20AE23AE26

AF2AF5AF9

AF11AF13AF15AF17AF19AF21AF24

B3B6B9

B12B16B19B22B25C1C4C7

C10C13C15C18C21C24

D2D5D7D9

D11

D13D15D17D19D21D23D26E3E6E8E10E12E14E16E18E20E22E25F1F4F5F7F9F11F13F15F17F19F21F24G2G6G22G23G26H3H5H21H25J1J4J6J22J24K2K5K21K23K26L3L6L22L25M1M4M5M21M24N3N6N22N23N26P2P5P21P24R1R4R6R22R25T3T5T21T23T26U2U6U22U24V1V4V5V21V25W3W6W22W23W26Y2Y5Y21Y24

VSS0VSS1VSS2VSS3VSS4VSS5VSS6VSS7VSS8VSS9VSS10VSS11VSS12VSS13VSS14VSS15VSS16VSS17VSS18VSS19VSS20VSS21VSS22VSS23VSS24VSS25VSS26VSS27VSS28VSS29VSS30VSS31VSS32VSS33VSS34VSS35VSS36VSS37VSS38VSS39VSS40VSS41VSS42VSS43VSS44VSS45VSS46VSS47VSS48VSS49VSS50VSS51VSS52VSS53VSS54VSS55VSS56VSS57VSS58VSS59VSS60VSS61VSS62VSS63VSS64VSS65VSS66VSS67VSS68VSS69VSS70VSS71VSS72VSS73VSS74VSS75VSS76VSS77VSS78VSS79VSS80VSS81VSS82VSS83VSS84VSS85VSS86VSS87VSS88VSS89VSS90VSS91VSS92VSS93VSS94VSS95VSS96

VSS97VSS98VSS99

VSS100VSS101VSS102VSS103VSS104VSS105VSS106VSS107VSS108VSS109VSS110VSS111VSS112VSS113VSS114VSS115VSS116VSS117VSS118VSS119VSS120VSS121VSS122VSS123VSS124VSS125VSS126VSS127VSS128VSS129VSS130VSS131VSS132VSS133VSS134VSS135VSS136VSS137VSS138VSS139VSS140VSS141VSS142VSS143VSS144VSS145VSS146VSS147VSS148VSS149VSS150VSS151VSS152VSS153VSS154VSS155VSS156VSS157VSS158VSS159VSS160VSS161VSS162VSS163VSS164VSS165VSS166VSS167VSS168VSS169VSS170VSS171VSS172VSS173VSS174VSS175VSS176VSS177VSS178VSS179VSS180VSS181VSS182VSS183VSS184VSS185VSS186VSS187VSS188VSS189VSS190VSS191

855PM (U3A)


2-6

H_D#18

H_D#54

H_D#58

H_D#40

H_D#46

H_D#29

H_D#33

H_D#26

H_D#16

H_D#53

H_D#6

H_D#2

H_D#39

H_D#60

H_D#7

H_D#25

H_D#0

H_D#5

H_D#17

H_D#20

H_D#12

H_D#52

H_D#19

H_D#1

H_D#4

H_D#22

H_D#24

H_D#32

H_D#21

Intel 855PM 1/3

HOSTH

UB I

/F

U3A

855PM SL752

U6T5R2U3R3P7T3P4P3P5R6N2N5N3J3M3M4M5L5K3J2N6L6L2K5L3L7K4J5

U2T7R7U5T4

R5N7

K8J8

AC13AD13AC2AA7

AD4AF6

AD11AC15AD3AG6

AE11AC16AD5AG5AH9

AD15

AE17

M7P8

AA9AB12AB16

P25P24N27P23M26M25L28L27M27N28M24

N25N24P27P26

AA2AB5AA5AB3AB4AC5AA3AA6AE3AB7AE5AF3AC6AC3AF4AE2AG4AG2AE7AE8AH2AC7AG3AD7AH7AE6AC8AG8AG7AH3AF8AH5AC11AC12AE9AC10AE10AD9AG9AC9AE12AF10AG11AG10AH11AG12AE13AF12AG13AH13AC14AF14AG14AE14AG15AG16AG17AH15AC17AF16AE15AH17AD17AE16

U7V4W2Y4Y3Y5W3V7V3Y7V5W7W5W6

HA#3HA#4HA#5HA#6HA#7HA#8HA#9HA#10HA#11HA#12HA#13HA#14HA#15HA#16HA#17HA#18HA#19HA#20HA#21HA#22HA#23HA#24HA#25HA#26HA#27HA#28HA#29HA#30HA#31

HREQ#0HREQ#1HREQ#2HREQ#3HREQ#4

HADSTB#0HADSTB#1

BCLK#BCLKHRCOMP1HSWNG1HRCOMP0HSWNG0

HDSTBN#0HDSTBN#1HDSTBN#2HDSTBN#3HDSTBP#0HDSTBP#1HDSTBP#2HDSTBP#3DBI#0DBI#1DBI#2DBI#3

CPURST#

HVREF0HVREF1HVREF2HVREF3HVREF4

HI_0HI_1HI_2HI_3HI_4HI_5HI_6HI_7HI_8HI_9HI_10

HI_STBHI_STB#HLRCOMPHI_REF

HD#0HD#1HD#2HD#3HD#4HD#5HD#6HD#7HD#8HD#9

HD#10HD#11HD#12HD#13HD#14HD#15HD#16HD#17HD#18HD#19HD#20HD#21HD#22HD#23HD#24HD#25HD#26HD#27HD#28HD#29HD#30HD#31HD#32HD#33HD#34HD#35HD#36HD#37HD#38HD#39HD#40HD#41HD#42HD#43HD#44HD#45HD#46HD#47HD#48HD#49HD#50HD#51HD#52HD#53HD#54HD#55HD#56HD#57HD#58HD#59HD#60HD#61HD#62HD#63

ADS#HTRDY#DRDY#

DEFER#HITM#

HIT#HLOCK#

BR0#BNR#BPRI#

DBSY#RS#0RS#1RS#2

H_D#38

H_D#62

H_D#15

H_D#30H_D#31

H_D#9H_D#8

H_D#57

H_D#3

H_D#37

H_D#34

H_D#44

H_D#49

H_D#28

H_D#10

H_D#43

H_D#48

H_D#63

H_D#14

H_D#36

H_D#56

H_D#13

H_D#51

H_D#61

H_D#42

H_D#47

H_D#59

H_D#11

H_D#27

H_D#45

H_D#50

H_D#55

H_D#23

H_D#41

H_D#35

SIS 962 POWER (U3B)


2-7

DDR

DDR

Intel 855PM 2/3

AGP

U3B

855PM SL752

E12F17E16G17G18E18F19G20G19F21F13E20G21G22

G28F27C28E28H25G27F25B28E27C27B25C25B27D27D26E25D24E23C22E21C24B23D22B21C21D20C19D18C20E19C18E17E13C12B11C10B13C13C11D10E10C9D8E8

E11B9B7C7C6D6D4B3E6B5C4E4C3D3F4F3B2C2E2G4

C16D16B15C14B17C17C15D14

F26C26C23B19D12

C8C5E3

E15

G11G8

F11

J27H27H26

R27R28T25R25T26T27U27U28V26V27T23U23T24U24U25V24Y27Y26AA28AB25AB27AA27AB26Y23AB23AA24AA25AB24AC25AC24AC22

V25V23Y25AA23

Y24W28W27W24W23W25AG24AH25AD25AA21P22

R24R23AC27AC28

AH28AH27AG28AG27AE28AE27AE24AE25AF27AF26

AE22AE23AF22AG25AF24AG26

J23

G7

J24

E24

F5

K25

J21J9

G23E22H23F23

G12G13E9F7F9E7

J28G15G14

AD26AD27

V8Y8

K23

G6

G25

G24

G5

J25

AD24

SMA0SMA1SMA2SMA3SMA4SMA5SMA6SMA7SMA8SMA9SMA10SMA11SMA12RSVD2

SDQ0SDQ1SDQ2SDQ3SDQ4SDQ5SDQ6SDQ7SDQ8SDQ9SDQ10SDQ11SDQ12SDQ13SDQ14SDQ15SDQ16SDQ17SDQ18SDQ19SDQ20SDQ21SDQ22SDQ23SDQ24SDQ25SDQ26SDQ27SDQ28SDQ29SDQ30SDQ31SDQ32SDQ33SDQ34SDQ35SDQ36SDQ37SDQ38SDQ39SDQ40SDQ41SDQ42SDQ43SDQ44SDQ45SDQ46SDQ47SDQ48SDQ49SDQ50SDQ51SDQ52SDQ53SDQ54SDQ55SDQ56SDQ57SDQ58SDQ59SDQ60SDQ61SDQ62SDQ63SDQ64SDQ65SDQ66SDQ67SDQ68SDQ69SDQ70SDQ71

SDQS0SDQS1SDQS2SDQS3SDQS4SDQS5SDQS6SDQS7SDQS8

SWE#SCAS#SRAS#

RSTIN#RSVD1TESTIN#

GAD0GAD1GAD2GAD3GAD4GAD5GAD6GAD7GAD8GAD9

GAD10GAD11GAD12GAD13GAD14GAD15GAD16GAD17GAD18GAD19GAD20GAD21GAD22GAD23GAD24GAD25GAD26GAD27GAD28GAD29GAD30

GCBE#0GCBE#1GCBE#2GCBE#3

GFRAME#GDEVSEL#

GIRDY#GTRDY#GSTOP#

GPARGREQ#GGNT#

GRCOMPAGPREF

66IN

AD_STB0AD_STB#0AD_STB1

AD_ATB#1

SBA0SBA1SBA2SBA3SBA4SBA5SBA6SBA7

SB_STBSB_STB#

RBF#WBF#PIPE#

ST0ST1ST2

SCK#5

SCK#4

SCK#3

SCK#2

SCK#1

SCK#0

SMVREF1SMVREF0

SCKE0SCKE1SCKE2SCKE3

SBS0SBS1

SCS#0SCS#1SCS#2SCS#3

SMRCOMPRCVENIN#

RCVENOUT#

NC0NC1

DPSLP#DPWR#

SCK5

SCK4

SCK3

SCK2

SCK1

SCK0

GAD31

M_DQS2

M_D27

AGP_AD26

AGP_AD2

M_D13

M_A8

M_CB0

AGP_AD25

M_D62

M_DQS8

M_D61

M_D17

M_D24

M_D3

M_D36

AGP_AD29

M_D31

M_D42

TP_M_NC_1

AGP_AD4

M_D57

AGP_AD14

M_D10

M_D35

AGP_AD18

M_CB3

M_D56

M_RCOMP

AGP_AD13

M_DQS5

M_D45

AGP_AD15

AGP_AD20

AGP_AD3

M_D11

M_D25

M_D44

TP_M_NC_0

AGP_AD8

M_A2

AGP_AD31

AGP_AD1

M_D33

AGP_AD19

M_D16

M_A7

AGP_AD16

M_CB6

M_D1

M_D37

AGP_AD21

M_D9

M_D40

M_D20

M_DQS1

AGP_AD28

M_D43

M_D14

M_CB1

M_D50

M_A0

AGP_AD22

M_A1

M_D63

M_A12

M_D2

M_D6

AGP_AD5

AGP_AD30

M_D49

AGP_AD11

M_D15

M_D38

M_D60

M_A5

AGP_AD23

M_D28

AGP_AD12

M_CB4

M_D21

M_D53

M_D4

M_CB2

M_D58

AGP_AD17

M_D48

M_D23

M_D39

M_D54

M_D29

M_D59

AGP_AD27

AGP_AD24

M_DQS6

M_D47

M_A4

M_D19

M_A10M_A11

M_CB7

AGP_AD10

M_D34

M_D8

M_D22

M_A3

M_CB5

M_D46

M_D52

AGP_AD6

M_D12

M_A6

M_DQS3

M_D51

M_D7

M_DQS0

AGP_AD0

AGP_AD7

M_A9

M_DQS4

M_D55

M_D0

M_D5

M_D30

M_D18

M_DQS7

AGP_AD9

MCH_TEST#M_RCV#

M_D32

SM_VREF_MCH

M_D26

M_D41

855PM (U3C)


2-8

MCH_ETS#

+V1.8S_MCH

MCH_RSVD8

+V1.2S_MCH

+VCCP

MCH_ETS# 33MCH_RSVD7

MCH_RSVD4

+V1.8S_MCH

MCH_RSVD6

MCH_RSVD3

MCH_RSVD9

Intel 855PM 3/3

Ground Power

The AGTL bus terminationvoltage(1.05V)

DDR (2.5V)

AGP I/O (1.5V) 1.2V

1.8V

PLL power(1.8V)

U3C

855PM SL752

A11A15A19A23A27A3A7

AA1AA29AA4AA8

AB11AB13AB15AB17AB19AB22

AC1AC18AC20

AB6AB9

AD14AD16

AG20AG22

D19D23D25

F16

A9C1

D7E5F10F14

F22F18

C29D11D15

AF18AF20AG19AG21

A17A21

AJ23

T8

A25A5

M8

A13

AC21AC23AC26AC4

AD10AD12

AD19AD22AD6AD8AE1

AE18AE20AE29AE4

AF11AF13

AF17AF19AF21AF25AF5AF7AF9AG1

AG18

AH19AH21AH23AJ11AJ13AJ15AJ17AJ27AJ3AJ5AJ7AJ9D13D17D21D5D9E1

E14E26E29F12F15F20F24F6F8

G26H11H13H15H17H19H21H6H9J1

J22J26J29J4J7

R22

R29

AG23AJ19AJ21

AA

22A

A26

U22

U26

W22

W29

H7H4H3G3G2

T17T13

AB10AB14AB18AB20AB8AC19AD18

AB

21A

C29

AD

21A

D23

AE

26A

F23

AG

29A

J25

N14N16P13P15P17R14R16T15U14U16

L25L29M22N23N26

G10G16

G9

AD20AE19AE21

K27

K6

L1 L22

L24

L26

L4 L8 M23

M6

N1

N13

N15

N17

N22

N29

N4

N8

P14

P16

P6

R1

R13

R15

R17

R26

R4

R8

T14

T16

T22

T6

U1

U13

U15

U29

U4

U8

V22

V6

W1

W26

W4

W8

Y22

Y6

G1G29H10H12H14H16H18H20H22H24H5H8J6K22K24K26K7L23

AF15

U17

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGND

GNDGND

GNDGND

GNDGND

VCCSMVCCSMVCCSM

VCCSM

VCCSMVCCSM

VCCSMVCCSMVCCSMVCCSM

VCCSMVCCSM

VCCSMVCCSMVCCSM

VTTVTTVTTVTT

VCCSMVCCSM

VTT

VTT

VCCSMVCCSM

VTT

VCCSM

GNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGND

GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND

VC

CA

GP

VC

CA

GP

VTTVTTVTT

VC

CA

GP

VC

CA

GP

VC

CA

GP

VC

CA

GP

VC

CA

GP

VC

CA

GP

RSVD6ETS#

RSVD7RSVD8RSVD9

VCCGAVCCHA

VTTVTTVTTVTTVTTVTTVTT

VC

CA

GP

VC

CA

GP

VC

CA

GP

VC

CA

GP

VC

CA

GP

VC

CA

GP

VC

CA

GP

VC

CA

GP

VCCVCCVCCVCCVCCVCCVCCVCCVCCVCC

VCCHLVCCHLVCCHLVCCHLVCCHL

RSVD4RSVD3

RSVD5

VTTVTTVTT

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

DG

ND

GN

D

VCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSMVCCSM

GND

GN

D

MCH_RSVD5

Clock Generator


2-9

66BUF166BUF2

CPU0

Z1001

CPU2#

66BUF0

MULT0 = 0 -> Ioh = 20mA/1.0V [IREF(5.0mA / 221R) X 4)] = 1 -> Ioh = 14mA/0.7V [IREF(2.32mA / 475R) X 6]

CPU1CPU1#

CPU0#

TZ1004

TZ1003TZ1002

TZ1001

CPU2

* : 120K PU.** : PD.

U12

ICS950813BG

1

46

814193237

50

5455

40

25

345328

43

29

4

30

33

41

35

42

91520 31

3647

2627

4544

11

51

4948

52

24232221

765

18

1312

1617

10

3938

56

2

3

VDDREF

VDDCPU

VDDPCIVDDPCIVDD3V66VDD3V66VDD48

VDDCPU

FS0FS1

PWRSAVE#*

*PD#

PCI_STOP#CPU_STOP#Vtt_PWRGD#

MULTSEL*

SDATA

GND

SCLK

3V66_0/FS4**

GND

3V66_1/VCH-CLK/FS3**

IREF

GNDGNDGND GND

GNDGND

VDDAGND

CPUCLKT2CPUCLK2

**E_PCICLK1/PCICLK1

CPUCLKC0

CPUCLKT1CPUCLKC1

CPUCLKT0

3V66_53V66_43V66_33V66_2

*ASEL/PCICLK_F2PCICLK_F1PCICLK_F0

PCICLK6

**E_PCICLK3/PCICLK3PCICLK2

PCICLK4PCICLK5

PCICLK0

48Mhz_USB/FS2**48MhZ_DOT

REF

X1

X2

CLK_REF0

PCIF2

ICH4-M (U16A)


2-10

ICH4-M 1/3

PCII/F

Sys

tem

Man

agem

ent

I/F

Hub I/F

Inte

rrup

t I/F

LAN

I/F

CPU I/F

EEP

RO

MI/F

U16A

ICH4-M

H5J3H3K1G5J4H4J5K2G2L1G4L2H2L3F5F4N1E5N2E3N3E4M5E2P1E1P2D3R1D2P4

J2K4M4N4

C1E6A7B7D6

B1A2B3C7B6

P5M3F1B5A6E8C5L5G1L4M2W2U5K5F3F2

Y22AB23

AA21W21V22AB22V21Y23U22U21W23V23

W6AC3AB1AC4AB4AA5

U23

D5C2B4A3

P21N20

T21

M23R23

R22

J22

L19L20M19M21P19R19T20R20P23L22N22K21

J19H19K20

AC13C4C3D7C8

AA19

B10C10A12

A10A9A11

C11B11Y5

D10

C12

D11A8

PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10PCI_AD11PCI_AD12PCI_AD13PCI_AD14PCI_AD15PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27PCI_AD28PCI_AD29PCI_AD30PCI_AD31

PCI_CBE0#PCI_CBE1#PCI_CBE2#PCI_CBE3#

PCI_GNT0#PCI_GNT1#PCI_GNT2#PCI_GNT3#PCI_GNT4#

PCI_REQ0#PCI_REQ1#PCI_REQ2#PCI_REQ3#PCI_REQ4#

PCI_CLKPCI_DEVSEL#PCI_FRAME#PCI_REQA#/GPIO0PCI_REQB#/REQ5#/GPIO1PCI_GNTA#/GPIO16PCI_GNTB#/GNT5#/GPIO17PCI_IRDY#PCI_PARPCI_PERR#PCI_LOCK#PCI_PME#PCI_RST#PCI_SERR#PCI_STOP#PCI_TRDY#

CPU_A20GATECPU_A20M#

CPU_FERR#CPU_IGNNE#

CPU_INIT#CPU_INTRCPU_NMI

CPU_PWRGDCPU_RCIN#

CPU_SLP#CPU_SMI#

CPU_STPCLK#

SM_INTRUDER#SM_LINK0SM_LINK1SMB_CLK

SMB_DATASMB_ALERT#/GPIO11

CPU_DPSLP#

INT_PIRQA#INT_PIRQB#INT_PIRQC#INT_PIRQD#

HUB_STB/HUB_STBSHUB_STB#/HUB_STBF

HUB_CLK

HUB_VREFHUB_COMP

HUB_VSWING

INT_SERIRQ

HUB_PD0HUB_PD1HUB_PD2HUB_PD3HUB_PD4HUB_PD5HUB_PD6HUB_PD7HUB_PD8HUB_PD9

HUB_PD10HUB_PD11

INT_APICCLKINT_APICD0INT_APICD1

INT_IRQ14INT_PIRQH#/GPIO5INT_PIRQG#/GPIO4INT_PIRQF#/GPIO3INT_PIRQE#/GPIO2

INT_IRQ15

LAN_TXD0LAN_TXD1LAN_TXD2

LAN_RXD0LAN_RXD1LAN_RXD2

LAN_CLKLAN_RSTSYNC

LAN_RST#

EEP_CS

EEP_SHCLK

EEP_DINEEP_DOUT

+V3.3

ICH4-M (U16B)


2-11

TZ1203

LPC_AD2

TZ1202

LPC_AD1

TZ1201

LPC_AD0

PM_THRM#_ICH

USB_RBIAS

PM_THRMTRIP#_D

ACSYNC_D

ICH4-M 2/3

Pow

er Managem

entAC ' 97I/F

USB I/F

IDE I/F

GPIO

MIS

C

IST

LPCI/F

Clock

Unm

uxed

U16B

ICH4-M

Y13AB14AB21AC22

AA13AB13W13AA20AC20AC21

AB11AC11Y10AA10AA7AB8Y8AA8AB9Y9AC9W9AB10W10W11Y11

W17AB17W16AC16W15AB15W14AA14Y14AC15AA15Y15AB16Y16AA17Y17

Y12

AC12

W12

H23

C20A21C18A19C16A17D20B21D18B19D16B17

B15C14A15B14A14D14

A23B23

F21H20F23H22G23H21F22E23

B8C13D13A13B13D9C9

AB19

AB18

Y18

AA18

AC19

V2W1W4

J20G22F20G20

R3V4V5W3

AB12

AA11

W7AC7AC6Y6

U4U3

T5

U2T4R4T2

V19Y20J21

Y3

W20

V1AB3AA4Y21W19AA2Y2Y4

W18AA6Y1

AB6AA1V20

T3AB2

R2

AC2

J23F19

IDE_PDCS1#IDE_PDCS3#IDE_SDCS1#IDE_SDCS3#

IDE_PDA0IDE_PDA1IDE_PDA2IDE_SDA0IDE_SDA1IDE_SDA2

IDE_PDD0IDE_PDD1IDE_PDD2IDE_PDD3IDE_PDD4IDE_PDD5IDE_PDD6IDE_PDD7IDE_PDD8IDE_PDD9

IDE_PDD10IDE_PDD11IDE_PDD12IDE_PDD13IDE_PDD14IDE_PDD15

IDE_SDD0IDE_SDD1IDE_SDD2IDE_SDD3IDE_SDD4IDE_SDD5IDE_SDD6IDE_SDD7IDE_SDD8IDE_SDD9

IDE_SDD10IDE_SDD11IDE_SDD12IDE_SDD13IDE_SDD14IDE_SDD15

IDE_PDDACK#

IDE_PDIOR#

IDE_PDIOW#

SPKR

USB_PP0USB_PP1USB_PP2USB_PP3USB_PP4USB_PP5USB_PN0#USB_PN1#USB_PN2#USB_PN3#USB_PN4#USB_PN5#

USB_OC0#USB_OC1#USB_OC2#USB_OC3#USB_OC4#USB_OC5#

USB_RBIASUSB_RBIAS#

GPIO36GPIO37GPIO38GPIO39GPIO40GPIO41GPIO42GPIO43

AC_BITCLKAC_RST#AC_SDATAIN0AC_SDATAIN1AC_SDATAIN2AC_SDATAOUTAC_SYNC

IDE_SDDACK#

IDE_SDDREQ

IDE_SDIOR#

IDE_SDIOW#

IDE_SIORDY

GPIO25GPIO27GPIO28

GPIO32GPIO33GPIO34GPIO35

GPIO7GPIO8

GPIO12GPIO13

IDE_PIORDY

IDE_PDDREQ

RTC_RST#RTC_X1RTC_X2

RTC_VBIAS

LPC_DRQ1#LPC_DRQ0#

LPC_FRAME#/FWH4

LPC_AD3/FWH3LPC_AD2/FWH2LPC_AD1/FWH1LPC_AD0/FWH0

PM_VGATE/VRMPWRGDPM_CPUPERF#PM_SSMUXSEL

PM_SYS_RST#

PM_THRMTRIP#

PM_THRM#PM_SUS_STAT#/LPCPD#PM_SUS_CLKPM_STP_PCI#PM_STP_CPU#PM_SLP_S5#PM_SLP_S4#PM_SLP_S3#PM_SLP_S1#PM_RSMRST#PM_RI#PM_PWROKPM_PWRBTN#PM_DPRSLPVR

PM_C3_STAT#PM_BATLOW#

PM_AGPBUSY#

PCI_CLKRUN#

ICH4_CLK_14MUSB_CLK_48M

TZ1205TZ1204

LPC_AD3

ICH4-M (U16C)


2-12

+V1.5S_ICH

+V5A_ICH

+V3.3S_ICH

+V3.3_ICHLAN

C202

0.1U

21

Z1301

VCCPLL

ICH4-M 3/3

PO

WE

R &

VS

S

U16C

ICH4-M

P14U18AA23

E7

E15

V6

K10K12K18K22P10T18U19V14

A5B2H6H18J1J18K6M10P6P12U1V10V16V18AC8AC17

L23M14P18T22

C22

E12E13E20

G18R6T6U6

F6F7

F14

E9F9

E11F10F15F16F17F18K14V7V8V9

A1A4

A16A18A20A22B9

B12B16B18B20B22C6

C15C17C19C21C23

D1D4D8

D12D15D17D19D21D22D23E10E14E16E17E18E19E21E22F8G3G6

G19G21

H1J6K3

K11K13K19K23L10L11L12L13L14L21M1

M11M12M13M20M22

N5N10N11N12N13N14N19N21N23

P3P11P13P20P22R5

R18R21

T1T19T23

Y7Y19AA3AA9AA12AA16AA22AB7AB20AC1AC5AC10AC14AC18AC23

U20V3

W8

W22

V15V17W5

AB5

V_CPU_IOV_CPU_IOV_CPU_IO

V5REF

V5REF_SUS

V5REF

VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5VCC1_5

VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3VCC3_3

VCC_HUBVCC_HUBVCC_HUBVCC_HUB

VCC_PLL

VCCSUS1_5VCCSUS1_5VCCSUS1_5

VCCSUS1_5VCCSUS1_5VCCSUS1_5VCCSUS1_5

VCCLAN1_5VCCLAN1_5

VCCSUS1_5

VCCLAN3_3VCCLAN3_3

VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3VCCSUS3_3

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSS

VSS

VSS

VSSVSSVSS

RTC_VCC +V_RTC

+V1.5_ICHLAN

+V3.3_AUX_ICH

+V1.8S_ICHHUB

+V1.5A_ICH

VCC5REF

MOBILITY M11-P_A (U8A)


2-13

MEM_ID0

GPIO9

ZV_LCDDATA20

TZ1433

GPIO5

GPIO2

TZ1432

DVO

/ EX

T TM

DS

/ GPI

OLV

DS

TMDS

DAC

1

PCI /

AG

PA

GP2

X4X

DAC

2SS

CLK

Part 1 of 7

8X

AG

P

MA

N

PWR

THER

M

U8A

M11-P_A15-FSC

H29H28J29J28K29K28L29L28N28P29P28R29R28T29T28U29N25R26P25R27R25T25T26U25V27

W26W25Y26Y25

AA26AA25AA27

N29U28P26U26

AG30AG28AF28AD26

M25N26V29V28

W29W28

AE26

AC26

AH30AH29

AE29M28V25

AB29

AD28AD29AC28AC29AA28AA29Y28Y29

AF29AD27AE28

AB28M29V26

M26M27

AK21

AJ23AJ22AK22

AJ24AK24

AG23AG24

AK25

AJ25

AH28

AJ29

AH27

AG26

AJ5AH5AJ4AK4AH4AF4AJ3AK3AH3AJ2AH2AH1AG3AG1AG2AF3AF2

AH6AJ6AK6AH7AK7AJ7AH8AJ8AH9AJ9AK9AH10AE6AG6AF6AE7AF7AE8AG8AF8AE9AF9AG10AF10

AJ10AK10AJ11AH11

AK16AH16AH17AJ16AH18AJ17AK19AH19AK18AJ18AG16AF16AG17AF17AF18AE18AH20AG20AF19AG19

AE12AG12

AJ13AH14AJ14AH15AJ15AK15AH13AK13

AE13AE14

AF12

AK27AJ27AJ26

AG25AH25

AH26

AF25AF24

AF26

AE10

AB25AB26

E8

AG4

B6

AG29

AC25

AE25

AF11AE11

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31

C/BE#0C/BE#1C/BE#2C/BE#3

PCICLKRST#REQ#GNT#PARSTOP#DEVSEL#TRDY#IRDY#FRAME#INTA#

WBF#

STP_AGP#AGP_BUSY#

RBF#AD_STBF_0AD_STBF_1SB_STBF

SBA0SBA1SBA2SBA3SBA4SBA5SBA6SBA7

ST0ST1ST2

SB_STBSADSTBS_0ADSTBS_1

AGPREFAGPTEST

R2SET

C_RY_GCOMP_B

H2SYNCV2SYNC

DDC3CLKDDC3DATA

SSIN

SSOUT

XTALIN

XTALOUT

TESTEN

SUS_STAT#

GPIO0GPIO1GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7GPIO8GPIO9

GPIO10GPIO11GPIO12GPIO13GPIO14GPIO15GPIO16

ZV_LCDDATA0ZV_LCDDATA1ZV_LCDDATA2ZV_LCDDATA3ZV_LCDDATA4ZV_LCDDATA5ZV_LCDDATA6ZV_LCDDATA7ZV_LCDDATA8ZV_LCDDATA9

ZV_LCDDATA10ZV_LCDDATA11ZV_LCDDATA12ZV_LCDDATA13ZV_LCDDATA14ZV_LCDDATA15ZV_LCDDATA16ZV_LCDDATA17ZV_LCDDATA18ZV_LCDDATA19ZV_LCDDATA20ZV_LCDDATA21ZV_LCDDATA22ZV_LCDDATA23

ZV_LCDCNTL0ZV_LCDCNTL1ZV_LCDCNTL2ZV_LCDCNTL3

TXOUT_L0NTXOUT_L0PTXOUT_L1NTXOUT_L1PTXOUT_L2NTXOUT_L2PTXOUT_L3NTXOUT_L3P

TXCLK_LNTXCLK_LP

TXOUT_U0NTXOUT_U0PTXOUT_U1NTXOUT_U1PTXOUT_U2NTXOUT_U2PTXOUT_U3NTXOUT_U3PTXCLK_UNTXCLK_UP

DIGONBLON

TX0MTX0PTX1MTX1PTX2MTX2P

TXCMTXCP

DDC2CLKDDC2DATA

HPD1

RGB

HSYNCVSYNC

RSET

DDC1DATADDC1CLK

AUXWIN

DVOMODE

DBI_HIDBI_LO

TEST_YCLK(NC)

(NC)VREFG

TEST_MCLK(NC)

RSTB_MSK(NC)

AGP8X_DET#

PLLTEST(NC)

DPLUSDMINUS

GPIO3

TZ1431

TZ1411

TZ1419

TZ1430

PANEL_ID0

TZ1423

MCLK_SS

DVOMODE

GPIO1

ROM_ID1

GPIO6

TZ1422

TZ1416

ROM_ID3

DMINUS

M11_ALERT#

TZ1413

TZ1421

TZ1415

TZ1407

DPLUS

TZ1410

MEM_ID1

TZ1420

TZ1414

Z1424

LDDCCLK

TZ1425

TZ1417

ROM_ID2

GPIO0

LDDCDATA

TZ1429

ZV_LCDCNTL0

TZ1428

TZ1437

TZ1408

ZV_LCDCNTL1

TZ1424

TZ1412

GPIO4

GPIO8

ZV_LCDCNTL2

TZ1427

GPIO10

ZV_LCDCNTL3

TZ1426

M11_VREFG

TZ1435TZ1436

PANEL_ID1

TZ1409

TZ1434

MOBILITY M11-P_B (U8B)


2-14

MEM_QSA0

MEM_QSA7

MEM_MAA9

Z1510

MEM_DQMA#1

MEM_MAA13

Z1512

MEM_MAA14

Z1507

MEM_MAA12

MEM

OR

Y IN

TER

FAC

EA

Part 2 of 7

U8B

M11-P_A15-FSC

L25L26K25K26J26H25H26G26G30D29D28E28E29G29G28F28G25F26E26F25E24F23E23D22B29C29C25C27B28B25C26B26F17E17D16F16E15F14E14F13C17B18B17B15C13B14C14C16A13A12C12B12C10

C9B9

B10E13E12E10F12F11E9F9F8

E22B22B23B24C23C22F22F21C21A24C24A25E21B20

J25F29E25A27F15C15C11E11

J27F30F24B27E16B16B11F10

A19

E18

E19

E20

F20

B19

B21C20

C18A18

B7

B8

C19

D30B13

DQA0DQA1DQA2DQA3DQA4DQA5DQA6DQA7DQA8DQA9DQA10DQA11DQA12DQA13DQA14DQA15DQA16DQA17DQA18DQA19DQA20DQA21DQA22DQA23DQA24DQA25DQA26DQA27DQA28DQA29DQA30DQA31DQA32DQA33DQA34DQA35DQA36DQA37DQA38DQA39DQA40DQA41DQA42DQA43DQA44DQA45DQA46DQA47DQA48DQA49DQA50DQA51DQA52DQA53DQA54DQA55DQA56DQA57DQA58DQA59DQA60DQA61DQA62DQA63

MAA0MAA1MAA2MAA3MAA4MAA5MAA6MAA7MAA8MAA9

MAA10MAA11

(MAA13)MAA12(MAA12)MAA13

DQMA#0DQMA#1DQMA#2DQMA#3DQMA#4DQMA#5DQMA#6DQMA#7

QSA0QSA1QSA2QSA3QSA4QSA5QSA6QSA7

RASA#

CASA#

WEA#

CSA0#

CSA1#

CKEA

CLKA0CLKA0#

CLKA1CLKA1#

MVREFD

MVREFS

(NC)MAA14

DIMA_0DIMA_1

MEM_MAA3

MEM_MAA5

MEM_MAA11

MEM_MAA4

MEM_RASA#

MEM_DQMA#4

MEM_DQMA#0

MEM_CKEA

MEM_MAA8

MEM_MAA1

MEM_QSA1

Z1511

TZ1502

MEM_DQMA#3

MEM_MAA10

MEM_CSA0#

MEM_CASA#

MEM_WEA#

MEM_CSA1#

MEM_QSA2

MEM_QSA4MEM_QSA3

Z1508

MEM_MAA0

MEM_DQMA#5

MEM_MAA6

Z1509

MEM_QSA6

MEM_DQMA#7MEM_DQMA#6

MEM_MAA2

MEM_DQMA#2

MEM_QSA5

TZ1501

MEM_MAA7

MOBILITY M11-P_C (U8C)


2-15

MEM_QSB2

MEM_CSB0#

MEM_CKEB

TZ1503

MEM_QSB1

Z1520

MEM_MAB6

MEM_DQMB#7

MEM_MAB7

0:1=VDDR1 2.5V

MEM_DQMB#6

MEM_DQMB#2

MEM_DQMB#0

MEM_MAB4

MEM_MAB13MEM_MAB14

MEM_DQMB#4

Z1526

MEM_QSB3

MEM_DQMB#5M

EMO

RY

INTE

RFA

CE

B

Part 3 of 7

U8C

M11-P_A15-FSC

D7F7E7G6G5F5E5C4B5C5A4B4C2D3D1D2G4H6H5J6K5K4L6L5G2F3H2E2F2J3F1H3U6U5U3V6

W5W4Y6Y5U2V2V1V3

W3Y2Y3

AA2AA6AA5AB6AB5AD6AD5AE5AE4AB2AB3AC2AC3AD3AE1AE2AE3

N5M1M3L3L2M2M5P6N3K2K3J2P5P3

E6B2J5G3W6W2AC6AD2

F6B3K6G1V5W1AC5AD1

R2

T5

T6

R5

R6

R3

N1N2

T2T3

AF5

C6C7

C8

P2

E3AA3

DQB0DQB1DQB2DQB3DQB4DQB5DQB6DQB7DQB8DQB9DQB10DQB11DQB12DQB13DQB14DQB15DQB16DQB17DQB18DQB19DQB20DQB21DQB22DQB23DQB24DQB25DQB26DQB27DQB28DQB29DQB30DQB31DQB32DQB33DQB34DQB35DQB36DQB37DQB38DQB39DQB40DQB41DQB42DQB43DQB44DQB45DQB46DQB47DQB48DQB49DQB50DQB51DQB52DQB53DQB54DQB55DQB56DQB57DQB58DQB59DQB60DQB61DQB62DQB63

MAB0MAB1MAB2MAB3MAB4MAB5MAB6MAB7MAB8MAB9

MAB10MAB11

(MAB13)MAB12(MAB12)MAB13

DQMB#0DQMB#1DQMB#2DQMB#3DQMB#4DQMB#5DQMB#6DQMB#7

QSB0QSB1QSB2QSB3QSB4QSB5QSB6QSB7

RASB#

CASB#

WEB#

CSB0#

CSB1#

CKEB

CLKB0CLKB0#

CLKB1CLKB1#

ROMCS#

MEMVMODE_0MEMVMODE_1

MEMTEST

(NC)MAB14

DIMB_0DIMB_1

Z1524

Z1522

MEM_WEB#

1:1=VDDR1 2.8V

MEM_QSB6

TZ1504

MEM_MAB5

MEM_MAB0

MEM_MAB11

MEMV_MODE(1:0)=

MEM_QSB5

MEM_MAB12

Z1525

1:0=VDDR1 1.8V

MEM_MAB10

MEM_QSB0

Z1521

MEM_DQMB#1

MEM_MAB3

MEM_MAB8

Z1519

MEM_MAB2

MEM_CASB#

MEM_CSB1#

MEM_MAB9

MEM_QSB7

MEM_RASB#

MEM_QSB4

MEM_MAB1

MEM_DQMB#3

MOBILITY M11-P_D(U8D)


2-16

Z1601

MPVSS

Z1603

M11P_VDD15/18

R504 0R/B12

PVSS

LTPVSS

R507 @0R/B

12

AVSSQ

Part 4 of 7

I/O PO

WE

R

U8D

M11-P_A15-FSC

A9A15A21A28B1

B30D26D23D20D17D14D11D8D5

E27F4G7

G10G13G15G19G22G27H22H19

H17H15H13H10

J1J4

A3

AJ20

AE15AF21

AE17AE20

AJ19

AE16AF15

AF20AE19

AK12 AJ12

AF13AF14

AG14

AH12AG13

AG21AH21

AF22

AH24

AH22

AE21

AF23

L8

J8J23J24

L27M4N7N8R1R4T7

J7

F18N6

F19M6

A7 A6

AK28 AJ28

AC9AC10AD10

AD9

N30P23P27T23T24T30U27

V24V23W30Y27AA23AA24AB30AC23AC27AE30AF27

M23M24

AE24

AD24

AE23

AH23

T8V4V7V8

AA1AA4AA7AA8

AG7

AJ21

J30

AE22

T4N4

D13D19

AD7AD19AD21AD22AC22AC21AC19AC8

P8Y8AC11AC20Y23L23H20H11

AC13AD13AD15AC15AC17

AD4

VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1

VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1

VDDR1

LPVDD

LVDDR_18LVDDR_18

LVDDR_25(LVDDR18_25)LVDDR_25(LVDDR18_25)

LPVSS

LVSSRLVSSR

LVSSRLVSSR

TPVDD TPVSS

TXVDDRTXVDDR

TXVSSR

TXVSSRTXVSSR

A2VDDA2VDD

A2VDDQ

AVDD

A2VSSN

VSS2DI

A2VSSQ

VDDR1

VDDR1VDDR1VDDR1

VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1(CLKBFB)VDDR1

VDDR1

VDDRH0VDDRH1

VSSRH0VSSRH1

MPVDD MPVSS

PVDD PVSS

VDDR4VDDR4VDDR4

VDDR4

VDDPVDDPVDDPVDDPVDDPVDDPVDDP

VDDPVDDPVDDPVDDPVDDPVDDPVDDPVDDPVDDPVDDPVDDP

VDDPVDDP

VDD1DI

AVSSQ

VSS1DI

AVSSN

VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1VDDR1

VDDR4

A2VSSN

VDDP

VDD2DI

VDDR1VDDR1

VDDR1VDDR1(CLKAFB)

VDDR3VDDR3VDDR3VDDR3VDDR3VDDR3VDDR3VDDR3

(VDDC18)VDD15(VDDC18)VDD15(VDDC18)VDD15(VDDC18)VDD15(VDDC18)VDD15(VDDC18)VDD15(VDDC18)VDD15(VDDC18)VDD15

VDDCVDDCVDDCVDDCVDDC

VDDR1

+V3.3S

A2VSSQ

+V1.2S_M11

+V1.5S

AVSSDI

MOBILITY M11-P_E(U8E)


2-17

CORE GND

Part 5 of 7

U8E

M11-P_A15-FSC

A2A10A16A22A29C1C3

C28C30D27D24D21D18D15D12D9D6D4

F27G9

G12G16G18G21G24H27H23H21H18H16H14H12H9H8H4

K30

K8K7K1L4M30M8M7N23N24N27P4R7R8R23R24R30T27T1U4U8U23V30W7W8W23W24W27Y4AA30AB27AB24AB23AB8AB7AB1AC4

K27K24

AC12AC14

K23AC16AC18AD30AD25AD18

AD16

AD12AE27AG5AG9

AG11

AG15

AG18AG22AG27 AJ1

AJ30AK29AK2

D10D25

E4AB4

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSSVSS

VSSVSS

VSSVSS

VSSVSSVSSVSSVSSVSS

VSS

VSSVSSVSSVSSVSS

VSS

VSSVSSVSS VSS

VSSVSSVSS

VSSVSS

VSSVSS

MOBILITY M11-P_F(U8F)


2-18

CENTERARRAY

Part 6 of 7

M10-P

U8F

M11-P_A15-FSC

P17P18P19U12U13U14U17U18U19V19

M16N16N15P15P16R18R17R16R15

V18V17V14V13V12N18N17N14

R14R13R12T13T14T15W15V16

W17W18

V15U15U16T19T18T17T16

W16M15R19T12

W19

W12W13W14N13N19M19M18M12N12M13M14P12P13P14M17

VDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDC

VSSVSSVSSVSSVSSVSSVSSVSSVSS

VDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDC

VSSVSSVSSVSSVSSVSSVSSVSS

VDDCVDDC

VSSVSSVSSVSSVSSVSSVSS

VDDC1VDDC1VDDC1VDDC1

VDDC1

VDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDCVDDC

+V1.2S_M11

VDDC1+V1.2S_M11

DDR CHANNEL A (U13)(U36)


2-19

MEM_MAA13

MEM_MDA2

MEM_MDA24

MEM_MDA19

MEM_MAA11

MEM_DQMA#3

MEM_MAA7

MEM_CKEA

MEM_MDA27

TZ1820

TZ1807

TZ1823

DDRVREFA1

MEM_CLKA0#

MEM_MAA10 MEM_MDA6

MEM_WEA# TZ1804

MEM_CASA#

MEM_CKEA

MEM_MDA29

MEM_CSA0#

TZ1817

MEM_MAA5

MEM_CLKA0

MEM_MAA12

MEM_MAA12

MEM_MAA9

MEM_MDA25

MEM_QSA1

TZ1819

MEM_MAA4

MEM_MAA2

MEM_MAA13MEM_MDA23

TZ1806

TZ1802

TZ1824

MEM_DQMA#0

MEM_MDA22

MEM_MDA21

TZ1808

MEM_MDA10

MEM_MAA2

MEM_MDA16

MEM_MAA5

MEM_MAA14

MEM_QSA3

MEM_CLKA0#

MEM_MDA12

MEM_MAA3

MEM_MDA26

MEM_MAA9

MEM_MAA8

MEM_RASA#

MEM_MAA0

MEM_DQMA#1

MEM_MDA1MEM_MDA13

U13

8Mx16_K4D261638F-TC40

49

293031323536373839

2627

40

232221

24

45

44

41

9

245781011135456575960626365

118333

42

155561

344866

28

46

612525864

1651

2047

14171925435053

VREF

A0A1A2A3A4A5A6A7A8

BA0BA1

A9

RASCASWE

CS

CLK

CKE

A11

VDDQ

DQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7DQ8DQ9

DQ10DQ11DQ12DQ13DQ14DQ15

VDDVDDVDD

VDDQ

A12

VDDQVDDQVDDQ

VSSVSSVSS

A10/AP

CLK

VSSQVSSQVSSQVSSQVSSQ

LDQSUDQS

LDMUDM

NC1NC1NC1NC1NC1NC1NC1

MEM_MAA7

TZ1803

MEM_MAA0

MEM_QSA2

MEM_CASA#

MEM_MAA6

MEM_MDA5

TZ1818

MEM_MDA11

TZ1801

TZ1822

+V2.5S

MEM_MAA14

MEM_CSA0#MEM_RASA#

MEM_MDA9

MEM_MDA14

U38

8Mx16_K4D261638F-TC40

49

293031323536373839

2627

40

232221

24

45

44

41

9

245781011135456575960626365

118333

42

155561

344866

28

46

612525864

1651

2047

14171925435053

VREF

A0A1A2A3A4A5A6A7A8

BA0BA1

A9

RASCASWE

CS

CLK

CKE

A11

VDDQ



VDDVDDVDD

VDDQ

A12

VDDQVDDQVDDQ

VSSVSSVSS

A10/AP

CLK


LDQSUDQS

LDMUDM


MEM_MAA6

MEM_WEA#

MEM_QSA0

MEM_MDA30

MEM_MDA7

MEM_MDA8

MEM_MDA18

MEM_MDA4

MEM_MAA4

MEM_CLKA0

MEM_MDA20

MEM_MDA15

MEM_MAA10MEM_MDA31

+V2.5S

MEM_MAA8

MEM_MDA3

DDRVREFA0

MEM_MAA3MEM_MDA17

MEM_MAA1

MEM_MDA28

MEM_MAA11

MEM_DQMA#2

MEM_MDA0

MEM_MAA1

DDR CHANNEL A (U11)(U38)


2-20

MEM_MDA44

MEM_WEA#

TZ1825

MEM_DQMA#6

MEM_MDA57

MEM_MDA36

MEM_CLKA1

MEM_MAA7

MEM_MAA1

MEM_MDA43

MEM_MDA33

TZ1814

MEM_CLKA1

MEM_MDA37

MEM_QSA6

U11

8Mx16_K4D261638F-TC40

49

293031323536373839

2627

40

232221

24

45

44

41

9

245781011135456575960626365

118333

42

155561

344866

28

46

612525864

1651

2047

14171925435053

VREF

A0A1A2A3A4A5A6A7A8

BA0BA1

A9

RASCASWE

CS

CLK

CKE

A11

VDDQ



VDDVDDVDD

VDDQ

A12

VDDQVDDQVDDQ

VSSVSSVSS

A10/AP

CLK


LDQSUDQS

LDMUDM


MEM_RASA#

MEM_MDA39

TZ1828

MEM_MDA58

MEM_MAA14

MEM_MAA0

MEM_CKEA

MEM_RASA#

MEM_WEA#

MEM_MDA50

MEM_MDA45

MEM_MAA4

MEM_MAA2

MEM_CASA#

MEM_MDA38

MEM_DQMA#4

MEM_MDA48

MEM_MAA11

MEM_MDA56

MEM_CLKA1#

MEM_DQMA#7

MEM_QSA7

MEM_MDA49

U36

8Mx16_K4D261638F-TC40

49

293031323536373839

2627

40

232221

24

45

44

41

9

245781011135456575960626365

118333

42

155561

344866

28

46

612525864

1651

2047

14171925435053

VREF

A0A1A2A3A4A5A6A7A8

BA0BA1

A9

RASCASWE

CS

CLK

CKE

A11

VDDQ



VDDVDDVDD

VDDQ

A12

VDDQVDDQVDDQ

VSSVSSVSS

A10/AP

CLK


LDQSUDQS

LDMUDM


DDRVREFA0_BOT

MEM_MDA53

MEM_CSA0#

MEM_MAA5

TZ1826

MEM_MDA34

MEM_CASA#

MEM_CSA0#

MEM_MDA51

MEM_MDA62

MEM_QSA4

MEM_CKEA

MEM_MAA3

TZ1827

MEM_MDA42MEM_MAA7

MEM_MAA6

MEM_MDA40

+V2.5S

MEM_CLKA1#

MEM_MAA11

MEM_MAA5

DDRVREFA1_BOT

MEM_MDA35

MEM_MAA12

MEM_MAA6

+V2.5S

MEM_MDA54

MEM_MAA13

MEM_MDA41

TZ1812

TZ1831

MEM_MAA8

MEM_QSA5

MEM_MDA55

MEM_MAA9

MEM_MAA14

MEM_MAA10

MEM_MDA60

TZ1809

MEM_MDA47

MEM_MDA32

MEM_MDA63MEM_MAA0

MEM_MAA9

MEM_MAA1

MEM_MDA52

TZ1810

MEM_MDA46

MEM_MAA12

TZ1816

MEM_MAA8

MEM_MAA3

MEM_MAA4

TZ1811

TZ1832

MEM_MDA61

MEM_DQMA#5

MEM_MAA2

TZ1815

MEM_MAA13

MEM_MAA10

TZ1830

MEM_MDA59

DDR CHANNEL B (U34)(U7)


2-21

MEM_MAB8

MEM_MDB11MEM_MDB8

MEM_QSB3

U7

8Mx16_K4D261638F-TC40

49

293031323536373839

2627

40

232221

24

45

44

41

9

245781011135456575960626365

118333

42

155561

344866

28

46

612525864

1651

2047

14171925435053

VREF

A0A1A2A3A4A5A6A7A8

BA0BA1

A9

RASCASWE

CS

CLK

CKE

A11

VDDQ



VDDVDDVDD

VDDQ

A12

VDDQVDDQVDDQ

VSSVSSVSS

A10/AP

CLK


LDQSUDQS

LDMUDM


MEM_MAB0

MEM_MDB29

TZ1904

MEM_MAB12

MEM_MAB1

MEM_MDB20

MEM_MAB14

TZ1917

MEM_DQMB#1

MEM_MAB9

MEM_MAB7

MEM_MDB6

TZ1903

MEM_CSB0#

DDRVREFB1

MEM_MAB3

MEM_MDB9

TZ1902

MEM_MAB10

MEM_MDB19

TZ1918

MEM_DQMB#2

MEM_MDB13

MEM_DQMB#0

MEM_MDB0

MEM_MAB2

TZ1923

MEM_MDB10

MEM_CLKB0

PLACE NEAR U

MEM_MDB3MEM_MDB4

MEM_WEB#

MEM_QSB0

MEM_MAB13

MEM_MAB9

MEM_QSB1

MEM_CASB#

MEM_MDB16

MEM_MDB2

MEM_MAB3

MEM_MAB11

MEM_CASB#

MEM_MAB5

DDRVREFB0

MEM_MDB24

MEM_MDB26

MEM_CLKB0#

TZ1920

MEM_DQMB#3

MEM_MAB11

MEM_CSB0#

MEM_MAB2

MEM_WEB#

MEM_MAB10

MEM_MDB30

TZ1901

MEM_MDB18

TZ1919

TZ1907

MEM_CKEB

MEM_MAB7

MEM_MAB12

MEM_MAB0

MEM_MDB23

MEM_MDB25

TZ1922

MEM_MAB13

MEM_MAB6

U34

8Mx16_K4D261638F-TC40

49

293031323536373839

2627

40

232221

24

45

44

41

9

245781011135456575960626365

118333

42

155561

344866

28

46

612525864

1651

2047

14171925435053

VREF

A0A1A2A3A4A5A6A7A8

BA0BA1

A9

RASCASWE

CS

CLK

CKE

A11

VDDQ



VDDVDDVDD

VDDQ

A12

VDDQVDDQVDDQ

VSSVSSVSS

A10/AP

CLK


LDQSUDQS

LDMUDM


MEM_MAB6

MEM_QSB2

MEM_MDB14

MEM_RASB#

MEM_MDB28

MEM_MDB27

MEM_MDB15

MEM_MAB5

MEM_MAB1

MEM_MDB31

MEM_MDB12

MEM_MDB21

MEM_MDB1

TZ1924

MEM_MAB14

MEM_RASB#

MEM_MAB8

MEM_MDB17

+V2.5S

MEM_CLKB0

TZ1908

MEM_MDB7

MEM_MDB5

TZ1906

MEM_MAB4

MEM_CKEB

MEM_MAB4MEM_MDB22

MEM_CLKB0#

DDR CHANNEL B (U6)(U33)


2-22

MEM_MAB7

MEM_MAB8

MEM_MAB12

MEM_MAB6

MEM_MAB14

TZ1911

MEM_MDB63

MEM_CKEB

MEM_DQMB#4

MEM_MDB46

MEM_CASB#

MEM_MAB1

MEM_QSB5

TZ1915

TZ1932

MEM_WEB#

MEM_MAB5

MEM_MDB58

MEM_MAB10

DDRVREFB0_BOT

MEM_MAB9

TZ1914

MEM_DQMB#7

MEM_CSB0#

MEM_MDB62MEM_MAB11

+V2.5S

MEM_MAB0

MEM_QSB6

TZ1912

DDRVREFB1_BOT

MEM_MDB40

MEM_CSB0#

MEM_MAB14

MEM_MDB54

MEM_MAB7

MEM_DQMB#5

U33

8Mx16_K4D261638F-TC40

49

293031323536373839

2627

40

232221

24

45

44

41

9

245781011135456575960626365

118333

42

155561

344866

28

46

612525864

1651

2047

14171925435053

VREF

A0A1A2A3A4A5A6A7A8

BA0BA1

A9

RASCASWE

CS

CLK

CKE

A11

VDDQ



VDDVDDVDD

VDDQ

A12

VDDQVDDQVDDQ

VSSVSSVSS

A10/AP

CLK


LDQSUDQS

LDMUDM


MEM_MDB53

MEM_QSB7

MEM_MAB10

MEM_WEB#

MEM_CLKB1

MEM_MDB33

TZ1930

MEM_MDB49

TZ1931

MEM_MAB13

MEM_MDB59

MEM_MAB2

MEM_MDB45

MEM_CLKB1#

MEM_MAB0

MEM_MAB9

U6

8Mx16_K4D261638F-TC40

49

293031323536373839

2627

40

232221

24

45

44

41

9

245781011135456575960626365

118333

42

155561

344866

28

46

612525864

1651

2047

14171925435053

VREF

A0A1A2A3A4A5A6A7A8

BA0BA1

A9

RASCASWE

CS

CLK

CKE

A11

VDDQ



VDDVDDVDD

VDDQ

A12

VDDQVDDQVDDQ

VSSVSSVSS

A10/AP

CLK


LDQSUDQS

LDMUDM


MEM_CASB#

MEM_MDB43

MEM_CLKB1

TZ1909

MEM_CKEB

MEM_MAB4

MEM_MDB36MEM_MAB6

MEM_MDB35

MEM_MAB12

MEM_MAB3

MEM_MAB11

TZ1910

MEM_MDB61

MEM_MDB56

MEM_MAB4

MEM_MDB48

MEM_MDB47

+V2.5S

MEM_MDB42

MEM_MDB38

TZ1928

MEM_MDB50

MEM_MDB39

MEM_MDB51

MEM_MAB2

MEM_MDB34

TZ1925

MEM_MDB60

MEM_MDB32

MEM_QSB4

MEM_CLKB1#

MEM_MAB1

MEM_MDB44

TZ1926

MEM_RASB#

MEM_MAB5

MEM_MDB52

MEM_MDB57

TZ1927

MEM_MAB8

MEM_MDB41

MEM_MDB55

MEM_MAB3

MEM_RASB#

MEM_MAB13

TZ1916

MEM_DQMB#6

MEM_MDB37

CODEC (U24)


2-23

VAUX

AUX_L

LINE_L

TZ2405

TZ2410

AFILT1

MIC2

VRAD

Z2408TZ2403

Z2416

VIDEO_L

C300 1U21

TZ2407

AUX_R

PHONE

CAP2

VREF

Z2407

SPDIFO

TEST1

AFILT2

TZ2401

Z2418

VIDEO_R

Z2402

C316 1U21

MONO

Codec

LINE_RTZ2404

Z2443

TZ2408

TZ2402

VREFOUT

MIC1

R334

0R

12

+V5S_AUD

TZ2409

GND_AUD

Z2415

Z2406

Z2401

U24

VT1612A

116

1058

12

13

1415

1617

18

20

2122

2324

47 26

42

23

35

36

37

2728

29303132

33

34

43

444546

4748

394041

19

19

2538

RESET#BIT-CLKSYNCSDATA-OUTSDATA-IN

PC-BEEP

PHONE

AUX-LAUX-R

VIDEO-LVIDEO-R

CD-L

CD-R

MIC1MIC2

LINE-LLINE-R

VSSVSS AVSS

AVSS

XTL-INXTL-OUT

LINE-OUTL

LINE-OUTR

MONO-OUT

VREFVREFOUT

AFILT1AFILT2VRADVRDA

DC_VOL

VAUX

JD/SDIN1

TEST1ID0#ID1#

EAPDSPDIFO

HP-OUT-LNC

HP-OUT-R

CD-GND

VDDVDD

AVDDAVDD

AMPLIFIER(U19)

Audio Amp.

U19

TPA6011A

1

2

3

711

12

13

14

18

248

910

45

6

192021

151617

2223

PGND

ROUT-

PVDD

VDDPVDD

LOUT-

PGND

LOUT+

AGND

ROUT+LIN

LLINEINLHPIN

RHPINRLINEIN

RIN

SEMAXSEDIFFVOLUME

SHUTDOWN#FADE#BYPASS

HP/LINE#SE/BTL#

SPK_L-

SPK_R+

Z2429

7/8

Z2426Z2425

SPK_L+

Z2427

GND_AUD

SPK_R-

+V5S_AUD

BYPASS/A

Z2424

Z2428

IEEE1394(U22)


2-24

1394_TEST0

1394_TEST16

TZ2604

1394_TEST3

1394_TEST1

Z2605

1394_SCL

TZ

2606

1394_PC2

R332 @0R12

XO_1394

1394_SDA

1394_GPIO2

1394_TEST8

TZ2601

1394_GPIO3

U22

TSBA43AB22A

8482818079777674717069676665636146454342414038373231292826252422

73604734

16

58

49

5250

5436

1918

5657

53

85

13

21

91

110

109

103

8375686455443323179330 128

127

1527395159 120

7288100

112113114115116

121122123124125

78

106

126

117

108

107

2 111

1

98

1110

62 48 35 20

999897

105104102101

96

9594

92

7

9089

8786

1214

5

6

119

118

3

4

PCI_AD0PCI_AD1PCI_AD2PCI_AD3PCI_AD4PCI_AD5PCI_AD6PCI_AD7PCI_AD8PCI_AD9PCI_AD10PCI_AD11PCI_AD12PCI_AD13PCI_AD14PCI_AD15PCI_AD16PCI_AD17PCI_AD18PCI_AD19PCI_AD20PCI_AD21PCI_AD22PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27PCI_AD28PCI_AD29PCI_AD30PCI_AD31

PCI_CBE0#PCI_CBE1#PCI_CBE2#PCI_CBE3#

PCI_CLK

PCI_PAR

PCI_FRAME#

PCI_TRDY#PCI_IRDY #

PCI_STOP#PCI_IDSEL

PCI_REQ#PCI_GNT#

PCI_PERR#PCI_SERR#

PCI_DEVSEL#

PCI_RST#

PCI_INTA#

PCI_PME#

SCL

AG

ND

AG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

DG

ND

RE

G18

RE

G18

AG

ND

AG

ND

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

AV

DD

DV

DD

DV

DD

DV

DD

TPB0-TPB0+TPA0-TPA0+

TPBIAS0

TPB1-TPB1+TPA1-TPA1+

TPBIAS1V

DD

P

CPS

AN

GD

AG

ND

AV

DD

AV

DD

AV

DD

AV

DD

AG

ND

RE

G_E

N#

PLL

GN

D1

TEST16TEST17

VD

DP

VD

DP

VD

DP

VD

DP

PC0PC1PC2

TEST0TEST1TEST2TEST3

CNA

TEST8TEST9

SDA

PLL

VD

D

GPIO2GPIO3

CYCLEINCY CLEOUT

PCI_CLKRUN#G_RST#

XI

XO

R1

R0

FILTER0

FILTER1

TZ2603

R312 6.34K/F1 2Z2603

Z2606

Z2604

XTPB0P

1394_CNA

XTPBIAS0

1394_PC1

XI_1394

1394_PC0

1394_TEST9

1394_CY CLEOUT

XTPB0M

1394_TEST2

TZ2605

1394_CPS

1394_CY CLEIN

TZ2602

TZ

2607

XTPA0M

1394_TEST17

XTPA0P

PCMCIA(U20)


2-25

CAD10

PCI_AD27

PCI_AD19

CAD31

CAD4PCI_AD26

PCI_AD15

U20

711MC1

18 30 50 14

66

86 102

122

138

63 126

1441421411401391291281271241211201181161151139896979395929189878582838081777976

1081111101091071051011041331231061321031361191438410013111775137134135

1251129988

34

12273748

13

21

32

28293133

36

3435

12

20

59

62

69

65

60

6 22 42 94 114

130

26252423191716151110

9875

57565554535251494746454341403938

70

68676461587890

72

717473

44

PC

I_V

CC

PC

I_V

CC

PC

I_V

CC

CO

RE

_VC

C

GBRST

CO

RE

_VC

CC

OR

E_V

CC

CO

RE

_VC

CC

OR

E_V

CC

AU

X_V

CC

SK

T_V

CC

CAD31CAD30CAD29CAD28CAD27CAD26CAD25CAD24CAD23CAD22CAD21CAD20CAD19CAD18CAD17CAD16CAD15CAD14CAD13CAD12CAD11CAD10CAD9CAD8CAD7CAD6CAD5CAD4CAD3CAD2CAD1CAD0

CCLKCFRAME#

CIRDY#CTRDY#

CDEVSEL#CSTOP#

CPARCPERR#CSERR#

CREQ#CGNT#CINT#

CBLOCK#CCLKRUN#

CRST#R2_D2

R2_D14R2_A18

CVS1CVS2

CCD1#CCD2#

CAUDIOCSTSCHG

CC/BE3#CC/BE2#CC/BE1#CC/BE0#

AD31AD30

C/BE3#C/BE2#C/BE1#C/BE0#

IDSEL

PCI_CLK

DEVSEL#

FRAME#IRDY#TRDY#STOP#

PAR

PERR#SERR#

REQ#GNT#

RST#

RI_OUT#/PME#

SPKR_OUT#

MF6--CLKRUN#

MF3--IRQSER

MF0--INTA#

GN

DG

ND

GN

DG

ND

GN

DG

ND

AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29

AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15

CO

RE

_VC

C(S

US

PE

ND

#)

MS_BS(MF5)MS_CD#(MF4)DWP(MF2)ODR_DATA0(MF1)ODR_DATA1(GND)ODR_DATA2(GND)ODR_DATA3(SKT_VCC)

ODR_CLK(VPPD1/VPP_VCC)

SLATCH/VPPD0/VPP_PGMSCLK/VCCD1#/VCC3#SDAT/VCCD0#/VCC5#

ODR_CD#(PCI_VCC)

CAD28

CAD16

PCI_AD8

CAD20

CAD17

CAD7

PCI_AD20

PCI_AD2

PCI_AD17CAD15

PCI_AD30

PCI_AD1

CAD24

CAD13

PCI_CBE#0

CAD27

PCI_AD14

CAD3

CAD1

PCI_AD0

PCI_CBE#1

CAD2

CAD21

PCI_AD7

PCI_AD16

PCI_AD25

CAD11

CAD22

CAD12

CAD0

Z2712

PCI_AD11

PCI_AD31

PCI_CBE#3

CAD18

CAD14

PCI_AD21

CAD29

PCI_AD9

PCI_CBE#2

CB_MF0

PCI_AD22

PCI_AD10

CAD25

CAD19PCI_AD13

PCI_AD18

CAD8PCI_AD24

PCI_AD12

CAD26

CAD23

PCI_AD4

CAD30

PCI_AD6

PCI_AD29PCI_AD28

CAD9

CAD6

PCI_AD5

CAD5

GBRST_CB#

PCI_AD23

PCI_AD3

IEEE1394 (U37)


2-26

PCI_AD5

PCI_AD12

PCI_CBE#3

PCI_AD2

HSDAC+

PCI_AD16

ACTIVITY#

LAN_EE_CS

PCI_AD31Z2905

LINK_UP#

PCI_AD14

LAN_EE_DI

Z2906

R129 0R1 2

Z2903

LAN_EE_SK

TZ2902

PCI_CBE#0R141 0R1 2

PCI_AD8

PCI_AD11

PCI_AD26

PCI_AD6

PCI_AD28

LAN_EE_DO

PCI_AD7

R128 0R1 2PCI_AD27

PCI_AD21

Z2907

PCI_AD3

PCI_AD0

Z2902

PCI_AD25

LINK1000#

PCI_AD20

ISOLATE#

R585 0R1 2

PCI_AD30

PCI_AD17

Z2904

PCI_AD23

PCI_AD15

PCI_AD4

LINK100#

Z2909

LWAKE

PCI_AD19

PCI_AD24

PCI_AD13

Z2908

PCI_CBE#1

RTL8100C/RTL8110S-32/RTL8110SB

PCI_AD1

PCI_AD9

U37

RTL8100CL

12

34

56

7

8

9

10

11

12

13

1415

16

17

1819

20

2122

23

24

25

26

27

28

2930

31

32

3334

35

3637

38

3940

41

4243

44

45

46

47

48

4950

5152

53

54

55

56

575859

60

61

62

63

64102

101

100

99

98979695

94

93

92

91

9089

88

878685

848382

8180

79

78

77

76

75

74

73

72

71

7069

68

67

66

65

128

127

126

125

124

123

122

121

120

119

118

117

116

115114

113

112

111

110

109108

107

106

105

104103 MDI0+

MDI0-

AVD

D33

/AV

DD

L/A

VD

DL

GN

D/V

SS/

VSS

MDI1+MDI1-

AVD

D33

/AV

DD

L/A

VD

DL

CTRL25

NC

/VSS

/VSS

NC

/AV

DD

H/A

VD

DH

(NC)HSDAC+

AVDD25/NC/NC

NC

/VSS

/VSS

NC/MDI2+NC/MDI2-

NC

/AV

DD

L/A

VD

DL

GN

D/V

SS/

VSS

NC/MDI3+NC/MDI3-A

VDD

33/A

VD

DL/

AV

DD

L

GN

D/V

SSP

ST/V

SSPS

T

NC

/GN

D/G

ND

ISOLATEB

NC

/VD

D18

/VD

D12

INTAB

VD

D33

RSTB

CLK

GNTBREQB

PMEB

VD

D25

/VD

D18

/VD

D12

AD31AD30

GN

D

AD29AD28

GN

D/V

SSP

ST/V

SSPS

T

AD27AD26

VD

D33

AD25AD24

CBE3B

NC

/VD

D18

/VD

D12

IDSEL

AD23

NC

/GN

D/G

ND

AD22AD21

GN

D/V

SSP

ST/V

SSPS

T

GN

D

AD20

VD

D25

/VD

D18

/VD

D12

AD19

VD

D33

AD18AD17AD16

CBE2B

FRAMEB

NC

/GN

D/G

ND

IRDY B

NC

/VD

D18

/VD

D12

AD2

GN

D/V

SSP

ST/V

SSPS

T

GN

D

VD

D25

/VD

D18

/VD

D12

AD3AD4AD5AD6

VD

D33

AD7

CBE0B

GN

D/V

SSP

ST/V

SSPS

T

AD8AD9

NC/M66EN/M66EN

AD10AD11AD12

VD

D33

AD13AD14

GN

D/V

SSP

ST/V

SSPS

T

GN

D

AD15

VD

D25

/VD

D18

/VD

D12

CBE1B

PAR

SERRB

(NC)SMBDATA

NC

/GN

D/G

ND

(NC)SMBCLK

VD

D33

PERRBSTOPB

DEVSELB

TRDYB

GN

D/V

SSP

ST/V

SSPS

T

CLKRUNB

GN

D/V

SS/

VSS

RSET

NC

/VD

D18

/VD

D12

NC/CTRL18/CTRL12

GND/VSS/VSS

GND/VSS/VSS

XTAL2

XTAL1

NC/AVDDH/AVDDH

GN

D/V

SSP

ST/V

SSPS

T

NC

/GN

D/G

ND

LED0

NC

/VD

D18

/VD

D12

LED1LED2

LED3

NC

/GN

D/G

ND

EESK

NC

/VD

D18

/VD

D12

EEDIEEDO

VD

D33

EECS

LWAKE

AD0AD1

PCI_AD10

PCI_CBE#2

PCI_AD18

Z2901

TZ2903

PCI_AD29

PCI_AD22

PCI_IDSEL#LAN

KEYBOARD CONTROLLER (U40)


2-27

IT8511E

KB Matrix

Interface

EmbeddedController

U40

IT8510

56

141310

199

7

18

3122

23

16 34 45 123

136

95161

158160

124125126127128131132133

138139140141144145146147

150151

9617 35 46 122

159

157

166

167

137

143142135134130129121120113112104103

173

9798

15

110111114115

116117118119

99100101102

8182838487888990 2

442425

262930

41426263

3233363738394043

148149152155156168174

48545569707576

105

34

2728

471691701711721751761

153154162163164165

811122021858691

929394106107108109

49505152535657585960616465666768

7172737477787980

GA20/GPB5KBRST/GPB6

LAD1LAD2LAD3

WRSTLFRAME

SERIRQ

LPCCLK

ECSCI/GPD3ECSMI

PWUREQ

VC

C

VST

BYVS

TBY

VST

BYVS

TBY

AVC

CVB

AT

CK32KCK32KE

FA0FA1

BADDR0/FA2BADDR1/FA3

FLASHTRI/FA4SHBM/FA5

FA6FA7

FD0FD1FD2FD3FD4FD5FD6FD7

FRDFWR

AVS

S

VSS

VSS

VSS

VSS

VSS

VST

BYVS

TBY

VSS

VSS

FA8/ID0FA9/ID1

FA10/ID2FA11/ID3

FA12FA13FA14FA15FA16

GPG1/FA17GPG2/FA18GPG3/FA19

FCS

DAC4DAC5

LAD0

PS2CLK0/GPCF0PS2DAT0/GPCF1PS2CLK1/GPCF2PS2DAT1/GPCF3

PS2CLK2/GPCF4PS2DAT2/GPCF5PS2CLK3/GPCF6PS2DAT3/GPCF7

DAC0DAC1DAC2DAC3

ADC0ADC1ADC2ADC3ADC4/GPE0ADC5/GPE1ADC6/GPE2ADC7/GPE3 PWRSW/GPE4

WUI5/GPE5LPCPD/WUI6/GPE6

CLKRUN/WUI7/GPE7

RI1/WUI0/GPD0RI2/WUI1/GPD1

LPCRST/WUI4/GPD2

GPD4GINT/GPD5

TACH0/GPD6TACH1/GPD7

PWM0/GPA0PWM1/GPA1PWM2/GPA2PWM3/GPA3PWM4/GPA4PWM5/GPA5PWM6/GPA6PWM7/GPA7

GPI0GPI1GPI2GPI3GPI4GPI5GPI6

GPH0GPH1GPH2GPH3GPH4GPH5GPH6GPH7

GPG4/FA20GPG5/FA21GPG6/LPC80HLGPG7/LPC80LL

CLKOUT/GPC0SMCLK1/GPC1SMDAT1/GPC2

CRX/GPC3TMRI0/WUI2/GPC4

CTX/GPC5TMRI1/WUI3/GPC6

CK32KOUT/GPC7

GPB0/RXDGPB1/TXDGPB2GPB3/SMCLK0GPB4/SMDAT0GPB7/RING/PWRFAIL/LPCRST

GPJ0GPJ1GPJ2GPJ3GPJ4GPJ5/KSO16GPJ6/KSO17GPJ7

GPK0GPK1GPK2GPK3

ISAD/GPK4ISAS/GPK5

ISCLK/GPK6

KSO0KSO1KSO2KSO3KSO4KSO5KSO6KSO7KSO8KSO9KSO10KSO11KSO12KSO13KSO14KSO15

KSI0KSI1KSI2KSI3KSI4KSI5KSI6KSI7

3V,5V,&12V(PU2)


2-28

Z 3613

Z 3604

Z 3603 Z 3612

PC 1034.7U /16V/C2

1

Z 3618

Z 3619

Z 3617

Z 3620Z 3625

Z 3622

Z 3614

PU 2

SC 1404

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

2122

23

24

25

26

27

28

C SH 3

C SL3

C OMP3

12OU T

VD D

SY N C

TIME/ON 5

GN

D

R EF

PSAVE

RE

SET

C O MP5

C SL5

C SH 5

SEQ

D H 5

PH ASE5

BST5

D L5

PGN D

VLV+

SH D N

D L3

BST3

PH ASE3

D H 3

R U N /ON 3

Z 3606Z 3616

PR 56

10K

12

Z 3623

Z 3615Z 3605

Z 3608

Z 3610

Z 3607

Z 3628

Z 3609

VCORE (PU12)

PU12

LTC3734

1

2

3

5

6

7

8

4

9 10 11 12 13 14 15 16

17

18

19

20

21

22

23

24

2526272829303132

VOA+

VOA-

OAOUT

SGND

SENSE+

SENSE-

RDPRSLP

STP_CPUB

RD

PS

LP

RU

N/S

S

ITH

RB

OO

T

VID

0

VID

1

VID

2

N/C

VID3

VID4

VID5

PGND

BG

PVCC

SW

TG

BO

OST

PG

OO

D

MC

H_P

G

VFB

SVC

C

DPR

SLP

VR

FRE

QS

ET

PS

IB

DDR & 1.8 POWER (PU9)


2-29

PU9ISL6225CA

1

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

17

18

19

20

22

23

21

24

25

26

27

28GND

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

ISEN1

EN1

VOUT1

VSEN1

OCSET1

SOFT1

DDR

VIN PG1

PG2/REF

SOFT2

OCSET2

VSEN2

VOUT2

ISEN2

BOOT2

EN2

UGATE2

PHASE2

PGND2

LGATE2

VCC

1.2V & 1.5 POWER (PU8)

Z3904

Z3913

Z3907

PU8ISL6225CA

1

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

17

18

19

20

22

23

21

24

25

26

27

28GND

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

ISEN1

EN1

VOUT1

VSEN1

OCSET1

SOFT1

DDR

VIN PG1

PG2/REF

SOFT2

OCSET2

VSEN2

VOUT2

ISEN2

BOOT2

EN2

UGATE2

PHASE2

PGND2

LGATE2

VCC

Z3906

Z3905

PC106

0.1U/25V

21

Z3909

Z3908

Z3903

2.3 Connectors Definition


2-30

DDR (CN12)

SM_VREF_DIMM

CN12

AMP=DDR_1376409-1(RVS)DDR_REV

12

124123

101

105

107108

110111112

116117

119120

97

193195

200

197

99100

102

106

109

115

118

98

85

199

194196198

86

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113

114

131

132

143

144

155

156

157

167

168

179

180

191

192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103

104

125

126

137

138

149

150

159

161

162

173

174

185

186

571317681418192329312024303241434953424450545559656756606668127129135139128130136140141145151153142146152154163165171175164166172176177181187189178182188190

12264862

13414817018478

11254761

13314716918377

7173798372748084

121122

9695

3537

1601588991

VREFVREF

NCNC

A9

A7

A5A4

A2A1A0

BA1BA0

WE#CAS#

NC/A13

SDASCL

NC

VddSPD

A12A11

A8

A6

A3

A10 / AP

RAS#

NC/BA2

NC

VddID

SA0SA1SA2

NC/(RESET#)

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

DV

DD

VD

D

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS


DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63

DM0DM1DM2DM3DM4DM5DM6DM7DM8

DQS0DQS1DQS2DQS3DQS4DQS5DQS6DQS7DQS8

CB0CB1CB2CB3CB4CB5CB6CB7

CS0#CS1#

CKE0CKE1

CK0CK0#CK1CK1#CK2CK2#

DDR (CN11)


2-31

SM_VREF_DIMM

CN11

AMP=DDR_1376408-1(STD)DDR_STD

12

124123

101

105

107108

110111112

116117

119120

97

193195

200

197

99100

102

106

109

115

118

98

85

199

194196198

86

9 10 21 22 33 34 36 45 46 57 58 69 70 81 82 92 93 94 113

114

131

132

143

144

155

156

157

167

168

179

180

191

192

3 4 15 16 27 28 38 39 40 51 52 63 64 75 76 87 88 90 103

104

125

126

137

138

149

150

159

161

162

173

174

185

186

571317681418192329312024303241434953424450545559656756606668127129135139128130136140141145151153142146152154163165171175164166172176177181187189178182188190

12264862

134148170184

78

11254761

133147169183

77

7173798372748084

121122

9695

3537

160158

8991

VREFVREF

NCNC

A9

A7

A5A4

A2A1A0

BA1BA0

WE#CAS#

NC/A13

SDASCL

NC

VddSPD

A12A11

A8

A6

A3

A10 / AP

RAS#

NC/BA2

NC

VddID

SA0SA1SA2

NC/(RESET#)

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS


DQ10DQ11DQ12DQ13DQ14DQ15DQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23DQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31DQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39DQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47DQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55DQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63

DM0DM1DM2DM3DM4DM5DM6DM7DM8

DQS0DQS1DQS2DQS3DQS4DQS5DQS6DQS7DQS8

CB0CB1CB2CB3CB4CB5CB6CB7

CS0#CS1#

CKE0CKE1

CK0CK0#CK1CK1#CK2CK2#

INVERTER CONN. (CN21)


2-32

F5

FCC32202_2A/32V

C343

@0.1U/25V

21

Z2102

CN21

ACES=85204-0800INVERTER_CONN

12345678

Z2103

L51BLM11P600S

21

Z2101

S-VIDEO CONN. (CN6)

CN6S-VIDEO_35146S-04T1-FS-VIDEO_CONN

2

34

1

5 6

TV_GND

LCD CONN. (CN3)

TXD5-

TXD1+

TXC0+

LDDCCLK

TXD1-

TXD5+

LDDCDATAPNLID1

+V3.3S_LCDCN3

ACES=87216-3012LCD_CON

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 30

TXC0-

TXC1-TXC1+

+V3.3S_LCD

TV IN CONN. (CN1)


2-33

S_CIN

RF_IN

AUDIO_INR

CN1

@TV IN CONN

1

2

3

4

5

67

89

1

2

3

4

5

67

89

S_Y IN

TV BOARD CONN. (CN4)

CN4

@TV BOARD CON

12345678

12345678

CRT CONN. (CN2)

TZ2101

CN2D-SUB_15P_DZ11A91-WL_31CRT_CONN

15

14

13

12

111

2

3

4

5

6

7

8

9

10

16 17

Z2110

C329

22P

21

C330

22P

21

Z2111

Z2107TZ2102

DVD CONN. (CN9)


2-34

IDE_SDD14

TZ2201

IDE_SDCS3#

IDE_SD_CSEL

IDE_SDD11

IDE_SDA2IDE_SATADET

IDE_SDD12

CN9

DVD_CON

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 52

IDE_SDD8

IDE_SDD13

IDE_SDD9

TZ2203

IDE_SDDREQIDE_SDIOR#

IDE_SDD10

IDE_SDD15

TZ2202IDE_SDDACK#

IDECD_R

HDD CONN. (CN31)

TZ2206

IDE_PDD11IDE_PDD10IDE_PDD9

IDE_PDD15

IDE_PDD13

IDE_PDA2

CN31

HDD CONN

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 46

IDE_PATADET

+V5S_HDD

IDE_PD_CSEL

IDE_PDD14

IDE_PDD12

IDE_PDCS3#

+V5S_HDD

TZ2204

IDE_PDD8

TZ2205

USB CONN.(CN23)


2-35

CN23C71080-A01USB_CON

1

4

23

5 6

USB CONN. (CN24)

CN24C71080-A01USB_CON

1

4

23

5 6

USB CONN. (CN25)

Z2308Z2307

Z2309 CN25C71080-A01USB_CON

1

4

23

5 6

MDC CONN. (CN33)

TZ2307

TZ2310

MDCPHONE

Z2304

+V3.3

Z2301

TZ2308

Z2305

R287 1K1 2

R289 33R

1 2

AC_BITCLK

Z2302

R291

@10K

12

CN33

88018-3000-0.8MMMDC_CONN

13579

11131517192123252729 30

282624222018161412108642

MONO_OUTGNDAUXRAUXLCD_GNDCD_RCD_LGND3.3Vaux/dualGND3.3VmainSDATA_OUTRESET#GNDMSTRCLK BITCLK

GNDSDATA_INASDATA_INB

SYNCGND

5VPRIMARY_DN

RESRES

5VmainGNDRES

MONO_PHONEAUDIO_PD

R290 33R

1 2

R288 0R1 2

MDCLK

AC_SYNC

TZ2312

TZ2309

TZ2311Z2303

05/29 Modify

AC_SDATAIN1

SPEAKER CONN. (CN22)


2-36

C340

680P

21

CN22

SPEAKER CONN

1234

NC1NC2

1234

NCNC

MIC JACK CONN. (CN28)

TZ2501

Z2502

TZ2502

4/28 follow 255iiCN28

2SJ-S820-027MIC_JACK

1263

54

78TZ2503

GND_AUD

MIC JACK CONN. (CN36)

GND_AUD

4/28 follow 255ii

CN36

@2SJ-S820-027MIC_JACK

1263

54

78

1394 CONN. (CN26)

TPB0+/1394

CN26

MOLEX=1394_54030-04911394_CONN

1234

56TPB-

TPB+TPA-TPA+

SHLDSHLD

TPB0-/1394

TPA0+/1394TPA0-/1394

LINE IN (CN29)


2-37

Z2528

GND_AUD

Z2527

CN29

2SJ-S820-027LINE_IN

1263

54

78

TZ2504

C126@1000P

21

TZ2505

4/28 follow 255iiC133@1000P

21

TZ2506

05/28


2-38

3.1. TOP Cabinet Assembly …………………………….…………………… 3

3.2. BUTTOM Cabinet Assembly………………………………….……..… 4

3.3. ODD Cabinet Assembly…………………………………………………... 5

3.4. LCD Assembly ………………………………………………….………. 6


3-2

3.1 Top Cabinet Assembly.

ITEM PART.NO. DESCRIPTION QTY. A 22-325040-00 SPEAKER SUB WOOFER 25SB04 259IA1 1 B XXXXXX MB-259IA1 1 C 83-UG8010-00 TOP CAB ASSY #8100/8151 259IA1 1 D 35-UG8050-00 HDD TRANSFER BD 259IA1 1


3-3

3.2 Buttom Cabinet Assembly.

ITEM PART.NO. DESCRIPTION QTY. A 83-UG5090-00 DOOR BTM ASSY #8155 255II1 1 B 40-UG9040-00 THERMAL MODULE YDT&BISONIC 255/259IAX 1 C 83-UG6020-00 BTM CAB ASSY(W/O TV) #8155 259IA1 1 D 52-UG5012-00 RUBBER FOOT ADD 2MM FOR 255II1 1 E 50-UG5010-00 COVER HDD #8155 255II1 1 F 86-UG5020-01 HDD ASSY 40GB 255II1 1 G 50-UG5061-00 DOOR USB DONGLE #8155 255II1 1


3-4

3.3 ODD Assembly.

ITEM PART. NO. DESCRIPTION QTY

1 50-UG5133-00 BEZEL DVD DUAL QSI #8155 255II1 1 2 50-UG5076-00 KNOB DVD DUAL QSI #8155 1 3 70-240006-10 DVD-DUAL SDW-042 4X QUANTA FW:DX71 1 4 40-UG6023-00 MYLAR HDD PULL BAR 258SA0 1 5 41-720120-04 SCREW M2.0*4 I #1 NI 2 6 41-910217-03 SCREW TP1.7*3 I #0 BLACK H=0.6 1


3-5

3.6 LCD Module Assembly.


3-6

ITEM PART. NO. DESCRIPTION QTY1 83-UG8052-00 BACK CAB ASSY #8100/8151 259IA1 1 2 29-UG8080-00 CABLE FOR MICPHONE FG259IA1 1 3 40-UD7800-00 MAGNETIC FOR SUSPEND SENSOR 258SA0 1 4 40-UG8030-00 SHIELDING FOR LCD 259IA1 1 5 29-UG8060-00 CABLE FOR LCD INVERTER CMI 259IA1 1 6 73-03D169-1A INVERTER MPT N169 MPS R:1A 1 7 50-UG8210-00 MYLAR FOR LCD INVERTER 259IA1 1 8 40-UG6025-00 HINGE+BKT LCD-R 15.4” (HONTECH) 159IA1 1 9 72-115262-00 LCD 15.4” TFT WXGA QD15TL01 QDI 1

10 50-UG8211-00 MYLAR LCD FRONT #8151 259IA1 2 11 50-UG6030-00 FRONT CAB #8151 259IA1 1 12 52-UG8030-00 RUBBER LCD UP #8155 259IA1 4 13 40-UG6025-10 HINGE+BKT LCD-L 15.4”(HONTECH)259IA1 1 14 29-UG8054-00 CABLE LCD 15.4” WXGA CMI 259IA1 1 15 41-720102-03 SCREW M2*3 I#0 D2.8~3.1 T0.3~0.4 NI 20 16 41-720525-06 SCREW M2.5*6 I#1 NI+NYLOK 6 17 41-721520-06 SCREW M2*6 ISOT #1 NI+NYLOK 2


3-7

4.1. System Disassembly Procedures…………………………………………… 3

4.2. LCD Display Panel Disassembly Procedure………………….…………... 11


4-2

4.1. System Disassembly Procedures

1. Please refer to the

disassembly procedures of the Nobile 159W

2. Unlock the battery knob

and pull out the battery pack.

3. Unfasten 6 screws and

remove the CPU and DDR cover.


4-3

4. Unfasten 1 screw and

remove the ODD.

5. Unfasten 5 screws.

6.

(a) Unlock CPU lock and remove CPU .

(b) Gently remove the DDR


4-4

7. Unfasten 1 screw of the

HDD cover.

8. Disconnect the HDD

casing to the HDD Connector to remove it.



4-5


11. Unlock 3 Latches of the

Keyboard.

12. Disconnect KB cable from

the connector.


4-6

13. Remove 2 hinge cover and

speaker cover.

14. Disable LCD cable.

15. Unfasten 4 screws from

LCD hinge.


4-7

16. Unlock LCD Knob and

gently remove LCD panel..

17. Gently remove Bottom

cover.

18. Disconnect USB cable.


4-8

22. Unplug speaker cable and

unfasten 2 hexnuts.

23.

(a)Remove 1 hexnuts and 2 screws .

(b)Unplug touch pad cable

and HDD cable. (c)Remove 4 cables

24. Remove 2 screws before

remove modem board


4-9

25. System Disassembly.


4-10

4.2 LCD Display disassembly procedure.

1. Remove the 6 rubber stoppers.


3. Gently remove the LCD Front

cabinet.


4-11

4. Unfsaten 12 screws.

5. Disconnect LCD cable from the inverter board and remove the LCD from LCD back cabinet

6. Unfasten 8 screws and remove

left and right hinge.


4-12

7. Disconnect LCD connector and

remove LCD cable.

8. LCD display panel disassembly

finished.


4-13

5.1. CPU, RAM, HDD Installation…………………………………………… 3 5.2. Upgrade System & Keyboard BIOS…………..…………….…………... 8


5-2

5.1. CPU, RAM, HDD Installation Warning Notice For precautionary measures, please disconnect the AC adapter and remove the battery from the battery compartment while doing the installation procedure of the CPU, Memory & HDD. Procedure to remove the battery

Unlock the battery knob and pull out the battery pack.

A. CPU Installation Guide Important Notice The CPU thermal pad of the CPU fan heat sink (black color) is one time use only. Meaning that if you remove the CPU heat sink from the CPU, you must REPLACE the CPU thermal pad with a new thermal pad (black color). Clean any residue on the CPU and the CPU heat sink assembly before putting the new CPU thermal pad. Otherwise, there might be an overheat problem on the CPU.

1.Unfasten 6 screws and remove the CPU and DDR cover.


5-3

2.Unfasten 5 screws from CPU Fan cover and disconnect Fan cable from the connector.

3. Align the pin 1 of CPU with pin 1 of CPU socket and gently put the CPU into the CPU socket.

4. Fasten the CPU Lock clockwise.


5-4

5. Fasten 5 screws from CPU Fan cover and connect Fan cable from the connector.

6. Put CPU and DDR cover then fasten 6 screws.


5-5

B. HDD Installation Guide

1. Fasten 4 screws of HDD module.

2. Unfasten 1 screw of the HDD cover.

3. Push the HDD casing into the HDD connector.


5-6

4. Fasten 1 screw of the HDD cover.


5-7

C. DDR Module Installation Guide.

1. Unfasten 6 srews of the CPU and DDR cover.

2. Put the DDR Module to the DDR socket.

3. Fasten 6 srews of the CPU and DDR cover.


5-8

5.2. Upgrade the BIOS Important Notice The utility only support at real mode (DOS mode), can not run at the protected mode (Window Mode). Do make sure that the system boot from real mode and plug AC power when to update the BIOS or install the utility. BIOS Update Procedure The F82745EXE utility is used to flash the system ROM and upgrade the BIOS. 1. Make sure the AC adapter is connected to your notebook before you run this utility. 2. Please make a clean Boot Disk which has no config.sys and autoexec.bat files. 3. Boot from Floppy disk, enter DOS prompt. 4. Type DIR 5. Please make sure the diskette has the following files : F82745EXE and xxxx.xxx (Bios Filename) 6. Start to update the system BIOS, AC power must plug into unit. Type A:\F82745 xxxx.xxx 7. Press Enter. After updating the bios, please go to BIOS setup and load DEFAULT setting. The system reboots automatically after installation is complete.


5-9

Trouble Shooting List 6.1 No display 6.2 VGA controller failure 6.3 LCD no display / Invalid picture 6.4 External monitor has no display or color incorrect 6.5 Memory test error 6.6 Keyboard test error 6.7 Touch pad test error 6.8 Memory Card bus Failure 6.9 Hard disk drive test error 6.10 CMOS test error 6.11 IEEE 1394 Failure 6.12 Card read port test error 6.13 Audio failure 6.14 No power symptom 6.15 CD ROM drive test error 6.16 Stopping in LCD screen while booting 6.17 PCMCIA Card Bus failure 6.18 Modem Failure 6.19 LAN Failure 6.20 TV OUT Failure


6-2

CPU OK??

DDR RAM module ok? Replace DDR module

Replace CPU

Correct it

6.1 No display (system failure)

Symptom: There is no display on both LCD and Monitor after power on although the LCD and Monitor are known-good.

No Display

Monitor or LCD module ok? Replace monitor or LCD

Display Ok?

Replace motherboard

NO

Yes

Yes

No

Yes

Yes

NO

NO

Yes


6-3

VGA Controller Failure

Try reinstall VGA driver in Windows XP

Correct it Retest ok??

Detect Display Adapter?

Replace MotherboardScreen distortion?

Replace Motherboard

Check Memory Size

Replace Motherboard

Correct it

6.2 VGA controller failure

Symptom: There is no display or distortion on both LCD and Monitor although Power-On-Self-Test is passed

Yes

No

No

No

Yes

Yes

No

Yes


6-4

6.3 LCD no display or Invalid Picture

Symptom: The LCD shows nothing or abnormal picture, but it is ok for external monitor.

LCD No Display

Try another known good LCD module

Display OK?

No

Yes Replace each parts of LCD module / cables and test

Replace motherboard


6-5

6.4 External monitor has no display or color abnormal

Symptom: The CRT monitor shows nothing or abnormal color, but it is ok for LCD

Monitor No Display

Try another known good monitor

Replace faulty monitor

Correct it

Display Ok?

Setup Ok?

Replace motherboard

No

Yes

No

Yes


6-6

Memory test error

Try another known good DRAM module

Test OK? Replace the faulty DRAM module

Replace motherboard

6.5 Memory test error

No

Yes


6-7

6.6 Keyboard test error (including external K/B & PS/2 mouse)

Symptom: error message of keyboard failure is shown or any key doesn’t work

Keyboard test error

Is K/B cable connected to

M/B properly? Connect or Replace K/B cable

Try another good keyboard

Test Ok? Replace the faulty keyboard

Replace motherboard

No

No

Yes

Yes


6-8

1. Check Touch pad device in Windows XP if it is properly Installed (including driver)

2. Check cable connected properly

6.7 Touch Pad test error

Symptom: An error message is shown when the Touch Pad point is enabled

Touch pad error

Try another known good touch pad module and cable

Test Ok ? Replace the faulty parts

Replace motherboard

Yes

No


6-9

6.8 Memory Card Bus failure

Symptom: When insert Memory Stick can’t detect Device with removable storage.

Correct it Test Ok??

Replace Motherboard

Yes

No

1.Check Memory Card Bus Device in Windows XP if it is properly installed(including driver) 2.Try Reinsert Memory Stick

Memory Card Bus failure


6-10

6.9 Hard disk drive test error

Symptom: Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to Hard disk

Hard disk test error

Replace the faulty parts Re-boot ok?

Replace motherboard

Yes

No

Try another known good HDD

Check BIOS Setup OK?

Correct itYes

No


6-11

6.10 CMOS test error 1. CMOS data lost, or inaccurate system time & data

No

CMOS test error

1. Plug in AC adapter, power on the system and set correct data in BIOS setup 2. Replace CMOS Battery 3. Turn off power for 1 hour then turn on again

Re-boot OK? END

Replace motherboard

Yes


6-12

6.11 IEEE 1394 Failure

Symptom: When backup HDD using IEEE 1394 can’t detect the device..

IEEE 1394 Failure

Re-test Ok? Correct it

Replace Motherboard

Yes

No

1. Check IEEE 1394 device in Windows XP if it is properly installed (including driver)

2. Try another backup HDD using IEEE 1394 device


6-13

6.12 Card read port test error

Symptom: Can’t get this card read

Card read fail

1. check whether driver are installed properly 2. try another working Card read

Correct itRe-test OK?

Setup OK? Correct it

Replace motherboard

Yes

Yes

No

No


6-14

6.13 Audio failure Symptom: No sound from speaker after audio drive is installed.

Audio test error

1. check whether cables, speakers & audio drivers are installed properly 2. try another working speaker & cable

Correct it Re-test ok?

Setup ok?

Replace motherboard

Yes

No

No

Yes

Correct it


6-15

6.14 No power symptom:

Symptom: When the power button is pressed, nothing happens, power indicator is not light up.

Correct it

Check Adapter is good

Replace Bios ok?

No Power

Yes

No

Replace motherboard


6-16

6.15 CD-ROM drive test error

An error message is shown when reading data from CD-ROM drive

CD-ROM driver test error

Replace the faulty parts Re-boot ok?

Replace motherboard

Yes

No

Try another known good CD-ROM

Check BIOS Setup OK?

Correct itYes

No


6-17

Correct it

6.16 Stopping in LCD screen while booting

Replace Bios ok?

Yes

No

Yes

Replace Motherboard

Stop in LCD Screen while booting

1.Try another known good CD-ROM 2. Try another known good HDD 3. Try another known good CPU 4.. Thermal modle deformation


6-18

6.17 PCMCIA Card Bus failure

Symptom : when insert PCMCIA card to PCMCIA slot, but system can’t

detect.

PCMCIA card failure

Insert PCMCIA card completely again, make sure good connection.

Check drive & controller install OK?

Correct it

Replace Motherboard

Yes

No


6-19

6.18 Modem failure

Modem Failure

Check Driver install & Telephone Line is OK?

Replace another known good Modem

board

Replace Motherboard

Correct it

Correct it

No

Yes

Yes

No


6-20

6.19 LAN failure

Symptom: When cannot detect Network Adapter device and can’t enter internet.

Correct itRe-test Ok??

Replace Motherboard

Yes

No

1. Check Network Adapter Device in Windows XP if it is properly Installed (including driver)

2. Setup Network Connections in Windows XP 3. Reinsert LAN cable.

LAN failure


6-21

6.20 TV Out failure

Correct it Re-test Ok??

Replace Motherboard

Yes

No

2. Check Display adapter Device in Windows XP if it is properly installed(including driver)

3. Check S-Vedio cable if is properly insert TV 4. Setup display properties to select TV in Windows XP

TV Out failure


6-22

w w w. p r e s t i g i o . c o m

prestigio 159w

Documents