primace user guideapplication platform on chip) system design and the fpga design. it offers a...

May. 2014

Capital Microelectronics Co., Ltd.

Primace User Guide

Applies to：CME-M5/HR Family FPGA

Version: CME-PUGE03

Primace User Guide II

The information in this document has been carefully checked and is believed to be entirely reliable. However, no

responsibility is assumed for inaccuracies. Furthermore, Capital Microelectronics Co., Ltd. reserves the right to

discontinue or make changes, without prior notice, to any products herein to improve reliability, function, or

design. Capital Microelectronics, Co., Ltd. advises its customers to obtain the latest version of the relevant

information to verify, before placing orders, that the information being relied upon is current.

Copyright © 2014 Capital Microelectronics Co., Ltd. All rights reserved. No part of this document may be copied,

transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any

form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the

written permission of Capital Microelectronics Co., Ltd. All trademarks are the property of their respective

companies.

Revision History

Primace User Guide III

Revision History

Date Primace Version

Documentation Version

Revisions

July. 2012 Primace 4.0 Version 1.0 Initial Release

Oct. 2012 Primace 4.1 Version 1.1 Uniform the naming rules relates to this book.

Apr. 2013 Primace 4.2 Version 1.2 Optimize and update the Wizard function. Add the iXplorer option. Update some images.

July. 2013 Primace 5 CMEPUG01

Add and optimize the Timing function (Timing sdc and Timing Constraint)

Fix bugs and update all captured pictures in the manual.

Sep. 2013 Primace5.0.1 CME-P5UGE02

Update the interface of the IP Wizard Manger (see the second figure in Page19):

UART IP upgrade to Version 2.1; MAC IP upgrade to version 2.0; release USB2.0 Device IP

May. 2014 Primace6.0 CME-PUGE03 Support CME-HR3 engineer sample; Update the section of Timing Analysis; Update the section of Signal monitor;

Table of Contents

Primace User Guide IV

Table of Contents

Revision History ...................................................................................................................................... III

Table of Contents .................................................................................................................................... IV

Getting Started.......................................................................................................................................... 1

Primace Overview ............................................................................................................................... 1

System Requirements ......................................................................................................................... 1

Supported Devices .............................................................................................................................. 1

Installing and Uninstalling ................................................................................................................... 1

Getting Documentation Resources ..................................................................................................... 2

Getting Technical Support .................................................................................................................. 2

Start Primace ...................................................................................................................................... 2

Customizing Environment ................................................................................................................... 2

EDA Tools Page ............................................................................................................................... 3

External Editors ................................................................................................................................ 3

Text Editor Page ............................................................................................................................... 3

I/O Editor Page ................................................................................................................................. 4

Netlist Viewer Page .......................................................................................................................... 4

Design Flow .............................................................................................................................................. 5

Introduction.......................................................................................................................................... 5

Graphical User Interface Design Flow ................................................................................................ 6

Command-Line Executable ................................................................................................................. 7

Design Entry ............................................................................................................................................. 8

Project ................................................................................................................................................. 8

Creating a Project ............................................................................................................................. 8

Project Management ........................................................................................................................ 9

Creating a Design ............................................................................................................................. 11

Using the Primace Text Editor ........................................................................................................ 11

Text Editor Setting .......................................................................................................................... 12

Using RTL Template ....................................................................................................................... 15

Wizard Manager ................................................................................................................................ 16

Using Wizard Manager ................................................................................................................... 16

Constraint Entry ................................................................................................................................ 18

I/O Editor ......................................................................................................................................... 18

The Options Dialog Box.................................................................................................................. 25

Synthesis ................................................................................................................................................. 28

Introduction........................................................................................................................................ 28

Using Primace Synthesis .................................................................................................................. 28

Synthesis Options ........................................................................................................................... 28

Analyzing Synthesis Results ............................................................................................................. 31

Placement and Routing ......................................................................................................................... 32

Introduction........................................................................................................................................ 32

Using Primace P&R .......................................................................................................................... 33

Analyzing P&R Results ..................................................................................................................... 33

Optimizing the P&R ........................................................................................................................... 33

Table of Contents

Primace User Guide V

Timing Analysis ...................................................................................................................................... 35

Introduction........................................................................................................................................ 35

Timing analysis tools ......................................................................................................................... 35

To configure Prime Time ................................................................................................................... 35

To Specify the Timing Constraint ...................................................................................................... 36

Timing Constraint ........................................................................................................................... 37

Run Primace Timing Analysis ........................................................................................................... 44

Viewing Timing Report ................................................................................................................... 44

Cross Probe ...................................................................................................................................... 56

Viewing Timing Delays with Netlist Viewer .................................................................................... 56

Viewing Timing Delays with Chip Editor ......................................................................................... 56

Simultaion ............................................................................................................................................... 57

Introduction........................................................................................................................................ 57

Using Third-party Simulation Tools ................................................................................................... 57

Bitstream Generation and Download ................................................................................................... 59

Introduction........................................................................................................................................ 59

Generating Bitstream File ................................................................................................................. 59

Bitgen Options ................................................................................................................................ 59

Downloading ..................................................................................................................................... 61

To Make Connections between PC and Device ............................................................................ 61

To Download a Configuration File to Device .................................................................................. 62

Common Errors and Solutions ....................................................................................................... 64

Debugging and Optimization ................................................................................................................ 65

Introduction........................................................................................................................................ 65

Console window ................................................................................................................................ 65

Design Report ................................................................................................................................... 66

Netlist Viewer .................................................................................................................................... 67

Viewing Netlist in Single/Multiple page mode ................................................................................ 68

Viewing Property of Cells (Instance, net or port) ........................................................................... 68

Using Goto to Reach a Specified Page .......................................................................................... 68

Searching Resources you need ..................................................................................................... 69

Filtering and Tracing Nets .............................................................................................................. 69

Showing a Critical Path .................................................................................................................. 71

Specifying Options of Netlist Viewer .............................................................................................. 71

Chip Editor......................................................................................................................................... 72

Invoke Chip Editor .......................................................................................................................... 72

Windows of Chip Editor .................................................................................................................. 73

Cross Probing ................................................................................................................................... 80

Locating port ................................................................................................................................... 80

Locating Net .................................................................................................................................... 81

Locating Instance ........................................................................................................................... 81

Signal monitor ................................................................................................................................... 82

Flow ................................................................................................................................................ 82

Invoke signal monitor assigner ....................................................................................................... 83

Windows of Signal Monitor Assigner .............................................................................................. 83

iXplorer .............................................................................................................................................. 85

Ixplorer Setup ................................................................................................................................. 86

Table of Contents

Primace User Guide VI

Run iXplorer .................................................................................................................................... 87

To View the iXplorer Results .......................................................................................................... 87

Debugware ........................................................................................................................................ 88

Flow ................................................................................................................................................ 88

Using IP wizard to generate debug IP ............................................................................................ 89

Specifying and Running the JTAG Server ..................................................................................... 91

Using Debugware to debug the project .......................................................................................... 92

Keil Debugger ................................................................................................................................... 94

EDA Tool Support .................................................................................................................................. 95

Introduction........................................................................................................................................ 95

Simulation Tools ................................................................................................................................ 95

To Configure ModelSim Environment ............................................................................................ 95

RTL Simulation ............................................................................................................................... 96

Timing Simulation ........................................................................................................................... 96

Timing Analysis Tools ....................................................................................................................... 97

Appendix I: Design Example ................................................................................................................. 98

Preparing for this Lesson .................................................................................................................. 98

Create a Project ................................................................................................................................ 98

Create design files with Text Editor ................................................................................................ 100

Define System with Wizard Manager .............................................................................................. 100

Make an Embedded System Design .............................................................................................. 100

Specify initial design constraints ..................................................................................................... 100

Run Synthesis ................................................................................................................................. 100

Perform a functional simulation with an EDA simulation tool ......................................................... 101

Assign I/Os in I/O Editor .................................................................................................................. 101

Place/Route the design and Analyze result .................................................................................... 102

Analyze the timing ........................................................................................................................... 102

Perform timing simulation ............................................................................................................... 102

Debugging and Optimizing .............................................................................................................. 102

Create programming files and program the device ........................................................................ 102

Keil Debug ....................................................................................................................................... 103

Getting Started

Primace User Guide 1

Getting Started

Chapter 1 User Guide

Primace Overview

Primace provides powerful and flexible EDA tools to support the whole process of CAP (Configurable

Application Platform on chip) system design and the FPGA design. It offers a variety of Intellectual

Property (IP) cores that assist users to carry out different applications in distinctive fields as well as

accelerate the release of products.

Besides, Primace supports third-party design tools with friendly and easy-to-use Graphic User Interface

(GUI).

System Requirements

Primace works on Windows XP (SP3), Windows Vista and Windows 7. You must have a minimum of

1.3GB space on your system for the software running.

Supported Devices

Primace6 version supports either M5 or HR family devices. Please refer to datasheet for further details.

Installing and Uninstalling

To install the Primace,

Please double-click the Primace_setup.exe in the Primace CD, and follow the installation wizard to

complete installation. For the detailed steps, please refer to the Primace Installation Guide.

To Remove the Primace from your PC, please:

Click Start > All Programs > Capital Micro > Primace > Uninstall Primace,

Or

Go to the Control Panel, open Add/Remove Programs, and then select Primace to remove it.

Getting Started


CAUTION

The USB driver Cannot be removed together with the Primace from the pc upon the above-

mentioned methods. So please go to the System Explorer of your pc and reinstall the USB driver

separately if required. For the detailed information, please refer to the Primace Installation Guide.

Getting Documentation Resources

Primace includes a browser-based Help system that provides help documentation for Primace software.

You can view Help by clicking Help->Help menu of Primace.

Besides, you can find all the available documentation resources in the Doc folder of your received

Primace CD.

Getting Technical Support

If you have trouble with running Primace or encounter problems during design process, you may take

the following steps to troubleshoot it yourself first:

1) Check whether the system running on Primace meets the System Requirements, Licensing &

Technical Support.

2) Check the configuration of your design compilation. Make sure all the settings are allowed. For

more information, see The Options Dialog Box.

If the problem still persists, you can report it to Capital Micro Support ([email protected]) with

the following information:

Describe the precise steps leading to the problem.

Send us the log file (agateflow.log), which is located in the outputs folder of your project.

Send us the design file you are working with if necessary. In order to solve the technical issues that you

have reported, we need to reproduce your working environment so that we can recreate and analyze

the problem.

Start Primace

Use one of the following ways to start Primace:

Double click the Primace icon on your desktop.

Click Start > All Programs > Capital Micro > Primace

Customizing Environment

Getting Started


Choose Tools > Options to enter the Primace setup dialog, see figure below. From which, you may

setup the EDA tools, external editor, text editor, IO editor and Netlist viewer.

EDA Tools Page

The EDA Tools Page provides an access for users to specify a simulation tool and activate the software

by entering the obtained license number. For further details, see EDA Tool Support.

External Editors

This page enables users to load external editors. Primace does not only supports external editors, but

also has the function to name external editors.

Text Editor Page

Text Editor is a tool used to view, create, or modify text-based designs. You can pre-define its working

environment so that you can work with it in your favorite mode. Options of Primace provide you with text

Getting Started


editor to work faster and conveniently and save time on designing. For future details, see Using the

Primace Text Editor.

I/O Editor Page

I/O Editor is a tool used to assign I/O signals (ports) to I/O pins on Capital Micro device. It offers

different choices for color defining of different pins. For more details, see I/O Editor.

Netlist Viewer Page

Netlist Viewer provides different levels schematic view of your design and a hierarchy list, which lists

the instances, pins, and nets for the entire design Netlist. It helps you check the design. This page

offers choices for Netlist display. Port names, pin names, instance names, and other choices are

available. Please refer to Netlist Viewer for further details.

Design Flow


Design Flow


Introduction

Primace provides a complete design suite for CME CAP design. You can perform the design flow by

graphical user interface or command-line interface.

Primace Design Flow

See the diagram above, please firstly create a design based the IPs supported by the Primace.

Please note that you can decide whether to use a third-party tool to simulate or verify the design finished before you

move into the next step.

Second, perform the design flow in the order of synthesis, placement and routing, Bitstream

generating and download, and please note that:

Before or after the synthesis and placement/routing, you can perform either the timing analysis or the

debugging/optimizing until you satisfy the results.

After the design is loaded into the chip, you can still debug the design on-chip by using the third-party tool Keil or

rerun the whole process until the design meets the requirement.

Design Flow


Graphical User Interface Design Flow

The Primace offers a modular Compiler that is composed of the following modules:

Synthesis

Placement and Routing

Bitstream Generation and Download

Timing Analysis

You can run the whole flow by clicking Flow > Run Project, or run each flow step by step from Flow

menu.

The following steps describe the basic design flow using the Primace GUI

1) To create a new project and specify a target device, click Project > New Project.

For further details, refer to Creating a project.

2) Use the Text Editor to create source files, both VHDL and Verilog HDL is supported. Then add the

created source file into the project, or add exiting source files into the project.

For further details, refer to Creating a Design.

3) Use the Wizard Manager to generate and instantiate IP cores (such as 8051, EMB, MAC and etc.).

For further details, refer to Wizard Manager.

4) Specify initial design constraints with the Settings dialog box, including Project settings and EDA

tools.

For further details, refer to The Options Dialog Box.

5) Synthesize the design by clicking Flow-> Run Synthesis, analyze result with netlist viewer.

For further details, refer to Synthesis.

6) Perform a functional simulation with third-party simulation tool.

For further details, refer to Simulation Tools.

7) Assign I/Os in the I/O Editor.

For further details, refer to I/O Editor.

8) Run Placement by clicking Flow-> Run Placement and Routing by clicking Flow-> Run Routing,

analyze the result from design reports and log files.

For further details, refer to Placement and Routing.

Design Flow


9) Analyze the timing by clicking Flow-> Run Timing Analysis.

For further details, refer to Timing Analysis.

10) (Optional) Use a simulation tool to perform timing simulation for the design, and debug the design

with Netlist Viewer, Signal Monitor tool and Debugware too.

For further details, refer to Simultaion and Debugging and Optimization.

11) (Optional) Do manual placement in the Chip Editor to correct timing problems.

12) Create programmable Bitstream files for the design by clicking Flow-> Run Bitgen, then program

the device by clicking Tools -> Downloader.

For the details, refer to Bitstream Generation and Download.

13) Debug 8051 with Keil.

For further details, refer to Downloading.

Command-Line Executable

Using command lines is another method to run flows. In addition, this method can help you control

Primace to run a flow flexibly. You can either click Start > All Programs > Capital Micro > Primace >

Command Line or click Tools > Command-Line Window to launch it.

Design Entry


Design Entry


Primace project includes all of the design files, software source files, and other related files necessary

for the eventual implementation of a design in a programmable logic device. You can use Text Editor,

Wizard Manager to create design files that include CME intellectual property (IP) functions or add

existing VHDL files designed by third-party tools.

See the Design Entry Flow below.

Text EditorCME IP design files generated by Wizards (.v, .vhd)

Verilog HDL ＆ VHDL　design files (.v, vhd)

Wizard Manager

Third-party Editors

Design files generated by third-party editors (.v, .vhd)

To Primace Synthesis tool

To third-party Syntheis tool

Project

Creating a Project

Operation: Project - New Project, or click on the toolbar.

Design Entry


Please follow the steps below to create a new project.

1) Specify a location for saving your project.

2) Input a name for your project and top module.

3) Add the design files you required if have. The Primace at present allows both Verilog HDL

and VHDL format files.

NOTE

A special character for example * and white space characters and Chinese

characters should not be used for your project directory, project name and

file/folder name or else errors may occur during the follow running.

Project Management

Project Settings Specification

When a project created, you can manage the project options with the Project Settings dialog shown in

following figure. You can use one of the following ways to open Project Settings dialog box:

Click on the toolbar.

Click Project > Project Settings on the menu bar.

Design Entry


Click Tools > Options on the menu bar.

On the General page of Options dialog box, top module of the current project, and include file path are

shown as well as changeable.

Note: We suggest users not put your files under outputs directory at the current step, accidental

deletion may happen when cleaning flow results.

On the Device page of Options dialog box which is shown below. You can use the filter to select the

device.

To Set the Top Module

If you want to set a module as top module of a project, you can do it in two ways as follow:

“Set As Top Module” menu

In Project Explore Window, right click the mouse on a module and select Set As Top Module

from the pop-up options.

Design Entry


“Options” Dialog

Click Tools in Menu bar > Options> Project, you can input Top Module Name, case sensitive.

Creating a Design

You can create designs in Primace Text Editor. Primace also supports VHDL designs created from files

generated by third-party EDA tools.

Using the Primace Text Editor

Text Editor is a text-based tool that is used to view, create, and edit designs in Verilog HDL or VHDL. It

supports different character encoding modes including UTF-8, GB2312, and Big5. You can change the

coding mode by Edit-> Character Encoding.

In addition, it can view output files generated by Primace.

Besides, the Text Editor adds a RTL template, for the details please refer to Using RTL Template.

To create a design in Text Editor:

Method 1:

Select the project in Project Explorer, right-click the mouse and select Add New File. The file is

automatically added into the project as source file. You can create design in Verilog HDL or VHDL in

Text Editor.

Method 2:

1) Click File > New Text File on the menu bar or button.

2) Enter source code in Text Editor.

3) Click File > Save to save the file in Verilog HDL (..\src folder is suggested) and add this file

into the current project (see below).

Design Entry


To add a design file to the project

Select the project name in Project Explorer and right-click, select Add Existing File.

To use existing design files

If design files generated by third-party tools need to be used as source file in the project, or you want to

use existing design files created before, please follow the steps below:

Add these design files into the project by clicking Add Existing File.

1) Select the project name in Project Explorer and right-click, select Add Existing File.

2) In Open Files dialog box, browse and select the file you want to add, and then click Open to

add the existing file.

In fact, the file you add as an existing file will still be saved in its current path instead of copied to the

src path of the project. This makes easier to share files between different projects or tools. If you want

to move these files to the project src path, you can copy these files to the project src path first, then add

them into the project.

Text Editor Setting

When you create a design using text editor, you can customize your own working environment of text

editor. Click Tools > Options on the menu bar, and click Text Editor on the left list. See the figure as

follow.

Design Entry


Fonts and Colors

Font and color shown in text editor can be defined in this page. Font sample is visible in

whitespace while setting.

Design Entry


Templates

You can choose to comprehend or edit templates written in a certain languages here. Certain

default templates written in Verilog HDL are available to use.

Design Entry


Using RTL Template

The Primace provides multiple RTL templates for users to be inserted into the design file being used in

Text Editor in order to avoid duplication of effort. Besides, users can create a desired template through

this module or modify the supplied templates according to demand.

To use the RTL Template, please: right click the mouse on the location where you want to insert a

template and select Insert Template.

Design Entry


Wizard Manager

Wizard Manager offers a friendly graphic user interface to use complex high level embedded IP cores.

With Wizard Manager, you can instantiate IPs according to your application requirements and modify

which you have instantiated.

CAUTION

Before perform customizing, please make sure you are familiar with the properties of IP. CME

provides related manuals for your reference:

About Hard IPs: go to your received installation package (DOC folder) and find the related

device datasheet

About Soft IPs: press Help button on the related Wizard interface to get the manual (for

example: click Tools - Wizard Manage - Next – choose I2C(v1) – Next – Help)

Using Wizard Manager

1) Click Tools > Wizard Manager on the menu bar, or directly click on the toolbar.

Design Entry


2) A Wizard Manager Dialog box appears. You can select to create a new design or edit an

existing design shown as the following figure.

3) After your selection, click Next button to continue following steps. You can see the second page

of Wizard Manager.

Design Entry


Tips

Primace supports multi-IP cores, to get the related documentation resources, please

Refer to the related Guide (such as Data Sheet) or

Press Help button on the main interface of the software and choose the documentation you

required or

Press Help button after you enter the setting page (Press Next>) or

Go the Primace installation folder: \data\ip\ip_core (the default directory if no changes made)

Constraint Entry

During you run flows for the design, you can use the I/O Editor and the option dialog box to specify

design constraints, such as device options, logic flow options, physical flow options, IO assignments

and timing constraints.

The figure of Constraint Entry is shown as below.

Setting Dialog Box

IO Editor

Primace Project File(.apj)

Synopsis Design Constraint file(.sdc)

Constraint file(.aoc)

To Primace flows

I/O Editor

IO Editor displays the IO pin arrangement from all available packages through a graphic interface. It

allows users do I/O assignment. You can either specify a location for a port or modify the I/O attributes

to meet your requirements. However, please note that this function is disable until you run synthesis.

The I/O arrangement information is stored in an .aoc file that is initially created during the synthesis

process.

Tips

The .aoc file is upgraded from version 2.2 to 2.3. For M7 device, it adds two constraints:

pairedIoConstraint and <dedicatedIo> but no longer provide the default properties <ioCommon

driving_strength="4ma" fast_din="false"

Design Entry


Color Setup of I/O Editor

To modify the displayed pin colors, please click Tools > Options > I/O Editor, or directly click on

the toolbar.

Invoke I/O Editor

To start the I/O Editor, choose one way from the followings:

a) Choose Tools -> IO Editor (Ctrl + Alt + I) or click on the Toolbar.

b) Go to the Project view (click the icon below the Project), right click the mouse on the .aoc file

under the tmp folder and choose Open with -> IO Editor, see figure below.

Design Entry


Tool Buttons of I/O Editor

The I/O Editor supplies the following buttons to give you an assistance during the assignment.

Icon Function Description

Zoom In Enlarge the whole package view proportionately.

Zoom Out

Scale down the whole package view proportionately. It is useful while the package view is enlarged.

Batch Insert

Assign the ports with more than one at a time in the Table Mode.

Turn to Top/Bottom View

Switch between the top and bottom view of the package.

IOBank View

Switch to the bank information view.

It this mode, the pins belongs to a same IO Bank are shown under a same background color. Please note that ports within a same bank must work under a same voltage level.

Bird’s-eye View Invoke a scaled down package view in order to quickly go to the desired region while the package view is enlarged.

Design Entry


Drag to Zoom In Enlarge the selected package regions by dragging the mouse proportionately.

Hand Tool

Go to the desired package region with shown. It is useful while the package window is enlarged. In this state, you can assign or reassign ports only through the Table Mode.

Fit to Window

Scale the package view in order to display the whole information of ports.

Show Legend Recall the list that is showing all types of pin legends.

Show P-N Pairs

Show the ports with pair information.

It means that all the paired port would be specially indicated by

a connection line, such as .

Windows of I/O Editor

The interface contains of four parts: the Unassigned Port window (herein after referred as Unassigned

window), Assigned Port window (herein after referred as Assigned window), Port Attributes Table

window (herein after referred as Table window) and Main Graphic Package window (herein after

referred as Package window). The next part introduces each of the window.

Design Entry


Unassigned Port window (Unassigned window)

The window lists all the ports to be assigned. For the detailed assignment, please refer to Assigning I/O.

Besides, you can locate the ports in this window into the other view components (right click the mouse

on an assigned port, click Locate, and choose the desired view component from the pop-up menu).

Assigned Port window (Assigned window)

The window lists all the assigned ports. You can either locate one or more ports into the other view

components or reassign the ports. For the method, please refer to Assigning I/O.

Port Attributes Table window (Table window)

This table shows the port and pin attributes. You can setup the port attribute, assign or reassign the

port through this table. For the method, please refer to the Table Mode section.

Main Graphic Package window (Package window)

The window visualizes the device package. You can view the pin arrangement and do assignment.

Assigning I/O

There are two methods to assign I/O: Graphical Mode and Table Mode.

Graphical Mode

Take the following steps to assign a port to a pin:

1) Open the I/O Editor by clicking Tools > IO Editor on the menu bar.

2) Assign the ports directly as requirements (select one or more ports from the Unassigned

Ports list, hold your mouse and drag them to the desired location). The Zoom in/out buttons

( , or press and hold the Ctrl button on your PC keyboard and slid up/down the mouse

wheel) under the Edit menu (toolbar) in this moment are available.

Tips

You can also simply press F3 to use the function of “Find next”. Left-click the mouse, roll the

scrolling wheel of the mouse, and at the same time press Ctrl, you can change the height and

length of your view.

If you release the mouse pointer in the blanks during the assignment, the pointer may

changes to “+” which indicates that there are still some signals need to be assigned, see

figures below.

Design Entry


While the mouse pointer is hovered on a pin, a tip information may occurred to prompt you the port

status: green characters indicate that the location is assignable and red characters indicates that this

pin cannot be assigned (see figures below).

Before Assignment (Allowable) After Assignment

Design Entry


Before Assignent (Disable)

3) When finished, click the on the toolbar.

Tips

If you want to view the port assigned through the package window, click a port name in the

Assigned window, you will find this port is highlighted.

Table Mode

The table contains the information relates to the ports, from which you can directly assign or reassign

the port by setting the port attributes.

CAUTION

The ports within a same bank must be specified with a same voltage level.

The available range of the drive strength varies with the IO standard.

Un-assigning I/O

To un-assign I/O, choose one of the following ways:

In the Assigned window, choose the port to be deleted and press the Delete key directly.

In the Assigned window, choose the port to be deleted and drag it into the Unassigned window.

Select the pin under a colored background in the Package window and press Delete key.

Design Entry


Reassigning I/O

To reassign I/O, follow the two steps below:

In the Assigned window, choose the port to reassigned and move it into the location desired in

the Package window.

In the Package window, choose directly the port to be reassigned and move it into the desired

location.

In the Table window, change the port attribute directly.

Configuring I/O Properties

IO properties can help reserve I/O for monitored signal：

IO Alias

Specify an alias for an IO.

Assign Port

Show the assigned port name.

Reserved IO

When checked, this IO cannot be assigned and is only for the specific purpose.

The Options Dialog Box

You can use the Options dialog box to specify general project settings and synthesis, bitstream, timing

analysis and EDA tool settings for a project. Click Tools > Options or directly click the on the

toolbar to open the Options dialog box.

Specify project General settings

Design Entry


In the General page of Options dialog box, you can view or change top module of the current project

and include file path. See figure below.

Specify project Device settings

In the General page of Options dialog box, you can view or change target device. See the dialog box

below.

Design Entry


Specify Synthesis settings

In the Logic Flow page, you can specify different synthesis options. For further details, refer to

Synthesis Options.

Specify Bitstream settings

In the Physical Flow page, you can specify Bitstream options. For further details, refer to BitGen

Options.

Specify Timing Constraints

In the Timing Constraint page, you can specify different timing constraints. For further details, refer to

Static Timing Analysis.

Synthesis


Synthesis


Introduction

After you create a project and design files, you need to synthesize your design (a functional simulation

is suggested before this action, please refer to Simultaion). Synthesis translates a use RTL to a post-

mapping Netlist.

Figure of Synthesis Flow.

Synthesis ast

Verilog design files (.v) VHDL design files ( vhd) Post-map netlist (.amv)

Primitive libraries

to Placement

Netlist viewer

Design EntryConstraint

Report file (.rpt)

Using Primace Synthesis

The synthesis module supports both Verilog HDL and VHDL languages.

To run the CME Synthesis, click Flow > Run Synthesis or you can run the whole design flow which

includes Synthesis by clicking Flow > Run Project.

Synthesis Options

The Logic Flow page in the Settings dialog box allows you to specify Netlist optimization options.

Synthesis


The following are details about synthesis options:

Optimization Goal

speed: optimizes the design for speed by reducing the level of logic, this is the default value.

balance: balance the delay and area during optimization

area: optimizes the design for area by reducing the total amount of logic used for design

implementation

Enable RAM Extraction

When checked, the synthesis process will auto infer the memory that match particular pattern in user

RTL to EMBs on CME Chips. The default is checked.

USE DSP Block

Choose the strategy of Synthesis Multiplier Inference. Alternatives include yes, auto and no. The

default is auto.

Pack I/O registers into DGPIO

Synthesis


When checked, the synthesis process will pack I/O registers into IO cell. The default is not checked.

Enable Advanced Timing Optimization

When checked, the synthesis process will use advanced timing optimization strategies to get a better

timing performance. The default is not checked.

Timing Estimation

When checked, the timing analysis of synthesis is going to be performed and which provides the early

imagine about the timing performance of user design. The default is no checked.

Enable Detailed Log Output

When checked, the synthesis will print detailed processing log file. The default is not checked.

By clicking Advance button in the Logic Flow page, you can open the Synthesis Advance Setting dialog

box.

The following are details about advance synthesis options:

RAM Extraction

Define the minimum address width of memory which auto infer to EMB5K cells.

Enable Carry Chain Optimization

CME Synthesis will use Carry Chain Optimization strategies if checked.

Enable Collapse Constant Adder

CME Synthesis will collapse the constant adder in user RTL if checked.

Synthesis


Enable Collapse Constant Comparator

CME Synthesis will collapse the constant comparator in user RTL if checked.

Collapse Adder If Width

Synthesis will flatten adder with width greater than specified value to combinational logics other than

using carry chain. The default is 6.

Minimum Clock Enable Fanout

Clock Enable which fanouts less than this value will be push to the input of register. This will help P&R

to produce an implementation result with better signal integrity.

Keep Hierarchy

If checked, the hierarchy name will be shown in post-mapping netlist. This can ease user to trace an

instance from implementation to RTL. Default is unchecked.

Analyzing Synthesis Results

Primace provides the following three methods to analyzing synthesis results: Message Window,

Synthesis Report and Netlist viewer.

For further details, refer to Debugging and Optimization.





Introduction

As the first step in physical design process, the task of placement is to calculate the positions of the

cells. Then the routing process assign signals to routing resources in order to successfully route all

signals while achieving a given overall performance.

Primace Placement takes a post-mapping netlist (.amv), a constraint file (.aoc) and libraries as input, to

determine the legal location of each element in the mapped netlist. It takes different constraints (IO

distribution, logic cell structures, clock/non-clock interconnects, resource capacity and special macro

blocks) in CME FPGAs into account. The output is a post-placement netlist file (.apv), a netlist

annotation file (.apx) and an annotated AOC file if using manual placement.

Primace Routing tool takes a post-placement netlist (.apv) and a netlist annotation file (.apx) as input,

to connect all signal paths using the available programmable interconnects on-chip. The output is a

post-routing netlist annotation file (.ara) and an annotated aoc file if using manual placement.

Primace P&R has powerful timing driven capability which enables to optimize the designs in the

direction constrained by users.

The Place and Route Design Flow is shown as figure below.

Placement

Post-map netlist (.amv)

Post-placement netlist (.apv)

libraries

to Bitstream generation, Timing Analysis,Netlist Viewer

Report file (.rpt)

Routing from Synthesis

from Design Entry

Post-routing netlist (.arv)

Placement Drc Routing Drc

Report file (.rpt)

to Netlist Viewer

libraries

If you have made IO assignments or manual placement in your design, the P&R attempts to match

those resource assignments with the resources on the device, tries to meet any other constraints you

have set, and then attempts to optimize the remaining logic in the design. If you have not set any

constraints on the design, the P&R automatically optimizes it. If it cannot find a resolution, the P&R

terminates compilation and issues an error message.



Using Primace P&R

Before running Placement, you must run synthesis successfully. You can run CME Placement and

Routing separately by clicking Flow > Run Placement and Flows > Run Routing or you can run the

whole design flow by clicking Flow > Run Project.

If you make changes to the design or design settings as needed, you need to run P&R again. For

information about running a whole flow, refer to “Graphical User Interface Design Flow”.

You can also use Command lines to run Placement or Routing separately after you finish the flow for

the project. The following commands are provided for your reference.

Run Placement by Command lines step by step:

1) cstool scripts/syn_gen_db.tcl

2) cstool scripts/fplan.tcl

3) cstool scripts/assigner_cstool.tcl

4) cstool scripts/refiner_new.tcl

5) cstool scripts/fixer.tcl

6) cstool scripts/fixer_drc.tcl

Run Router by Command lines step by step:

1) cstool scripts/pack.tcl

2) cstool scripts/route.tcl

Analyzing P&R Results

Primace provides the following three methods to analyzing P&R results: Message Window, P&R Report

and Netlist viewer.

If necessary, you can use Chip Editor to view P&R results and make adjustments. For further details,

refer to Debugging and Optimization.

Optimizing the P&R

Once you have run the P&R and have analyzed the results, you can optimize the result according to the

following methods:

Manual: adjust the placement manually by using Chip Editor

Manual placement is used to optimize P&R after running the whole flow. With manual placement,

you can directly drag the resource assignment to the target location. After that, run P&R again to

check the result. For more detail, refer to Debugging and Optimization.

Manual placement is at present not recommended.



Auto: adjust the related parameters, settings and timing constraints

Tips

If the result is lower than the expected frequency while running the flow under the default timing

constraint, please optimize the design, or change the timing constraint value and have a try. If the

result cannot be reached after several changes, please try to run the iXplorer for the expected

performance.

Timing Analysis


Timing Analysis


Introduction

Static Timing Analysis allows you to analyze the timing characteristics of your design. You can use the

information generated by the timing analyzer to analyze, debug, and validate the timing performance of

your design.

Timing analysis tools

Primace support two kinds of tools to do static timing analysis: Primace Timing Analysis and Prime

Time. The first is CME self-owned tool; the second is a third-party tool that users are supposed to

install it before doing any analysis.

Operation: Tools > Options > EDA, choose Primace Timing Analysis or Primace Time

CAUTION

The effect of fmax caused by different voltage

While the core voltage is varying between 0.9v and 1.3v, if the voltage rises 0.05v, fmax will rise

6.72% correspondingly. And when the temperature is varying from 25℃ to 85℃, fmax will decrease

5%.

To configure Prime Time

1) Click Tools > Options on the menu bar to open Options dialog box.

2) On the EDA Tools page, choose Prime Time in Timing Analysis Tool box.

3) In the Server Settings box, type the server name and user name.

Timing Analysis


4) Click OK.

To Specify the Timing Constraint

Timing Constraints Editor is a tool to create and edit timing constraints in the SDC (Synopsys Design

Constraints) format. Before using this module, you have to run synthesis first.

Operations:

To open the Timing Constraints Editors, you may use either or the following ways:

Tools > Timing Constraints Editor

Click on the Toolbar.

Right click the mouse on the .sdc file and select Open with -> Timing Constraints Editor

Double click the .sdc file in the Project Explorer.

The editor enables you to specify the timing constraints based on the existing .sdc file.

Timing Analysis


Timing Constraint

In Timing Constraints Editor, there are several tabs in which they are the types of constraint you can

specify (Figure below). In each tab, you can edit the constraint. If the constraints that you have

specified are invalid, the Timing Constraints Editor will display them in red color. In the following part,

we will introduce the usage of it.

Search for Pins/Ports in the design

(a) Smart Filter (b) Search Design

In the Timing Constraint Editor, you can search the design objects to which constraints are be applied

by the searching dialog as displayed in figure above. Double click on the appropriate filed in Timing

Constraint Editor, and a dialog named Smart Filter (figure a) will be popped up.

Timing Analysis


Smart Filter Dialog

The content of the dialog is content sensitive. Most possible objects will be listed. You can select

object from the list, or click “Search Design…” button to invoke Search Design dialog (figure b).

Search Design Dialog

In the dialog, you can select Port/Pin/Clock type in the Search options. Also, you can set some filters

for each searching. You can specify the search pattern to search for a specific port/clock/cell pins.

Wildcard is supported in search pattern. The “Search results” tree will list all the pin/port/cell which

meets the condition you have set. And then you should select an item in the result tree, and click OK

button.

Clock Constraint

To enter clock constraints, select the Clock tab in the Timing Constraints Editor. The following fields

are displayed under the “Clock” tab.

Enable

Use the Enable tab to enable or disable the constraint.

Name

Specify the name of clock being created.

Object

Specify the object used as the source of the clock. The source can be port or pin. Double click in

Object field will pop up searching dialog, as shown in figure above.

Period(ns)

Specify the clock period.

Frequency(MHz)

Enter the frequency in the field.

Comment

Associate a string describe with the command for tracking purposes.

Generated Clock Constraint

Timing Analysis


Creates a generated clock and defines its characteristics. To enter generated clock constraints, select

the Generated Clock tab in the Timing Constraints Editor. The following fields are displayed under the

Generated Clock tab:

Enable


Name

Specify the name of the generated clock.

Object

Specify the generated clock object.

Source

Specify the port or pin name from which the clock is derived.

Divide By

Specify the division factor. It is optional.

Multiply By

Specify the multiplication factor. It is optional.

Comment


Clock Latency constraint

Define the timing uncertainty between two clock waveforms or maximum skew. To enter clock

uncertainty constraints, select the Clock Uncertainty tab in the Timing Constraints Editor. The

following fields are displayed under the Clock Uncertainly tab:

Enable


Timing Analysis


Uncertainly(ns)

Specifies the clock uncertainty (skew characteristics) of specified clock network.

Object

Specifies a name of clocks, ports, and pins for which the clock uncertainty is to be set

Setup

Specify that the uncertainty apply only to setup checks. If you do not specify either option (-setup or

-hold) or if you specify both options, the uncertainty applies to both setup and hold checks.

Hold

Specify that the uncertainty apply only to hold checks. If you do not specify either option (-setup or

-hold) or if you specify both options, the uncertainty applies to both setup and hold checks.

Comment


Clock Uncertainty Constraint

Define the timing uncertainty between two clock waveforms or maximum skew. To enter clock

uncertainty constraints, select the “Clock Uncertainty” tab in the Timing Constraints Editor. The

following fields are displayed under the “Clock Uncertainly” tab:

Enable


Uncertainly(ns)

Specify that the clock-to-clock uncertainty applies to both rising and falling edges of the source

clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the

constraint to be valid. This option is the default.

Object

Specifies a name of clocks, ports, and pins for which the clock uncertainty is to be set

Setup

Specify that the uncertainty applies only to setup checks. If you do not specify either option (-setup

or -hold) or if you specify both options, the uncertainty applies to both setup and hold checks.

Hold

Timing Analysis


Specify that the uncertainty applies only to hold checks. If you do not specify either option (-setup

or -hold) or if you specify both options, the uncertainty applies to both setup and hold checks.

Comment


Input Delay Constraint

Define the arrival time of an input relative to a clock. To enter input delay constraints, select the “Input

Delay” tab in the Timing Constraints Editor. The following fields are displayed under the “Input Delay”

tab:

Enable


Port

Provide an input port in the current design to which delay value is assigned.

Delay(ns)

Specify the arrival time in nanoseconds that represents the amount of time for which the signal is

available at the specified input after a clock edge.

Clock

Specify the clock reference to which the specified input delay is related. This is a mandatory

argument. If you do not specify -max or -min options, the tool assumes the maximum and minimum

input delays to be equal.

Min

Specify that delay_value refers to the shortest path arriving at the specified input. If you do not

specify -max or -min options, the tool assumes maximum and minimum input delays to be equal.

Max

Specify that delay_value refers to the longest path arriving at the specified input. If you do not

specify -max or -min options, the tool assumes maximum and minimum input delays to be equal

Comment

Associate a string describe with the command for tracking purposes

Output Delay Constraint

Timing Analysis


Define the output delay of an output relative to a clock. To enter output delay constraints, select the

Output Delay tab in the Timing Constraints Editor. The following fields are displayed under the Output

Delay tab:

Enable


Port

Provide an output port in the current design to which delay value is assigned.

Delay(ns)

Specify the amount of time before a clock edge for which the signal is required. This represents a

combinational path delay to a register outside the current design plus the library setup time (for

maximum output delay) or hold time (for minimum output delay).

Clock

Specify the clock reference to which the specified output delay is related. This is a mandatory

argument. If you do not specify -max or -min options, the tool assumes the maximum and minimum

input delays to be equal.

Min

Specify that delay_value refers to the shortest path from the specified output. If you do not specify -

max or -min options, the tool assumes the maximum and minimum output delays to be equal.

Max

Specify that delay_value refers to the longest path from the specified output. If you do not specify -

max or -min options, the tool assumes the maximum and minimum output delays to be equal.

Comment


Max Delay Constraint

Specify the maximum delay for the timing paths. To enter max delay constraints, select the “Max Delay”

tab in the Timing Constraints Editor. The following fields are displayed under the “Max Delay” tab:

Timing Analysis


Enable

Use the Enable field to enable or disable the constraint.

Delay

Enter the delay value (non-negative number) in the field.

From:

Enter the source pin or port of the constrained path. The constraint is applied for the data paths

launched on both rising and falling transitions.

To

Enter destination pin or port, up to which the path is defined. The constraint is applied for the paths

captured on both rising and falling transitions.

Comment


False Path Constraint

Identify paths that are considered false and excluded from the timing analysis. To enter false path

constraints, select the “False Path” tab in the Timing Constraints Editor. The following fields are

displayed under the “False Path” tab:

Enable

Use the Enable field to enable or disable the constraint.

From

Specify a list of timing path starting points. A valid timing starting point is a clock, a primary input,

an inout port, or a clock pin of a sequential cell.

To

Specify a list of timing path ending points. A valid timing ending point is a clock, a primary output,

an inout port, or a data pin of a sequential cell.

Timing Analysis


Comment


Run Primace Timing Analysis

After configurations, you can click Tools > Timing Analysis or the icon on the menu bar to start this

timing analysis step.

Viewing Timing Report

The Timing Analysis contains two parts: the left part is a Table of Contents and the right part is the

details of each path in the table, as shown in following figure.

Timing Corner Settings

Besides you can specify the operation conditions of the device when you create a new project, you also

can specify it in Timing Analysis by click button on the upper left side of the

interface. If you want to reset it to the setting of current project, you can click .

Timing Analysis


Timing Constraints Report

In Timing Analysis, you can get the timing constraint detail information by click Timing Constraints

Report button in Table of Contents view, as shown in follow Figure. Here, you cannot modify the detail

information of the timing constraint. However, if you want to modify the timing constraint, you can edit it

with Timing Constraint Editor.

Compared with Timing Constraint Editor, a new column Location is added to each constraint tab. This

column has indicated the sdc command location in the *.sdc file.

If the sdc is generated automatically by Primace, you can add it to the project by click Add Auto Sdc to

Project. And the timing constraint file will be added to the project.

Clock Summary

Clock Setup Summary

Select Setup Summary item under Clock Summary and the Clock Setup Summary will be displayed in

Clock Setup Summary tab, as shown in follow figure.

Timing Analysis


This section gives the details of the computed frequency summaries and the frequency defining paths

for all clocks in the design. When a particular clock is selected, the paths corresponding to that clock,

and the path used for frequency computation, are displayed in the path summary pane.

1) Critical Path Summary

For each frequency defining path, the following fields are displayed in the Critical Path Summary.

Start Point

This indicates the pin at which the data path initiates.

End Point

This indicates the pin at which the data path ends.

Launch Clock

The clock and its polarity at which the data is launched.

Capture Clock

The clock and its polarity at which the data is captured.

Constraint

This constraint value indicates the constraint of the clock.

Data Arrival Time

Timing Analysis


This value is the data arrival time.

Data Required Time

This value is the data required time.

Clock Skew

The clock skew between the edges of the launch clock and the latch clock.

Data Delay

The delay of the path as computed by the sum of the logic and routing elements between the

Start and End Points.

Cell Delay %

This describes the percent of the cell delay in data path delay.

Routing Delay%

This describes the percent of the routing delay in this path

Slack

The slack value computed for the path.

2) Launch Path

This section displayed the detailed information of the launch path containing launch clock edge

time, clock path, and data path.

3) Capture Path

This section displayed the detailed information of the capture path containing capture clock edge

time, clock path and library hold time.

Right click in Clock Setup Summary tab, a menu is available. In the menu, you can select “Top 20 paths

by slack” item to show the top 20 paths by slack of all the paths, and select “All paths” item to show all

paths. And the result will be shown in a new tab. For example, if you select “Top 20 paths by slack” item,

the result is displayed as in follow figure.

Timing Analysis


Clock Hold Summary

1) Critical Path Summary

For each frequency defining path, the following fields are displayed in the Critical Path Summary.

Start Point:

This indicates the pin at which the data path initiates.

End Point:

This indicates the pin at which the data path ends.

Launch Clock:

The clock and its polarity at which the data is launched.

Capture Clock:

The clock and its polarity at which the data is captured.

Constraint:

This constraint value indicates the constraint of the clock.

Data Arrival Time:

This value is the data arrival time.

Data Required Time:

This value is the data required time.

Clock Skew:

The clock skew between the edges of the launch clock and the latch clock.

Timing Analysis


Data Delay:

The delay of the path as computed by the sum of the logic and routing elements between the

Start and End Points.

Cell Delay %:

This describes the percent of the cell delay in data path delay.

Routing Delay%:

This describes the percent of the routing delay in this path

Slack:

The slack value computed for the path. The critical path has the lowest slack.

2) Launch Path

This section displayed the detailed information of the launch path containing launch clock edge

time, clock path and data path.

3) Capture Path

This section displayed the detailed information of the capture path containing capture clock edge

time, clock path and library hold time.

In Clock Hold Summary, “All violated paths”, “Top 20 paths by slack” and “All paths” are also available,

as shown in the follow figure.

Clock Relationship Summary

Timing Analysis


Clock Relationship Summary

The Clock Relationship Summary displays the constraints and slack details for the critical clocked paths,

which are in the same clock domain as well as cross clock domains. For each clock relationship, you

also can get the Critical Path Summary, Launch Path and the Capture Path.

Setup Summary

Similarly to Setup Summary of Clock Summary, you can get Clock Relationship Summary, Critical Path

Summary, Launch Path and the Capture Path from which you can get the detail information of each

clock relationship.

In this summary tab, a right-click-popped-menu is also available. The different to the clock summary is

that a new item “Show All Clock Relationship” is added. All the clock relationship will be shown in the

Clock Relationship Summary tab when the item is selected, as shown in follow figure. And the usage of

the other three items is same to the usage in Clock Summary.

Timing Analysis


Hold Summary

Similarly to Hold Summary of Clock Summary, you can get Clock Relationship Summary, Critical Path

Summary, Launch Path and the Capture Path from which you can get the detail information of each

clock relationship.

The usage of operation in the right-click-popped-menu is same to the usage in Clock Summary.

Datasheet Report

The Datasheet report provides an external perspective of the design for board analysis which

summarizes the external timing parameters for your design. It’s a worst case estimate to indicate

whether a design will work.

It reports the “Setup Times” and “Hold Times” for the input pad to FF paths in the design, maximum and

minimum clock to out times for the FF to output pad paths and maximum and minimum path delay for

the pad to pad paths.

Setup Times

Select Setup Times item under Datasheet Report to view the Datasheet Setup Delay Summary, Path

Summary and Data Path.

The setup times show the setup time for input signals with respect to an input clock at a source pad.

When two or more paths from a data input exist relative to a chip clock input, the worse-case setup

times are reported. One worse-case setup time is reported for each data input and clock input

combination in the design.

Timing Analysis


Hold Times

Select Hold Times item under Datasheet Report to view the Datasheet Hold Delay Summary, Path

Summary and Data Path.

The hold times show the hold time for input signals with respect to an input clock at a source pad.

When two or more paths from a data input exist relative to a chip clock input, the worse-case hold times

are reported. One worse-case hold time is reported for each data input and clock input combination in

the design.

Max Clock to Output Times

Timing Analysis


Select Max Clock to Output Times item under Datasheet Report to view the Max Clock to Output Delay

Summary, Path Summary and Clock to Output Path.

The propagation delay from clock inputs to chip data outputs is listed for each clock input. When two or

more paths from a clock input to a data output exist, the worse-case propagation delay is reported. One

worse-case propagation delay is reported for each data output and clock input combination.

Min Clock to Output Times

Select Min Clock to Output Times item under Datasheet Report to view the Min Clock to Output Delay

Summary, Path Summary and Clock to Output Path, as shown in follow figure.

Max Pad to Pad Times

Timing Analysis


Select Max Pad to Pad Times item under Datasheet Report to view the Max Pad to Pad Delay, Path

Summary and Pad to Pad Path.

The propagation delay from each chip input to each chip output is reported if a combinational path

exists between the chip input and output. When two or more paths exist between a chip input and

output, the worse-case propagation delay is reported. One worse-case propagation delay is reported for

every input and output combination in the design.

Min Pad to Pad Times

Select Min Pad to Pad Times item under Datasheet Report to view the Min Pad to Pad Delay, Path

Summary and Pad to Pad Path.

Timing Analysis

Clicking on the Timing Analysis allows the user to query paths in the following ways:

1. Querying for the paths based on the “Slack” value.

2. Querying for the paths based on the “Paths Start/End” Points.

Report by Slack

Timing Analysis


Select Report by Slack item and the Report Slack tab will be shown. This window allows user to list out

all the paths in the design with increasing slack values.

Search options

Search options give user different filters to limit the timing reports. Various filters include, filtering

the reported paths based on Launch Clock, Capture clock and their phases, filtering the paths

based on number of paths per start point and number of paths per end point, and filtering paths

based on maximum slack value, filtering the report type based on setup or hold options.

Path List

The Path List table has listed all the paths which meet the filters you have set.

Path Summary

Path Summary lists all the information of the current path which has been selected in the Path List.

Of course, you can get all the information of the path in the Path List.

Launch Path

Launch Path has shown the Launch Path information of the current path.

Capture Path

Capture Path has shown the Capture Path information of the current path

Report by Path

Timing Analysis


Select Report by Path item and the Report Path tab will be shown. Similarly to Report by Slack, you

also can set the search option to search the paths. Path Summary, Launch Path and Capture Path

which have described the current path also are available.

Cross Probe

In Timing Analysis, all the paths which have been listed in the report all can be located in Chip Editor or

Netlist Viewer (Post-Routing). For example, if you want to locate a path in Clock Summary to Chip

Editor, you should firstly list the path, secondly to right click on the target path, and thirdly to select

“Locate in Chip Editor”, as shown in follow figure.

In Clock Relationship Summary, Datasheet Report and Timing Analysis report, this operation is also

available.

Viewing Timing Delays with Netlist Viewer

After running timing analysis, you can locate critical path from timing report viewer to the Netlist Viewer

to view the nodes that make up a timing path, including information about total delay and individual

node delay. For further details, refer to Debugging and Optimization.

Viewing Timing Delays with Chip Editor

After running static timing analysis, you can locate critical path from timing report viewer to Chip Editor.

Chip Editor displays the critical path from source node to destination node with partitioned delays

marked. For further details, refer to Debugging and Optimization.

Simultaion


Simultaion


Introduction

Primace provides an interface that enables users to do simulations for testing and debugging the logical

operation and internal timing of your design based on the third-party tool.

Depending on the type of information you need, you can perform a functional simulation to test the

logical operation of your design, or you can perform a timing simulation to test both the logical

operation and the worst-case timing for the design in the target device.

Before starting a simulation, you must generate the appropriate simulation netlist by either compiling

the design for timing simulation and add a test bench (Tools – Options – Test Bench Settings).

Using Third-party Simulation Tools

Primace supplies the interface for third-party simulation tools.

Operation: Flow - EDA Simulation

To use this function in Primace, please specify the top module of the test bench firstly, see figure below

(Operation: Tools – Options – Project - General).

Simultaion


Top Module Name

Enter the top module name of the Test bench.

Instance Name of Design Top Module

Enter the top module name of the design that would be instanced in the Test bench.

For example, if the top modules of a project and the test bench file written by user are Mymac and tb-

top, the instantiation name of Mymac in the tb-top is u top, and then this option should be set to u top.





Introduction

Bitstream generator (Bitgen) generates configuration files for device programming. Download tool

downloads bitstream files to FPGA configuration memory ram or SPI flash memory.

Bitstream Generation abcgen

Post-routing netlist (.arv) P/R annotation files (.apa, .ara)

ABC file (.abc)

to Capital Micro chip

Bitstream Generation acfgen

from Routing

from Design Entry

Configuration file (.acf)

Memory mapConstraint file (.aoc)

Download agdl

from MCU design tool

MCU design file (.hex)

Generating Bitstream File

Before running Bitgen, you must run P&R (Placement/Routing) successfully. You can run CME Bitgen

separately by clicking or through Flow > Run Bitgen or you can run the whole design flow which

includes Bitgen by clicking menu Flow > Run Project.

Bitgen Options

Operation: Tools - Options - Physical Flow



The following are details about options on Bitstream page:

Unused IO’s default state

Specify the state for unused I/Os. There are four states available: input, output 0, output 1 and Hi-Z.

The default is Hi-Z.

Encryption Key

Set the bitstream encryption key to protect the FPGA configuration bistream against encryption. The

available key digits depends the device you plan to use. For CME-M5 series FPGA a 32 hex digits key

should be input and the contents below this title may show you tips.

CAUTION

This key has a close contact with the Decrypt Key while you use E-fuse Burner (please refer to the

E-fuse Burner User Guide from your received disc) and should be the same as which.

Output Formats

Specify the format of output bitstream files, please select one or more formats you required. There are

totally four formats:

BIN: a binary format bitstream file.

JTAG: a text format bitstream file that saves the configuration within JTAG frames.

SPI: a text file which save the bitstreams as BYTEs.

HEX: a text file that save the bitstreams as Intel 8051 HEX format.

The default format is BIN and this is a recommended choice. More bitstream types are not

recommended as this may take a long time, if they are not necessary.



Enable read protection

Enable or disable the read protection. If selected, the Flash contents of the device cannot be read. The

default is not selected.

Downloading

After you have successfully compiled a project and generated CME configuration file (.acf), you can

download this file into a device. Please note that a USB driver should be firstly installed before you

using this function. For the details about USB driver installation, please see CME Emulator User

Guide.

The table below lists the targets can be downloaded based on different file format.

File Format Target File Name Download Targets

BIN Xx_bin.acf Jtag, Flash

JTAG Xx_jtag.acf Jtag (Only)

SPI Xx_spi.acf Flash (Only)

HEX Xx.hex Flash (Only)

To Make Connections between PC and Device

The Primace provides two ways for connecting your device to a PC, users can chose the one according

to the requirements.

Method1: using the JTAG cable (Tools > Downloader > Setting)

This method should be used while the device to be programmed is directly connected to the PC where

Primace runs on.



Setup reference:

1) Check the option of Using JTAG cable.

2) Select the cable to be used such as CY-JTAG (CME-M5).

If no options available under the Cable box while the connection is well done, please click

Detect (the Primace cannot detect the available cable types automatically, users have to

add manually the cable you connected by clicking Detect).

3) Click OK to apply the setup and close the dialog.

Method2: using the JTAG Server (Tools > Downloader > Setting)

This method should be used while the device to be programmed is connected to the PC where the

Primace does not installed. Besides, the Debugware also requires the JTAG Server to be configured.

Before using this connection, make sure that the Server is already running. For the detailed information,

please refer to the JTAG Server User Guide.

Setup reference:

1) Leave option of Using JTAG cable unchecked and enable the Connect to JTAG Server

options.

2) Enter the Host value you specified while running the Server, such as 127.0.0.1.

3) Enter the Port value you specified while running the Server, such as 2508.

4) Click Connect.

To Download a Configuration File to Device

1) Connect your development board with PC through the USB cable supplied, for the

connection methods please refer to To Make Connections between PC and Device.



2) Click Tools > Downloader or on the tool bar, the download panel appears as the figure

below.

3) Specify the target device. If no target is appeared, click the Detect Devices and pay attention

to the information shown in the Console window.

4) Click Browse to select the file you want to download.

Note the default generated configuration file is with format bin.acf and the Primace support

multiple file formats to be downloaded: .acf, .hex, .dat and .mcf. Wherein, the .dat format is

used for the initialization of EMB.

The Bitgen function supports four types file to generate, for the setting method please refer to

the section Bitgen Options.

5) Setup the download Options.

The target allowable depends on the format of the generated configuration file to be used,

please refer to the table in section of Downloading to choose the one you required.



Erase: is used when the Target is Flash. If checked, the flash data would be firstly erased

before downloading.

NOTE

This option should be selected while a complete configuration file is

required to be loaded into the device.

While downloading different configuration files into different Flash

locations, please do not check this box if you divide the download

process into separate times.

Verify: if checked, data writing alternates with data verification during downloading, which

ensures the data programmed into Flash or Chip are correct. If the verification is failed, errors

will be reported to the Console Window and downloading will be stopped.

Address:0x: specify the start download address. The default is 0. This option is used only

when the Target is Flash.

NOTE

The original data file the device would be recovered after another

data file is written while using a same address.

Please do not assign a same address for each file you want to write

into a Flash.

6) Click Program button to start downloading automatically.

To stop the file downloading, click .

When the download task finished, the progress bar shows 100% and Console Window

shows the related information.

Common Errors and Solutions

This part lists some common errors during the download with recommended solutions for your

reference.

1) NO JTAG cables found, please

Check if you have installed the driver properly; Check if the connection between the download cable and PC is properly done.

2) Found 0 devices, please

Check if the develop board is powered on; Check the connection between the download cable and the develop board; Check the connection between the device and the develop board.

Debugging and Optimization




Introduction

An embedded logic analyzer Debugware is designed to inspect the signal translation inside the FPGA.

Primace offers console window, design report, Netlist Viewer, Chip Editor and Cross-probing feature

that enable you to analyze result of EDA flows and identifying timing critical paths, and provide ways of

manual optimization. It also offers Signal monitor feature that allows you to route user-specified signals

to output pins without affecting the existing fitting in a design, so that you can debug signals without

having to recompile the design. Capital Micro offers AGDI plug-in for Keil µVision software to debug the

embedded system design.

Besides, Primace provides options, Chip editor and iXplorer to optimize the design performance. You

can specify Synthesis Options to optimize the synthesis result and use the Chip editor to do manual

placement to improve the performance. iXplorer is used to get the best performance for your design.

Console window

Primace provides a Console window that includes several Tabs to monitor the running status of design

flow (see figure below).

Output: display all the output messages of a flow.

Information: general information.

Warning: show warnings about constraints and settings. The flow will not be blocked because of

warnings.

Error: show error messages, such as design errors, setting errors, constraints errors etc.

The Console window can be open or hidden by clicking View > Console on the menu bar.



Design Report

Primace generates a design report and automatically open it after the project is successfully complied.

If you running each flow step separately like synthesis, placement, routing and timing analyzing, the

design report of each flow step also will be generated and automatically opened. These reports contain

many sections that can help you analyze the implementation of your design. A typical design report

shows as follows.



Netlist Viewer

Netlist Viewer provides different levels schematic view of your design and a hierarchy list, which lists

the instances, pins, and nets for the entire design netlist. It can help you debug the design.

It consists of several types of viewers: technology mapper viewer, post-placement viewer, and post-

routing viewer. The technology mapper viewer is used to display the schematic of the synthesized

netlist. The post-placement viewer is used to display the schematic of the placed netlist and the post-

routing viewer is used to display the schematic of the routed netlist.

You can run Netlist Viewer by clicking Tools > Netlist Viewer and click on one of the three viewers.

Netlist viewer has two parts: a hierarchical list and a schematic view window. The hierarchical list

displays the project hierarchy in a tree format, while the schematic view window displays each element

of your designs. These elements include input and output ports, nets, and blocks. You can click the

element through expending and collapsing the hierarchical tree to navigate the element in schematic

view.



Viewing Netlist in Single/Multiple page mode

A netlist can be showed in only one page or in multiple pages in schematic view window. Sometimes,

you may have a large design, and to view a large netlist in a single page is not as convenient as you

view a small netlist. However, netlist can be partitioned into multiple pages. And you can switch from

the single page mode to multiple page mode by right-clicking anywhere of the schematic view window,

and on the shortcut menu, choose Show Mode > Multipage Schematics. In the multipage mode, each

page is divided according to the number of instances. You can set how many instances will be shown

per page in Options page, or you can use the default number (30 instances per page). When you

change the number of instances per page, the change applies only when you reopen the netlist viewer.

Viewing Property of Cells (Instance, net or port)

In order to view the property of an instance, right-click an instance and click Property on the dropdown

list. The values and pin attributes of this instance will be displayed. In order to view the property of a net,

right-click a net and click Property on the dropdown list. The connected ports and their types will be

displayed. In order to view the property of a port, right-click a port and click Property on the dropdown

list. The direction of the port and its connected net will be displayed.

Using Goto to Reach a Specified Page



To go to a previous page or following page, right-click anywhere of the schematic view window, and

click Goto Previous Page/Goto Next Page on the shortcut menu. Another way is to click or on

the toolbar.

To go to a particular page, right-click anywhere of the schematic view window, and click Goto Specified

Page on the shortcut menu. In the Goto dialog box, choose a page number you want to go or enter it

directly.

Searching Resources you need

To find what you need in the netlist viewer, do the followings:

1) Right-click anywhere of the schematic view window, and on the shortcut menu, click Find.

2) In the Find dialog box, enter what you want to find.

3) Select the following checkboxes if needed:

Select Match case checkbox if you want Primace to distinguish between uppercase and

lowercase characters.

Select Match whole word checkbox if you want the result matches the whole word precisely.

Select to use the regular expression to find resources.

4) Select what kind of resources you want to find, instances, ports, or nets. If you select all these

fields, Primace will find the matched results among ports first, then find among nets, and last

among instances.

5) Click Find Next and the schematic view window will locate the resource. Use F3 to find next

matched result.

Filtering and Tracing Nets

Tracing nets is a new function in Primace. To trace nets in more than one page, do as following steps:

1) Select Tools in toolbar> Netlist Viewer, choose the viewer you want.

2) Choose one net, right-click it and choose from page 1, or double-click it, you can trace the net until

the last page.



Filter allows you to filter out the source and destination of nodes, nets and instances in more than one

netlist. Do the followings to filter a net:

1) Press “ctrl” button and select nets, nodes or instances that you want to view.

2) Right-click anywhere of the schematic view, and on the shortcut menu, click Filter Selected Nodes.

3) The filtered view of the objects you select will be shown.



4) If you want to check a port without a value as source or destination, double-click the port, and you

will find it.

If you want to go back to the netlist, you can use the Backward button on the toolbar.

Showing a Critical Path

This function displays the logic-level critical path in the technology mapper viewer. Follow the

instructions above to use this function:

1) Right-click anywhere of the schematic view window, and on the shortcut menu, click Show critical

path (logic level).

2) Choose the critical path you want to see, and click it.

3) Once you are in the page displaying a critical path, you can right-click your mouse and Show Path

in Whole Netlist option will be visible. Click it and you can see the location of this critical path in the

whole netlist.

Specifying Options of Netlist Viewer



To open the netlist viewer options page, click Tools > Options on the menu bar, and On the Options

dialog box, click Netlist Viewer. On the General Settings page, you can do the following specifications:

Notes:

You need to reopen the Netlist viewer to apply this setting.

Chip Editor

Chip Editor is designed for users to view the chip resources and modify the placement of cells to

achieve a better performance. You can view the placement and routing results of a design. In addition,

if you do not satisfy with the results, you can use Chip Editor to adjust some cell’s locations manually.

After the adjustments, the Place and Routing flows should be performed once more in order to update

routing paths.

WARNING

The cell must be locked manually after the placement, or else the edit information on which cannot

be written into the .aoc file.

Invoke Chip Editor

To enable the Chip Editor, choose one way from the followings:

a) Choose Tools -> Chip Editor or click on the Toolbar.

b) Go to the Project view (click the icon below the Project), right click the mouse on one of the file

among .apx, apa and .ara files under the outputs folder and choose Open with -> Chip Editor,

see figure below.



Windows of Chip Editor

See figure below, the main interface of the chip editor consists of serval parts: Chip window, Lock the

cell have been modified.

Step1 Press Ctrl+S or the Save button on the Tool bar to save the modification.

Cell window, IO window, History window and Bird View window. The next parts introduce you the

details of each window.

Chip window

Chip window



The Chip window displays the placement of the Netlist on the current device with utilized resources

highlighting.

A PLB contains four LPs (Logical Parcel), a CarryIn, a CarryOut and an Lbuf. In each LP, there is two

LUT4, a LUT4C and 2 registers. The layout of the PLB follows an (x,y) co-ordinate number scheme,

with the origin at the bottom-left corner of the device. Moussing over the PLB displays the location co-

ordinate of it as Location:CxRy. The location of the LP in the PLB is lp0, lp1, lp2 and lp3 from bottom

to up. In addition, the logic cells location in the LP are also assigned as LP.

In the figure above, the locations of the logic cells in the lp0 of the PLB whose location is C11R27 are

C11R27.lp0.lut0, C11R27.lp0.lut40, C11R27.lp0.lut41, C11R27.lp0.reg0, and C11R27.lp0.reg1.

Finally, the CayrryIn, CarryOut and Lbuf location is CxRy.co, CxRy.ci and CxRy.lbuf,

respectively.MAC and EMB are also follow the above location rule.

The IO Tiles are located along the periphery of the chip. Each IO Tile may have 0, 1, 2, 3 or 4 IO pins.

For M7 device, the hard IP PLL, DLL, Oscillator and Crystal are located at the four corners of the chip.

In addition, Spram, JTAG, 8051, Arm and Debugware are located to the right IO Tiles.

Operations on Chip Window

Setup the Chip View

This chip editor provides multiple views for displaying the chip resources to meet users with different

requirements. Right click the mouse on anywhere in the Chip window, a menu pops as shown in figure

below.



Lock

Lock the cell you selected currently. When checked, a lock symbol is appeared at the left side of the

cell you selected like .

CAUTION

The lock function is only for the used cell.

This action must be done after the placement, or else the edit information on which cannot be written into the .aoc file.

Lock all

When selected, all used cells would be locked.

Unlock all

Release the lock for all used cells.

Display fanin

Display only the nets that drive the cell. When checked, moving the mouse on the net displays the

From and To location as shown in figure below.

Display Fanout

Display only the nets that are driven by the selected cell. When checked, moving the mouse on the net

displays the From/To location of the cells.

Display both fanin and fanout

Display both the fain and fanout cells, see figure.



CAUTION

Neither the fanin nets nor fanout nets can be selected.

Show timing

Display the timing delay on the fanin and fannout net. This is availabe only when the Timing flow is

done.

No split

Resume the default view of the chip placement.

Vertical/Horizontal split

Split the chip view into two samed view vertically or horizontally. This is useful while the target location

if far from the original.

Fit in window

When selected, the current chip view would be switched into the intial view in order to show all the cells

in the Chip window.

Locate

The Chip Editor allows you to locate a selected cell into the othe tools supported by the software. For

the details, please refer to the section of Cross Probing.

Modifying Placement of the Cells

A cell can be moved as a unit to a new placement location in this window.

Step2 Find the cell to be assigned and click the mouse on it, see the left figure below.



CAUTION

This operation is permitted only when the cell is selected, ie, the mouse pointer chenges to indicates this cell is editable.

You can select more than one cell at one with the help of Ctrl key;

The selected cell is shown with the fannin nets and fanout nets and is highlighted with a dark red color background.

Step3 Click and hold the left mouse and drag the cell you selected to the desired position. Please

note that the target cell must be empty and the type of which should be the same as the

original cell.

Before assigning (when selected) After assignning

Step4 Lock the cell have been modified.

Step5 Press Ctrl+S or the Save button on the Tool bar to save the modification.

Cell window

This window lists all the cells that have placed in the chip.

Name

Displays the name of the cell in the design.

Location



Displays the current location of the cell. Please note that the location would be highlighted in red color if it is modified. Moving the cell may cause this action.

Locked

Lock the cell or release the lock of a cell. This funciton is the same with the Lock/Unlock opeartion in

Chip window, plese refer to description in the seciton of Setup the Chip View.

CAUTION

Too lock/Unlock all the cells at once in the Cell window, click the mouse on the Table Header

and Choose Lock all or Unlock all from the pop-up menu.

Designed Location

Display the cell location from the Routing flow.

Operations on Cell Window

Cell Locating in Chip Window

The table provides an access for uses to locate the cell in the chip window faster and accurately. You

may select one or more cells with the help of Ctrl or Shift key from the table and click the right mouse.

From the pop-up menu, choose Selected in ChipView, see table below.

Besides, you can also double click the mouse on a row in the table to directly locate a cell into the Chip

window.

Cell Searching by Filter

This chip editor module allows you to find the required cell quickly by using its Filter function. To use

this function, right click the mouse on any place of the Table Header and choose Set filter from the

pop-up menu.



Match all

When checked, the cell table lists only the cell that meets all the search condition you specified.

Match any

When checked, the filter lists all the cells if any of the specified condition is reached.

CAUTION

As the searching result will be listed in the cell tabel instead of the total cell data, so you have to clear the filter when you finish the cell searching:

Click the mouse on the Table Header and choose Clear filter from the pop-up menu, see the left figure above.

Besides, you can also use the icon next to each title in the Table Header to list the cell alphabetically

in ascending and descending order.

IO window

This window provides an IO table that lists all the used IOs in the Chip window with its name and

location.

In this window, you can:

Locate into the desired the IO faster, the method is the same with in the Cell window; please

refer to Cell Locating;

Re-arrange the order shown of IO in the table by using the arrow next to the tile name.

History window

In this window, it lists all operations including moving, locking and unlocking that have been done in the

Chip window. You can easily resume to the last or any operation status record in this window.



CAUTION

If you resume to one of the operation and continue editing the placement, the records after the resumed operation would be deleted.

The history information persists in the window while you restart the Primace.

Bird View window

The Bird View provides a real-time and scaled-down global view of the chip. It is useful while the Chip

view is enlarged and you want to move to other location. To do so, drag the red rectangle in the Bird

window into the area you are concerning. In this view, the used PLB is identified in a darker background,

see figure below.

Cross Probing

Cross-probing features enable you to locate instance, pin and net among different editors/viewers. You

can use cross-probing features among editors and viewer to analyze your design.

Notes:

Cannot locate from design file in Text Editor.

If the opened file is not generated by current project (with current top module setting), locating operation will be disabled.

Technology Netlist mentioned below includes post-mapping, post-placement and post-router.

Locating port

Cross probing will support locating ports among all kinds of editor/viewer. Port name in design will not

be changed during whole flow.



Since Chip Editor cannot show design port, when locate port to Chip Editor, corresponding I/O cell in

Chip Editor will be chosen

Locating Net

Net can only be located among three kinds of technology netlist viewer and chip editor, the net name

keeps the same during these flows, no change is needed for net name. If we try to locate net “N1” from

technology netlist viewer to chip editor, the same net name and node type will be passed to chip editor.

Locating Instance

Instance can be located between all editors/viewers except I/O Editor.

Design File

(Text Editor)

Chip Editor

IO Editor

Gate-level

Netlist Viewer

Technology Netlist Viewer



Only I/O cells in Chip Editor can be located to I/O Editor.

Signal monitor

Signal monitor is designed for debugging after router is successfully run. It allows you to route user-

specified signals to output pins without affecting the existing fitting in a design, so that you can debug

signals without having to recompile the design. Incremental routing method is applied in this flow. The

I/O(s) reserved in I/O assignment are available for use in this flow.

Starting with a fully routed design, you can select and route signals for debugging through I/O pins that

were either previously reserved or are currently unused.

Flow

The following diagram describes the flow of signal monitor:



Invoke signal monitor assigner

Select Tools->Signal Monitor Assigner to enable the Signal Monitor Assigner dialog.

Windows of Signal Monitor Assigner

Profiles

This part lists all the available profiles. You can set the current active profile that will be used when you

run signal monitor flow. The available operations on profiles are listed as following:

Set as active profile

Right click a profile which you want to be used in the signal monitor flow, and select “Set as active

profile”. The profile item will be marked with a green tick icon to indicate it is active. It can be switched

between different profiles.

Add profile

Right click in the profile list, and select “Add profile”. The new profile is named profile_ appended a

sequence number by default, for example, profile_1, profile_2, profile_3 and so on.



Copy profile

Right click the profile you want to copy and select Copy profile. A new profile will be created.

Remove profile

Right click the profile you want to remove from the profiles list, and select Remove profile. The file will

be removed. However, you cannot remove the profile that has been set as active profile.

Nets Table

The table that contains four columns: Net Name, Port Name, Pin Location, and Pin Name have listed

all the nets that you want to monitor. In the table, add a net or remove a net operations are be available.

Add Net

Right click in the table, and select Add Net. A dialog will be popped up. In this dialog, you can search a

pin or net that you want to monitor. You can set the search type, search pattern and whether case

sensitive.

Type

According to your requirement, you can select Pin or Net in the Type combo box.



If you select Net as search type, the net that you have selected will be added to the Nets Table.

If you select Pin as search type, it will list all the pins that match the search pattern. And the net which is drived by the port you have selected will be added to the Nets Table.

Pattern

You need to set the search pattern in the Pattern edit. The search pattern meets to tcl string match

pattern.

Case Sensitive

You can set the checkbox checked or not to determine whether the search is case sensitive.

After find the target net, you should click the OK button in the dialog to add the net to the Nets Table.

Remove Net

Right click a net in the Nets Table, and select Remove Net to remove a net form the Nets Table.

Edit Net

In the table, it allows you to router user-specified signals to output pins without affecting the existing

fitting in a design, so that you can debug signals without having to recompile the design. In the Pin

Location column, the I/O(s) reserved in I/O assignment are available. You can select a pin location for

the net from the Pin Location column, and then you can debug the signal through the I/O pin that is

indicated by the pin location.

In addition, you can modify the Pin Name to specify the I/O pin. The pin location and the pin name is

one to one correspondence.

Net Driver

In this part, it lists the driver of the net that is selected in the Nets Table.

Net Loads

In this part, it lists all the net that is loaded by the net you have selected in the table.

Note: After you have finished the setting for the signal, you should run signal monitor flow that is

available in the Flow menu.

iXplorer

iXplorer is a tool that helps users achieves the best performance by automatically scanning various

options and timing constraints.

Operation: Tools - Options – iXplorer



Ixplorer Setup

Parameters of End Way

The iXplorer flow stops when one of the following setting is matched.

CAUTION

Users have to specify at least one mode of the end way, or else the flow would not be stopped unless

you click

Target Fmax

Specify the desired maximum value of the frequency.

Max Loop Count

Specify the desired maximum flow numbers for the iXplorer. The default is 1.

Ending before time

Set when the iXplorer flow stops.



FMax Scan Range

Specify the Fmax range while running iXplorer. The minimum should be greater than 0. A range

between 50MHz and 200MHz is recommended in common situations.

Run iXplorer

Operation: Flow->Run iXplorer

When the case has more than two clocks, you have to choose the clock to be analyzed.

During the iXplorer running process the progress of each flow is shown in a real-time at the Progress

View.

When finished, a dialog pops up and reminds you the results. To stop the process, click the button

on the Toolbar.

To View the iXplorer Results

Operation: Flow - iXplorer Report

The results are shown in the interface below when the flow finished.



If right click the mouse on some item, you can select:

Open Timing Report

Go to the Timing Report relates to this result.

Debugware

The Debugware is an embedded logic analyzer. Designer always wants to inspect the signal transition

inside an FPGA. The Debugware uses the embedded memory to store the internal signals waveform,

and retrieves data via JTAG port after trigging events happened.

Flow

The following diagram describes the flow of Debugware:



The whole Debugware flow can be divided into 6 steps like follows:

1) Use the Debugware IP Wizard to generate the customized IP.

2) Instantiates this module in user design file. Connect the signals that are observed and trigger

signal to the module.

3) Rerun the project to generate the new bitstream and download the *_jtag.acf to device.

4) Use the real time debugger to set the trigger condition settings.

5) Run JTAG server and connect the JTAG cable to run. Trigger and dump the VCD waveform file.

For the detailed JTAG Server settings, please refer to To Make Connections between PC and

Device.

6) Use the Wave viewer to view waveform.

Using IP wizard to generate debug IP

Click Tools > Wizard Manager and choose to create the Debugware IP.

Take the following steps to customize Debugware core:



1) Specify a name in Module name box, and select a directory to save output files. The default

directory is the src folder in the current project, or you can browse to any folder to save files. Then

click Next.

2) Choose the number of LA cores. The Debugware supports up to 4 LA cores.

3) Set the Storage settings and Trigger type. The EDGE type has RISE edge and FALL edge trigger

modes; The Arithm compares the data in with the operand to generate the trigger condition; the

trigger will be generated when the data in is between the two operands.



The Wizard will also generate a ADF(Agate debug file) when customization finished. ADF file is the

exchange data file and will be used during real time debug

Specifying and Running the JTAG Server

Take the following steps to run and set the JTAG Server:

1) Connect the JTAG cable with the board and power on.

2) Click Capital Micro->Primace -> Tools -> jtagserver to start the program.

3) Double click the tray icon and set the port as the figure below and click Run button to run the

JTAG Server.



4) Open the Downloader tool and setup the Host and Port information. Please note that the port

must be same as the JTAG Server, and then click the Connect button.

5) Download the *.acf bitstream to the device.

Using Debugware to debug the project

Click Tools > Real Time Debug to open the Debugware interface.

Take the following steps to use the Real Time Debug tool.

1) Open the Real Time Debug tool, the GUI is shown as below, the ADF file that is generated by

the Debugware IP wizard is loaded automatically.



From which, you can set the IP and Port; reset the trigger and storage settings in the GUI.

Please note that both IP and Port should be the same as the JTAG Server settings of the

Downloader tool and the operation do not need rerun the Primace flow.

2) Click the Run button and the Real Time Debug tool starts sampling the signal to storage. The

waveform is shown automatically and which would be saved into the vcd file when the trigger

condition is met. The button provides you an access for viewing the waveform directly

without performing running process.



Keil Debugger

Refer to the CME Emulator Quick Start.

EDA Tool Support


EDA Tool Support Chapter 10 User Guide

This chapter introduces the supported third-party EDA tools and interface.

Introduction

Primace allows you to use a third-party EDA tool for various stages of the design flow, including

simulation, and formal verification and timing analysis. The figure below illustrates the EDA Tool Design

Flow.

Source design files(.v, .vhd, )

Primace Synthesis Tool

Primace Placement

Primace Routing

Primace Timing

Analysis

Third-party Timing

Analysis Tool

Third-party

Simulation Tool

Primace Bitstream Generation

Primace Download

Verilog netlist (.amv )

Third-party Formal

Verification Tool

Verilog netlist (.apv, .arv )

Third-party Tool-Keil

Embedded System Design

Debugger Driver Plugged-in

MCU design file(.hex)

Simulation Tools

Primace permits you to perform functional simulation and timing simulation with the third-party

simulation tool ModelSim. The following contents introduces you how to use ModelSim to do simulation.

To Configure ModelSim Environment

1) Open the Options Dialog by clicking Tools > Options to customize the Primace Environment.

2) In the Environment Page, input the ModelSim installation path by Browse. If the path is not the one

you installed the ModelSim, the ModelSim does not start.

EDA Tool Support


RTL Simulation

RTL simulation is recommended when you finish a design in order to make sure that your design

function is as expected.

Click Flow > Simulation > RTL Simulation to run logic simulation.

Timing Simulation

Timing simulation allows you to check that the implemented design meets all functional and timing

requirements and behaves as you expect in the device. It is recommended when you finish the timing

analysis.

Before starting a timing simulation, you must generate the appropriate simulation netlist by either

compiling the design for timing simulation and add a test bench (Tools – Options – Project – General

- Test Bench Settings).

Appendix I: Design Example


Timing Analysis Tools

Primace provides an interface which enable users to do simulations for testing and debugging the

logical operation and internal timing of your design based on the third-party STA tool – Primace Time.

To specify the Primace Time:

1) Click Tools > Options on the menu bar to open Options dialog box.

2) On the EDA Tools page, choose Prime Time.

3) Specify the settings of the Server where the Prime Time is running.

4) Specify the timing constraint, then you can run Primace Time form Flow->Run Timing Analysis.

The timing report comes out after timing analysis is successful.




This section will lead you to accomplish a complete design. This design performs the task of counter

and 8051 outputting waveform to control LED display. Here CME offers a complete design example,

please visit Capital Microelectronics website to download it. Related URL is http://www.capital-

micro.com/****** .

Preparing for this Lesson

Before starting this lesson, you should install the following software and prepare for the source design:

CME Software: Primace CD

Third-Party Tools: Keil µVision

Download Kits: CME Development Board, Download Cable, and USB driver

Create a Project

To start working on a new design, you have to create a project. In this chapter, a project named demo1

will be created.

You can also double-click the icon of Primace on desktop or select Start > All Programs > Capital

Micro > Primace XXX > from the start menu to launch it.

To create a project,

1) Click to bring out a New Project dialog.

2) Type E:\qdesign\ in the Project Directory box.

3) Choose for both the Project Name and Top Module name and type it in.

http://www.capital-micro.com/******

http://www.capital-micro.com/******



4) In the Select a device box, choose the current device.



5) Click OK to accept the settings.

Create design files with Text Editor

To create a design in Text Editor:

1) Click File > New Text File on the menu bar, or to bring out the Text Editor.

2) Enter source code in Text Editor.

3) Click Flow > Check Syntax to be sure there is no syntax errors.

4) Click File > Save to save the file in Verilog HDL. In the Save As dialog box, enter a name for

the design file, select the file format and then save it.

Primace supports the following two formats when you want to save a new design file:

Verilog HDL: Verilog Hardware Description Language

VHDL: VHDL Hardware Description Language

Define System with Wizard Manager

To define system with system wizard, follow the instructions below:

1. On the Toolbar, click Wizard Manager to start configuration.

2. Choose Create a new design to continue the design.

3. Choose 8051 of System in IP Cores to configure it.

Make an Embedded System Design

Make an embedded design in the third-party tool Keil µVision software. For further design information,

please refer to the related Keil documents. Place the .hex file which was created after system defined in

the scr sub-folder under the project folder and configure 8051 initialization file with System Wizard.

Specify initial design constraints

Specify initial design constraints with the Settings dialog box, including Project settings and EDA tools.

For more details about I/O design constraints please refer to Constraint Entry.

Run Synthesis

Select Flow > Run Synthesis.



Perform a functional simulation with an EDA simulation tool

For further details, refer to Simulation Tools.

Assign I/Os in I/O Editor

1) Select Tools>I/O Editor or open the demo1.aoc in the root directory of the project to open the I/O

Editor interface.

2) Assign ports. Either drag the unassigned port name and drop it to the I/O pin in graphic panel like

the following figure, or you can assign the port to appropriate I/O pin location in the table mode as

the following figures.

3) Save your assignments.

For more information about the I/O assignment, please refer to the chapter of I/O Editor in the user

guide.



Place/Route the design and Analyze result

Select Flow > Run Placement/Run Routing to carry out the placement and routing.

The progress of the steps are visible in process view:

Analyze the timing

Analyze the timing of the design by Flow > Run Timing Analysis.

For further details, refer to Timing Analysis

Perform timing simulation

Specify the Test Bench (Tools – Options – Project – General - Test Bench Settings) and run the timing

simulation (Flow-Simulation-Timing Simulation) by the third-party simulation tool ModelSim.

Debugging and Optimizing

Netlist viewer, timing critical path-debug

Signal monitor, Debugware. Keil C for 8051-debug

iXplore--optimize

Use the netlist viewer checking the connections and timing critical paths to analyze timing issues and

use Debugware and signal monitor to make timing closer.

For further details, refer to Timing Closure.

Create programming files and program the device

Create programming files for the design by Flow > Run Bitgen, then program the device by Tools >

Downloader. For the details, refer to Programming and Configuration.



Keil Debug

After your whole design is finished, download 8051 file and debug it in Keil µVision software. Make sure

you install our AGDI plug-in first. During the debugging process choose Capital Micro 8051 Emulator

like the following picture.

primace user guideapplication platform on chip) system design and the fpga design. it offers a...

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