proasicplus development system · 1. overview this user guide was designed for the engineer to...

SDB-750/1000

ProASICPLUS Development System

USER GUIDE

Version 1.3Document No. 41397.50.13

INICORE INC.5600 Mowry School RoadSuite 180Newark, CA 94560t: 510 445 1529 f: 510 656 0995 e: [email protected]

© 2 0 0 3 , I N I C O R E I N C .

SDB-750/1000 User Guide

INICORE, INC. has made every attempt to ensure that the information in this documentis accurate and complete. However, INICORE, INC. assumes no responsibility for anyerrors, omissions, or for any consequences resulting from information included in thisdocument or the equipment it accompanies. INICORE, INC. reserves the right to makechanges in its products and specifications at any time without notice.

Any software that is described in this document is furnished under a license or non-disclosure agreement. It is against the law to copy this software on any media for anyother purpose than the licensee's personal use.

Acknowledgments:

ProASICPLUS TM is a registered trademark of Actel Corporation.ARM and EmbeddedICE are trademarks of Advanced RISC Machines, Ltd.PICMG®, Compact PCI®, and the PICMG®, and CompactPCI®, logos are registeredtrademarks of the PCI Industrial Computer Manufacturers Group.All other brand, product names or trademarks may be trademarks or registeredtrademarks of their respective holders.

© 2002, 2003 INICORE, INC.All rights reserved.

© 2003, INICORE INC. Indexes - Page II


TAB L E O F C O N T E N T S

OVERVIEW..........................................................................................................7

Document History...............................................................................................7

References..........................................................................................................8

Naming Convention............................................................................................9

Acronyms.............................................................................................................9

Definitions..........................................................................................................10

Conventions.......................................................................................................11

Features............................................................................................................12

Block Diagram..................................................................................................13

Layout................................................................................................................14

GETTING STARTED..........................................................................................15

Package Content..............................................................................................15

Documents.........................................................................................................15

Software.............................................................................................................16

Accessories........................................................................................................16

SDB development board....................................................................................16

Manuals..............................................................................................................16

Additional Information......................................................................................16

System installation...........................................................................................17

Board setup........................................................................................................17

Power supply......................................................................................................17

Host connection.................................................................................................18

Basic Jumper setting..........................................................................................19J3: UART 1 Source Select............................................................................................19J4: UART 2 Source Select............................................................................................20J7: CPU Disable...........................................................................................................20J8: Clock Jumpers........................................................................................................21

© 2003, INICORE INC. Indexes - Page I


MAIN BUILDING BLOCKS.................................................................................23

ProASICPLUS and CPU Sub-System..............................................................23

ProASICPLUS FPGA (750k/1000k System Gates)............................................25Block Diagram..............................................................................................................25Signal Description........................................................................................................26

ATMEL CPU.......................................................................................................27Bus & I/O Signals.........................................................................................................28Memory Mapping.........................................................................................................30

GlueChip............................................................................................................31Block Diagram..............................................................................................................31Register Mapping.........................................................................................................32Pin Description.............................................................................................................36

Flash..................................................................................................................39

SRAM.................................................................................................................39

Power Regulators.............................................................................................40

Reset Logic.......................................................................................................41

Prototyping Area...............................................................................................42

CANbus..............................................................................................................44J5: CAN Port 1 Configuration.......................................................................................45J6: CAN Port 2 Configuration.......................................................................................45J9: CAN Bus Termination.............................................................................................45

LVPECL Differential Data.................................................................................46

User Interface....................................................................................................47

Real Time Clock................................................................................................48

EXTERNAL HARDWARE..................................................................................49

Overview............................................................................................................49

PCI Mezzanine card (PMC)...............................................................................50

SDRAM-DIMM....................................................................................................50

Compact Flash..................................................................................................50

SOFTWARE.......................................................................................................51

© 2003, INICORE INC. Indexes - Page II


Program Memory Mapping...............................................................................52

RedBoot Monitor...............................................................................................52

Application Installation Process......................................................................54

Application Mode Installation..............................................................................55

Demo Application Overview.............................................................................56

Additional Tools................................................................................................57

CONFIGURATION..............................................................................................58

Jumper Settings...............................................................................................58

J1: JTAG Source Select.....................................................................................58

J2: JTAG PCI Mezzanine card...........................................................................58

J3: UART 1 Source Select.................................................................................58

J4: UART 2 Source Select.................................................................................59

J5: CAN Port 1 Configuration.............................................................................59

J6: CAN Port 2 Configuration.............................................................................59

J7: CPU Disable.................................................................................................60

J8: Clock Jumpers..............................................................................................60

J9: CAN Bus Termination...................................................................................60

Options..............................................................................................................61

LK1: JTAG PMC Enable.....................................................................................61

LK2: JTAG GlueChip FPGA Enable...................................................................61

LK3: Flash Byte Mode Select.............................................................................62

LK4: DC-DC Converter.......................................................................................62

LK5: Registered SDRAM DIMM Configuration...................................................63

LK6: BVD2 Enable.............................................................................................63

LK7: SRAM Configuration..................................................................................63

LK8, LK9: ProASICPLUS Power........................................................................63

LK10: I2C / CF_IO signals..................................................................................64

LK11: Boot-Mode Select....................................................................................64

LK12: Shutdown - INTC Select..........................................................................64

LK13: RCK - INTD Select...................................................................................64

© 2003, INICORE INC. Indexes - Page III


Connector Definitions......................................................................................65

Power.................................................................................................................65

PMC connectors.................................................................................................65J11: PMC-Jn1..............................................................................................................65J12: PMC-Jn2..............................................................................................................66J13: PMC-Jn3..............................................................................................................66J14: PMC-Jn4..............................................................................................................67

J15 : I2C.............................................................................................................67

J16: JTAG ProASICPLUS..................................................................................68

J17: JTAG ProASIC...........................................................................................68

J18: JTAG-ICE...................................................................................................68

J19: SDRAM DIMM (PC100)..............................................................................69

J20, J21: CPUext 1, CPUext 2 respectively.......................................................70

J22: Display Connector......................................................................................71

J23, J24: LVPECL Data.....................................................................................71J23: EPECLIN, Positive PECL......................................................................................71J24: EPECLREF, Negative PECL.................................................................................71

J25: CompactFlash...........................................................................................72

J26: User IO 1....................................................................................................72

J27: User IO 2....................................................................................................73

J28: User IO 3....................................................................................................74

J29: User IO 4....................................................................................................74

J30, J31, J32: Debug Header............................................................................75J30: CPU_CTRL...........................................................................................................75J31: CPU_Addr............................................................................................................75J32: CPU_Data............................................................................................................75

J33, J34: UART 1, UART 2 respectively............................................................76

J35, J36: CAN 1, CAN 2 respectively.................................................................76

J37, J38, J39, J40, J41: Local Power Connectors.............................................76

Test Points........................................................................................................77

Prototyping Area...............................................................................................77

SDB-750/1000 connectivity table.....................................................................78

CPU....................................................................................................................78

PMC J1 & J2......................................................................................................78

© 2003, INICORE INC. Indexes - Page IV


PMC J3 & J4......................................................................................................79

SDRAM..............................................................................................................81

Prototype Area...................................................................................................82

Keyboard............................................................................................................82

PA_GPIO's.........................................................................................................82

UART 1/2 (Transceiver)......................................................................................82

CANbus 1/2........................................................................................................83

Clocks and Reset...............................................................................................83

PECL..................................................................................................................83

JTAG..................................................................................................................83

Programming......................................................................................................83

Miscellaneous.....................................................................................................83

SCHEMATIC......................................................................................................84

© 2003, INICORE INC. Indexes - Page V


TABLE OF FIGURESFigure 1 - SDB Block Diagram...........................................................................13Figure 2 - SDB System Layout...........................................................................14Figure 3 - SDB Packaging Information...............................................................15Figure 4 - Board setup.......................................................................................17Figure 5 - Power Connector...............................................................................18Figure 6 - RS-232C connection..........................................................................19Figure 7 - Clock distribution network..................................................................21Figure 8 – PA+ & CPU Sub-System Block.........................................................23Figure 9 - Block Diagram ProASICPLUS FPGA.................................................25

Figure 10 - Block Diagram AT91X40 Series CPU ( 2000 ATMEL Corporation)...........................................................................................................................27Figure 11 - GlueChip Block Diagram..................................................................31Figure 12 - DC-DC converter configuration........................................................40Figure 13 - Reset Logic block diagram...............................................................41Figure 14 - Reset Logic......................................................................................41Figure 15 - Prototyping area block diagram.......................................................42Figure 16 - Prototyping Area..............................................................................42Figure 17 - CANbus block diagram....................................................................44Figure 18 - CANbus network..............................................................................44Figure 19 - LVPECL block diagram....................................................................46Figure 20 - LVPECL impedance match..............................................................46Figure 21 - User Interface block diagram...........................................................47Figure 22 - RTC block diagram..........................................................................48Figure 23 - External Hardware block diagram....................................................49Figure 24 - Layer structure.................................................................................51Figure 25 - Installation process..........................................................................54Figure 26 - Demo Application screen flow..........................................................56Figure 27 - Power connector..............................................................................65Figure 28 - UART connector pinout....................................................................76Figure 29 - CANbus connector pinout................................................................76

© 2003, INICORE INC. Indexes - Page VI


1 . OV E R V IE W

This User Guide was designed for the engineer to provide technical information of the SDB-750/1000 development platform. This guide should allow the user to get a quick start andsolid introduction into the world of ProASICPLUS based systems.

This guide is divided into three sections:

1. The getting started guide that helps with the unpacking and setting up of the system.

2. Detailed explanations of all system components and features.

3. Explanations of the system software that comes installed with the SDB-750/1000development platform.

The application notes section at the end provides additional information how the SDB-750/1000 development platform can be used to program the ProASICPLUS FPGA.

1.1. Document History

The following table gives an overview of the document history and can help in thedetermination if the latest version of this document has been used.

Version Date Author Comments

1.0 2/21/02 DL Initial version

1.1 5/2/02 JPM Completely updated version with new chapters

1.2 5/7/02 JPM Minor updates after verification

1.3 5/9/03 HJK Corrected memory sizes, added schematic

© 2003, INICORE INC. Overview - Page 7


1.2. References

The following reference documents have been used. Most of them are available on the CD-ROM that were delivered with the SDB development platform. If they are not available withthe appropriate institutions they can be requested via Inicore for an additional fee.

• CompactPCI, The PCI Telecom Mezzanine/Carrier Card (PTMC) Specification,PICMG2.15 R1.0, 4/11/2001, © Copyright 2001, PCI Industrial Computer ManufacturingGroup

• Standard for a Common Mezzanine Card Family: CMC, P1386, D2.4a, March 2001, ©Copyright 2001, Institute of Electrical and Electronic Engineers, Inc.

• Standard Physical and Environmental Layers for PCI Mezzanine Cards: PMC, P1386.1,D2.4, January 2001, © Copyright 2001, Institute of Electrical and Electronic Engineers,Inc.

• AT91X40 Series, ARM® Thumb® Microcontrollers, Rev. 1354B-07/00, © Copyright 2000,ATMEL

• ProASICPLUS TM APA Family Product Profile, Advanced v0.3, December 2001, © Copyright2001, Actel Corporation

• SX-A Family FPGAs, Preliminary v1.1, September 1999, © Copyright 1999, ActelCorporation

• 28F320J3A, 3-Volt® StrataFlash® Memory, Datasheet Order # 290667-010, © Copyright2001, Intel Corporation

• 3.3V CMOS Static RAM 4 Meg (512K x 8-Bit), DSC-3622/03, © Copyright 1999,Integrated Device Technology, Inc.

• CompactFlashTM Memory Card Product Manual, Lit. No. 20-10-00038 Rev. 7 4/2000, ©Copyright 2000, SANDISK CORPORATION

• PCA82C250 CAN Controller Interface, 1997 Oct 21, © Copyright 1997, PhilipsSemiconductors

• AND Application Notes, Intelligent Alphanumeric Displays, 12/17/99, © Copyright 1999,Purdy Electronics Corporation

• I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs, RS5C372A/B, ApplicationManual, NO.EA-04409908, © Copyright 1995, Ricoh Electronic Devices Division

• MAX322x datasheet, 19-0306; Rev 6; 3/99, © Copyright 1999, MAXIM IntegratedProducts

• Micropower Inverting DC/DC Converters, © Copyright 1999, Linear Technology



1.3. Naming Convention

The following two sections define the acronyms and definitions that have been used withinthis user guide. For additional information please refer to the corresponding documentationeither through the respective agencies or via the Internet.

1.3.1. Acronyms

Within this section we defined the acronyms that have been used throughout this document.

Acronym Explanations

ARM Advanced Risk Machine

CF Standard CompactFlash device that is supported by the SDBdevelopment board.

GC GlueChip: Preprogrammed FPGA that contains the system logic

GND Ground signal

GPIO General purpose input and/or output port

Mb One Mega-bit is 1024 bits or 128 Bytes

MB One Mega-Byte is 1024 Bytes or 8096 bits

PA ProASICPLUS FPGA from Actel Corporation

PCI Peripheral Component Interconnect

PMC PCI Mezzanine Card

PTMC PCI Telecom Mezzanine Card

RCK Running clock signal that is used to program the ProASICPLUS FPGA.

SMLink Surface mounted link that are represented by 0Ω resistors

STAPL Standard Test and Programming Language

UPI Microprocessor interface

VDD12 12V power supply signal, only used in connection with the PMCMezzanine expansion card

VDD25 2.5V power supply signal



VDDCF Power supply signal for CompactFlash card

VDDDCDC Power supply signal for DC-DC converter

VDDL Core voltage signal of the PA FPGA. Usually connected to VDD25

VDDN12 Negative 12V power supply signal, only used in connection with thePMC Mezzanine expansion card



Acronym Explanations

VDDNP Negative programming voltage signal that is used for the ProASICPLUS

devices

VDDP SDB-750/1000 voltage signal of the PA FPGA. Usually connected toVDD33

VDDPP Positive programming voltage for ProASICPLUS devices

1.3.2. Definitions

This section should simplify the usage of this document by providing a single place wherecommon definitions are defined for the reader.

Definitions Explanations

CAN Controller Area Network, which is a serial data bus system developedby Bosch for the automotive industry. Subsequently it was standardizedinternationally (ISO11898). The bus itself is a symmetric or asymmetrictwo wire circuit, which can be either screened or not screened.

eCos Embedded micro controller operating system that is based on the openstandard featured by RedHat Corporation

GCC GNU open source C compiler that comes with standard Linuxinstallations

GDB GNU open source debugger for C as part of standard Linux installations

I2C Inter-IC, a type of bus designed by Philips Semiconductors in the early1980s, which is used to connect integrated circuits (ICs). I2C is a multi-master bus, which means that multiple chips can be connected to thesame bus and each one can act as a master by initiating a data transfer

LVPECL Low Voltage Positive Emitter Coupled Logic or Low Voltage PseudoEmitter Coupled Logic which is a differential mode transmissionstandard that allows for fast signal transmissions

SDB ProASICPLUS system design and demonstration board with either 750k(SDB-750 ) or 1,000k system gates (SDB-1000)

SDRAM Synchronous DRAM, a type of DRAM (dynamic RAM) that can run atmuch higher clock speeds than conventional memory

SRAM Static random access memory that doesn't need any refresh cycles

UART Universal asynchronous receiver-transmitter, the UART is a chip thathandles asynchronous serial communications



1.3.3. Conventions

Throughout this document the following naming conventions are used:

Convention Explanations

'_n' Signal names with this convention indicate an active LOW signal.

r/W Read back operations are executed to access static registers that don'tchange their information through external events.

Write operations are performed to change the register status.

R/W Read operations are executed to gain new information on theappearance of external events that might have a changed a registerstatus.

Write operations are performed to change the register status.

⊗ Entries market with this symbol indicate the default settings



1.4. Features

The SDB development board provides a feature rich prototyping platform for theProASICPLUS FPGA family. It allows developers to gain expertise in the specifics ofembedded design using the ProASICPLUS FPGA combined with an ARM basedmicrocontroller.

In particular the SDB supports the following features:

• Easy-to-Use development board that functions without additional hardware orsoftware.

• Contains up to 1,000,000 system gates ProASICPLUS FPGA from Actel (SDB-1000)that can be reprogrammed using the ARM CPU without external hardware.

• 2MB SRAM and 128Mb Flash memory that is accessible either by the ARM CPU orvia ProASICPLUS

• Simple user interface with LCD (2x16 characters), six programmable LED's thatprovide programmable indications of events and four input keys to control the userinterface

• ARM7TDMI subsystem that uses the AT91M40800 CPU from AMTEL

• Standard PC100 DIMM interface with 64-bit wide SDRAM

• Standard Compact Flash card slot for memory cards

• Standard PMC expansion bus that supports:- IEEE P1386.1- PCIMG 2.15 (PTMC)- 64-bit PCI interface

• Four different serial I/O interfaces such as UART, I2C, CAN and the analog LVPECLstandard

• 16 x 16 pins prototyping area with prewired signals from the ProASICPLUS

• Support for system expansion board with standard PMC Mezzanine card fortelecommunications applications

• Independent real time clock with backup battery

• eCos operating system from RedHat



1.5. Block Diagram

The following block diagram gives a high level overview of the SDB development board.

The center of the SDB is the ProASICPLUS FPGA that is connected with the CPU subsystemvia the CPU-Bus. This connectivity allows the ProASICPLUS to be programmed as the mainCPU, therefore controlling all major functions of the board.

Furthermore, the ProASICPLUS is connected to all external interfaces in order to embed theprogrammable logic into any external system architecture without difficulties or specialadaptations.


Figure 1 - SDB Block Diagram

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4

UART 1 UART 2 CAN 1 CAN 2 JTAG ICE

JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1

CPU Debug (CTRL, ADDR, DATA)

SDRAM DIMM

UIO 1

UIO 2

PM

CP

MC

PM

CP

MC

I2C

RT

C CP

U-B

usReset

CPU

GlueChipFPGA

16x16 prototype area

Clock

ProASIC+

LVPECL

User Interface


1.6. Layout

The high level board layout is shown in the following figure.

With the above layout we can see that there is additional space on the SDB developmentboard to include an external PMC Mezzanine card.

In addition the SDB development board contains a 16x16 through-hole matrix for add-onelectronic or additional connectors.


Figure 2 - SDB System Layout

AC

TE

LP

roA

SIC

PL

US

AT

ME

L

AC

TE

LSX

-A

J4_1

J4_2

J3_2

J3_1

AB

C

UIO

1

CA

N1

JTA

G-

ICE

CA

N2

JTAG

SD

RA

MD

IMM

UIO

4

PROTO

Compact Flash

CP

UE

xt1

CP

UE

xt2

CA

NC

EL

UP

DO

WN

OK

J7

CPU

CT

RL

CPU

AD

DR

CPU

DA

TA

OSC1

OSC2

OSC3

CB

A

J8_3

J8_1

J8_2

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

UA

RT

1U

AR

T2

TP5

TP6

TP7

TP4

TP3

PO

WE

R

RE

SE

T

PM

CM

ezza

nine

LC

D

J37-

J41

J33

J34

J35

J36

J18

J16

J1

J19

J9_2

J6_1

J5_1

J9_1

J5_2

J6_2

J27

J28

UIO

3

UIO

2

LE

D11

2233

4455

66

LVPECL

J2

CB

AC

BA

5V3.

3V2.

5VA

BC

PTMC


2 . GE T TIN G S TAR TE D

This section provides the new SDB user with all essential information so that thedevelopment board can be connected and initialized successfully.

In addition we describe what should have been delivered with the new SDB developmentboard and provide system installation information.

2.1. Package Content

The following figure gives an overview what should have been delivered with your new SDBdevelopment board.

2.1.1. Documents

The following documents should have delivered with your new SDB development board:

• A detailed packing list that list the specific content of your delivery

• Test report of SDB-750/1000 development board

© 2003, INICORE INC. Getting started - Page 15

Figure 3 - SDB Packaging Information

Accessories

Manuals

Documents

Software

SDB-750/1000

Content

Demo Software Application Notes

Content

5V/5A Power Supply Power Cable RS-232C Cable

Content

SDB-750/1000System Design Board

Content


Content

Packing List Test report


2.1.2. Software

The software for the SDB development board is already installed. It contains a Boot Monitorand software that supports the standard operations of the board.

In addition to the already installed software, there is a CD-ROM that contains the followinginformation:

• Electronic version of the documentation

• Necessary files that allow re-creating the manufactured configuration

Please visit http://inicore.com regularly for latest files, additional support information andapplication notes.

2.1.3. Accessories

The accessories that were delivered with the SDB development board are the following:

• 5V / 4A 110V/230V Power supply (20W)

• US power cord

• 6' long RS-232C serial interface cable

2.1.4. SDB development board

The SDB development board that contains either the ProASICPLUS FPGA with 750,000system gates or the ProASICPLUS FPGA with 1,000,000 system gates.

2.1.5. Manuals

The SDB development board user guide is the main documentation that is delivered with thepackage. It contains all necessary information to get a new user started quickly.

2.2. Additional Information

Refer to the following web-sites for additional information:

• INICORE, INC. home page at http://www.inicore.com

• Actel Corporation home page for FPGA information at http://www.actel.com

• ATMEL Corporation home page for CPU information at http://www.atmel.com

• RedHat Corporation for additional information on the operating system eCos athttp://www.sources.redhat.com/ecos



2.3. System installation

This section contains important information for the setup and installation.

2.3.1. Board setup

The following figure gives a high level overview of the board setup.

The above illustrated test set up shows the SDB development board with the accompanyingpower adapter and RS 232 cable connected to a serial port of the PC.

When connecting the RS 232 cable, please use the UART1 connector for easy set up andapplying the pre-configured board settings.

2.3.2. Power supply

The SDB development board is powered through a regular disk drive power connectorlocated in the upper left hand corner of the board.


Figure 4 - Board setup


For general purpose operations only a +5V DC power source is required that was included inthe package. The following figure shows how the power is connected to the SDBdevelopment card with the regular disk drive connector [Jameco P/N: 42067]

In case the user would like to work with a PCM Mezzanine card (separate item) that needsto be supplied with ±12V DC, the included power supply will have to be replaced.

The on-board LDOs are powered through the VDD50 signal and have the followingmaximum rating:

• VDD33: 5A

• VDD25: 1.5A

Please evaluate carefully your power budget and verify that you are within the given limitsand that the current rating of your power supply is sufficient.

2.3.3. Host connection

The connection to the host computer is achieved by using an RS-232C serial cable that isconnected to a PC, UNIX or Linux machine.

The SDB development board contains two serial RS-232C ports. They can be eitherconnected to the CPU or the ProASICPLUS FPGA device. The selection is done through theconfiguration of a jumper block as indicated in the following figure.


Figure 5 - Power Connector

+ 12V (optional)

- 12V (optional)GND+ 5V


As seen in the figure above, the UART 1 connector is designed for 'no hardwarehandshaking', e.g., RTS and CTS are connected together as well as DCD, DSR and DTR.

The UART 2 connector doesn't have the RTS, CTS, DCD, DSR and DTR lines connected.Therefore a simple protocol with only RX and TX is used while using a software handshake.

2.3.4. Basic Jumper setting

The following basic jumper settings for J3, J4, J7 and J8 should be verified as specified inthe following tables.

2.3.4.1. J3: UART 1 Source Select

The following two jumpers can be used to select the UART device that is connected tothe RS-232 transceiver. This can either the be the UART from the CPU or theProASICPLUS.

J3_1 Function Setting

A-B The CPU UART port is used for receiving signals ⊗

B-C The ProASICPLUS UART port is used for receiving signals


Figure 6 - RS-232C connection

PA+

1 DCDDSR

DTR

TXRTSRXCTS

6273

48

95

1

TX

RX

6273

48

95

UART 1

UART 2

J3_1A

B

C

J4_1

J4_2

cpu_tx2

cpu_rx2

cpu_tx1

cpu_rx1

pa_rx1A23

A24

B24

C25pa_tx1

pa_rx2

pa_tx2

A

B

C

B

U2



A-B The CPU UART port is used for transmitting signals ⊗

B-C The ProASICPLUS UART port is used for transmitting signals

Note: Please configure both jumpers for the same signal source otherwise your interfacewill not function properly.

2.3.4.2. J4: UART 2 Source Select

These jumpers can be used to select the UART macro that is connected to the RS232transceiver. This macro can be either a software routine that runs on the CPU or as anembedded function within the ProASICPLUS .



B-C The ProASICPLUS pre-configured UART port is used forreceiving signals



B-C The ProASICPLUS pre-configured UART port is used fortransmitting signals

Note: Please configure both jumpers for the same signal source otherwise your interfacewill not function properly.

2.3.4.3. J7: CPU Disable

This jumper controls if the CPU will be enabled or disabled during the startup process. Ifthe CPU is disabled, the ProASICPLUS FPGA or an external source can control the systemresources. However, the initial setting should allow for the CPU to be operational.

J7 Function Setting

None The CPU is operational ⊗

A-B The CPU is disabled



2.3.4.4. J8: Clock Jumpers

Four different clock sources are available to control the operation of the SDBdevelopment platform.

Clock sources:

1. OSC1: Socket for DIP-14 type clock oscillator with typical frequency of 30MHz.

2. OSC2: Socket for DIP-14 type clock oscillator with typical frequency of 60MHz.

3. OSC3: DIP-14 type LVPECL oscillator with typical frequency of 152.52MHz.This is a dedicated network, where the LVPECL oscillator is directly connected tothe LVPECL inputs of the ProASICPLUS FPGA. The impedance of thetransmission line is matched with a 50 Ù termination.

4. CLK32k: This is the 32kHz clock from the RTC block.

The clock source for the different clock networks can be selected using jumpers. This isshown in following diagram:


Figure 7 - Clock distribution network

PA_WPECLREF

PA_WPECLIN

GL

GL

Clk_to_ext1

Clk_to_gc

Osc2

Osc1

B

C

N22

TP 3

TP 5


Using the three jumpers that are explained in the following tables, different clockconfiguration can be chosen. The above figure indicates the default setup for thejumpers.


A-B The Clock buffer 1 is driven by the clk1_from_pa signal.

B-C The Clock buffer 1 is driven by the osc1 signal ⊗


A-B The Clock buffer 2 is driven by the clk2_from_pa signal



A-B The Clock buffer 3 is driven by the clk_to_cpu_from_pa signal


Note: Please configure all three jumpers for the desired signal source otherwise theclock interface will not function properly.



3 . M AIN BU ILD ING BL OCK S

This section describes the main building blocks as seen in the block diagram in the firstsection of this document. This section will provide all necessary information for the designerto start creating his/her own system designs.

3.1. ProASICPL U S and CPU Sub-System

In this section we will highlight the functionality of the ProASICPLUS and the CPU Sub-Systemas indicated in the figure below.

© 2003, INICORE INC. Main Building Blocks - Page 23

Figure 8 – PA+ & CPU Sub-System Block

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4


JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1


SDRAM DIMM

UIO 1

UIO 2

PM

CP

MC

PM

CP

MC

I2C

RT

C CP

U-B

us

Reset

CPU

GlueChipFPGA


Clock

ProASIC+

LVPECL

User Interface


As seen in the figure above, the CPU Sub-System contains the following devices that areconnected through the CPU-Bus.

• The ProASICPLUS FPGA that contains the custom logic.

• The ATMEL CPU which controls the SDB functions such as operating system, timerfunctions, program downloads, etc. when using the standard configuration.

• The GlueChip that controls functions such as SRAM decoding, CompactFlashinterface functions, programming reference clock, etc.

• The Flash memory chip that contains the operating system software.

• The SRAM that is used for the system software or as external memory for systemfunctions.

• Two CPU Extension connectors that provide access to the entire CPU-Bus and allowto control the SDB functionality if configured appropriately.

• Three connectors that provide the necessary CPU signals so a logic analyzer can beconnected for system analysis and debugging.

The following sections are explaining these components more in detail.



3.1.1. ProASICP L U S FPGA (750k/1000k System Gates)

The ProASICPLUS FPGA for the SDB is delivered in two different sizes. The smaller chipcontains 750,000 system gates, whereas the bigger size chip comes with 1,000,000 systemgates.

This chip combines the advantages of using ASIC's for system designs while having thebenefit of using a device that is programmable through nonvolatile Flash technology. Withsuch a device the engineer can create high-density systems using existing ASIC or FPGAdesigns and/or tools.

3.1.1.1. Block Diagram

Whereas the ProASICPLUS FPGA allows great flexibility for system designs, using theSDB development board offers the following pre-configured ports. These ports are wiredto the appropriate devices, as indicated in the block diagram above, allowing a simplifieddesign process.

The following figure gives an overview of the ProASICPLUS FPGA with its predeterminedfunctionality on the SDB.

Note: The above mentioned functional blocks are only one possibility on how to use theProASICPLUS FPGA. The VHDL/Verilog code for these interface blocks are notincluded with the board.By using the connectors on the SDB development board much of this functionalitycan be replaced and/or customized to the specific needs of the system design.


Figure 9 - Block Diagram ProASICPLUS FPGA

Pro ASICPLUS

CPUbus

SDRAM

PMCM

PMCM_auxProtoUIO4UART 1or 2

CANbus 1or 2

Buttons

Clocks Misc LED's PECL


3.1.1.2. Signal Description

The ProASICPLUS signal description for the specific layout of the SDB development boardcan be seen in the table below.

Signal Width

[# of pins]

Description

CPUbus 52 CPU Bus

SDRAM 96 SDRAM DIMM port

PMCM 61 Standard PMC Mezzanine port

PMCM_aux 92 Standard PMC Mezzanine auxiliary port

Proto 19 Signals for the 16x16 external prototyping area

UIO4 9 User definable I/O port 4 that is connected with the UIO4connector.

UART 1,2 4 UART port (RX, TX only) for either the UART 1 or 2connector.

CANbus 1,2 4 CANbus port for either the CAN 1 or CAN 2 connector.

Buttons 4 2x2 Keyboard matrix

Clocks 8 Clock signals

Misc 2 Reset and Flash memory status signals

LEDs 3 Control signals for LEDs, (red/green)

PECL 4 Standard two pin analog PECL interface

Of the above mentioned signals, some are shared with the I/O ports of the ProASICPLUS

FPGA. The following table gives the overview of the shared signal ports.

Port Signal names Description

UIO1 sdram_data<63:32> User definable I/O port 1 that is connected with theUIO1 connector.

UIO2 PMC_P3<45:0> User definable I/O port 2 that is connected with theUIO2 connector.

UIO3 PMC_P4<45:0> User definable I/O port 3 that is connected with theUIO3 connector.

Additional information on the ProASICPLUS FPGA can be found in the correspondingspecification that is mentioned within the reference section.

For further information regarding programming tools, please refer to Actel's website athttp://www.actel.com.



3.1.2. ATMEL CPU

The following block diagram gives an overview of the ATMEL CPU.

The ATMEL AT91x40 family of controllers are ARM based. This controller uses theARM7DTMI macrocell and is complemented with a standard set of peripheral functions suchas Timers, UARTs, EBI and Interrupt Controller.

One special feature of this CPU that is used with the SDB development board are theflexibility to put the entire CPU into an inactive state (tri-state mode) by using one externaljumper (J7). When this jumper is activated, it enables the use of either one of the following:

• Use a separate external CPU board that is connected to the CPU extension connectors 1or 2.

• Use a ProASICPLUS FPGA with an integrated CPU macrocell as a system-on-chip design.

Additional information on the ATMEL AT91x40 CPU can be found in the correspondingspecification that is mentioned within the reference section.


Figure 10 - Block Diagram AT91X40 Series CPU ( 2000 ATMEL Corporation)

ARM7TDMI Core

Embedded ICE

Reset

EB

I: E

xter

nal B

us In

terf

ace

ASBController

Clock

AIC: AdvancedInterrupt Controller

AMBA Bridge

EBI UserInterface

TC: TimerCounter

TC0

TC1

TC2

USART0

USART1

2 PDCChannels

2 PDCChannels

PIO: Parallel I/O Controller

PS: Power Saving

Chip ID

WD: WatchdogTimer

APB

ASB

PIO

PIO

NRST

D0-D15

A1-A19A0/NLBNRD/NOENWR0/NWENWR1/NUBNWAITNCS0NCS1

P26/NCS2P27/NCS3P28/A20/CS7P29/A21/CS6P30/A22/CS5P31/A23/CS4

P0/TCLK0P3/TCLK1P6/TCLK2

P1/TIOA0P2/TIOB0

P4/TIOA1P5/TIOB1

P7/TIOA2P8/TIOB2

NWDOVF

TMSTDOTDI

TCK

MCKI

P25/MCKO

P12/FIQP9/IRQ0

P10/IRQ1P11/IRQ2

P13/SCK0P14/TXD0P15/RXD0

P20/SCK1P21/TXD1/NTRI

P22/RXD1

P16P17P18P19P23

P24/BMS

RAM

ROMor

Extended SRAM


3.1.2.1. Bus & I/O Signals

The CPU Bus signals that are used on the SDB development card are explained in thetable below.

Signal Name Width[# of pins]

Description Activation

cpu_d<15:0> 16 Data bus <High>

cpu_a<23:1> 23 Address bus <High>

cpu_cs<3:0>_n 4 Chip selects <High>

cpu_wr_n 1 Write enable <Low>

cpu_oe_n 1 Output enable <Low>

cpu_ub_n 1 Upper byte enable <Low>

cpu_lb_n 1 Lower byte enable <Low>

cpu_wait_n 1 CPU wait <Low>

cpu_firq_n 1 Fast interrupt request <Low>

cpu_irq_n<2:0> 3 Interrupt request <Low>

Total 52 The number of pins that are used for the CPU Bus

The following pins are used to control the operation of the SDB development board.These signals are also available on the CPU Extension 1 and 2 connectors for externalCPU boards.


Port Description

cpu_gpio_tms 1 P16 JTAG TMS

cpu_gpio_tck 1 P2 JTAG TCK

cpu_gpio_tdi 1 P17 JTAG TDI

cpu_gpio_tdo 1 P18 JTAG TDO

cpu_gpio_trst 1 P19 JTAG TRST

cpu_gpio_jtag_sel 1 P6 JTAG select

cpu_gpio_tx1 1 n/a UART 1, TX

cpu_gpio_rx1 1 n/a UART 1, RX

cpu_gpio_tx2 1 n/a UART 2, TX

cpu_gpio_rx2 1 n/a UART 2, RX

cpu_gpio_led1 1 P7 LED 4 (red)

cpu_gpio_led2 1 P13 LED 5 (green)

cpu_gpio_led3 1 P8 LED 6 (yellow)




Port Description

cpu_gpio_key<3:0> 4 P1,P23,P4,P5

Status of keyswitch buttons

cpu_gpio_flash_busy 1 P20 Flash status indicator (STS)

cpu_gpio_sda 1 P0 I2C sda

cpu_gpio_scl 1 P3 I2C scl



3.1.2.2. Memory Mapping

The following table gives an overview of the SDB development board memory mappingafter a hardware reset.

Address Peripheral Peripheral Select Size

0x00000000

0x00001FFF

On-Chip RAM N/A 8 kB

0x00002000

0x00FFFFFFReserved

0x01000000

0x01FFFFFF

Flash cpu_cs0_n 16 MB

0x02000000

0x02FFFFFF

External SRAM cpu_cs1_n 16 MB

0x03000000

0x037FFFFF

ProASICPLUS cpu_cs2_n 8 MB

0x03800000

0x03FFFFFF

GlueChip cpu_cs2_n 8 MB

0x04000000

0x04FFFFFF

User device cpu_cs3_n 16 MB

0x05000000

0xFFDFFFFFReserved

0xFFE00000

0xFFFFFFFF

On-chip peripherals N/A 2 MB

The memory mapping above provides the default values used by the SDB platform.Depending on your application requirements, the address space configuration can bemodified. For additional details please check either the software section of this manual orthe specification from ATMEL.



3.1.3. GlueChip

In order to provide additional functionality that doesn't put restrictions on the CPU or theProASICPLUS FPGA the SDB development board contains a specific FPGA thatimplements these independent functions.

3.1.3.1. Block Diagram

The figure below highlights the main building blocks of the GlueChip FGPA:

All internal blocks of the GlueChip are connected to the Microcontroller interface viainternal bus.

• RCK Generator:This block creates the running clock signal that is used for the in-system programmingof the ProASICPLUS FPGA on the SDB development board.This signal is configured through the CPU software.

• SRAM Decode:Here the SRAM chip-select signals for different memory banks are generated.

• LCD I/O:This block maps the LCD controller into the memory space of the CPU via the CPUbus. Additional control logic is included to simplify software interaction.

• CompactFlash Interface:This block mainly maps the external CompactFlash device into the memory space ofthe CPU. It also includes logic that allows the detection of the presence for a new CFdevice.


Figure 11 - GlueChip Block Diagram

UP

I

RCKGenerator

SRAMDecodeSRAM

Decode

CompactFlashInterface

InterruptController

UP

Ibu

s

CF Socket

GC_RCK BANK_SELSRAM_CONFIG

LC

DI/O

LCD

INT

2_N

DC SwitchVDDCF

VDDDCDC

GlueChip


• Interrupt Controller:This function provides the masking of all GlueChip interrupts on to one interrupt line.

• UPI (Microprocessor Interface):Provides the main interface to the CPU where all GlueChip signals are centralized. Inaddition it provides one register to control the power source for the DC-DC converters.

Note: This FPGA can not be re-programmed and remains fixed within the system.

3.1.3.2. Register Mapping

The internal register mapping of the GlueChip is described in the following table. Pleasenote that the CPU must be configured to access the GlueCip with one-wait-cycle(cpu_cs2_n).

GlueChip base address: 0x03800000

Chip select: cpu_cs2_n = <Low> and cpu_addr(23) = <High>

Interrupt Controller

Offset Register Description Access Reset

State

0x0000 InterruptEnable

Register

<High> enables a particular interrupt source.(Connected to the CPU interrupt IRQ2)

[0]: CCD: Card Change DetectionAn insertion or removal of aCompactFlash card is indicated.

[1]: LCD ReadyIndicates an LCD status change from<Busy> to <Ready>

R

R

0x00

0x00

0x0002 Interrupt StatusRegister

[1:0]: '0': no interrupt pending'1': interrupt pending

[1:0]: '0': no action'1': acknowledge pending interrupt

R

W

0x00

Note: The CPU interrupt IRQ2 signal is connected to the GlueChip. The softwareacknowledges the pending interrupt by writing '1' into the corresponding statusregister.



LCD I/O

Offset Register Description Access Reset

State

0x0010 LCD CommandRegister

[7:0]: Data/Command Byte to LCD

[8]: A0 is the Register Selection port (RS) ofthe LCD.

'0' ⇒ Commands

'1' ⇒ Characters

r/W

W

-

0x0012 LCD StatusRegister

[6:0]: LCD cursor address

[7]: '0' ⇒ LCD is ready for new command

'1' ⇒ LCD is busy

R -

0x00

0x0014 Auto Poll LCDStatus Enable

[0]: '0' ⇒ GC does not check LCD status

'1' ⇒ GC checks LCD status after eachwrite command

r/W 0x00

Note: If Auto Poll Status Enable = '0':The GlueChip does not check the LCD status.

If Auto Poll Status Enable ='1':Bit [6:0] in the LCD status register represent the current cursor address and Bit [7]shows the current LCD status. Additionally after each data transfer to the LCD aninterrupt is requested from the CPU when the status changes from <Busy> to<Ready>. Please note that Bit [1] in Interrupt Enable Register must be set.

CompactFlash Status and Configuration register

Offset Register Description Access ResetState

0x0020 CF StatusRegister

[0]: CF_WP

[1]: CF_CD1

[2]: CF_CD2

[3]: CF_VS1

[4]: CF_VS2

[5]: CF_RDYBSY_N

[6]: CF_BVD1

[7]: CF_BVD2

[8]: CF_WAIT_N

R

R

R

R

R

R

R

R

R

N/A

0x0022 CF HardwareReset Register

[0]: CF_RESET r/W 0x00




0x0024 Wait CycleConfiguration

Register

[4:0]: CF_COM_WAIT_CYCLEMin. number of wait cycles for memoryaccess of CF common area. After 4clock cycles the CF interface statemachine waits for the cf_wait_n = '1' orcf_bsyrdy_n = '1'.

[9:5]: CF_ATT_WAIT_CYCLEMin. number of wait cycles for memoryaccess of CF attributes

[10]: CF_WAIT_SIGNAL_SELSelect the source of wait signals fromthe CF

'0' ⇒ cf_wait_n

'1' ⇒ cf_rdybsy_n

r/W

r/W

r/W

0x04

0x09

0x00

0x0026 CFConfiguration

Register

[0]: CF_VDD_SELECT can be changedonly if CF_VDD_EBL is '0'

'0' ⇒ VDDCF = 3.3V

'1' ⇒ VDDCF = 5V

[1]: CF_VDD_EBL

'0' ⇒ CF power disabled

'1' ⇒ CF power enabled

[2]: CF_INTERFACE_EBLEnable CF Interface

'0' ⇒ CF is disabled and ports are in tri-state mode

'1' ⇒ CF is enabled

r/W

r/W

r/W

0x00

0x00

0x00

Note: The GlueChip-CompactFlash interface is designed for memory mode operation. Inthis mode the CF reset is active <High> and the software can read the CF statussignals by accessing the registers described above.



GlueChip internal registers


0x0040 GC_RCK Pre-Scaler.

A prescaler is used to have a system clockindependent reference clock of 1MHz:

f rck = f clksys /[2∗ prescale1]

[5:0]: Prescale register

r/W 0x00

0x0042 RCK generator [0]: '1' ⇒ Enable register

[1]: '0' ⇒ Disable register

r/W 0x00

0x0044 DCDCConvertercommandregister

[0]: '1' ⇒ Disable DC-DC power supply

'0' ⇒ Enable DC-DC power supply

r/W 0x00

0x0046 Configurationof assembled

SRAMs

[1:0]: "11" ⇒ 128kb x 8

"10" ⇒ 256kb x 8

"01" ⇒ 512kb x 8

R -

0x0048 GlueChipVersion

Register.

[7:0]: Revision of GlueChip

[15:8]:Version of GlueChip

R -

0x0050

0x0FFFReserved

0x1000

0x17FF

CF CommonMemory

This is the common memory section of theCompactFlash.

R/W -

0x1800

0x18FF

CF AttributeMemory

This is the attribute memory section of theCompactFlash.

R/W -

Note: Please see the CompactFlash reference guide for additional information on theprogramming and usage of the common and attribute memory areas.



3.1.3.3. Pin Description

The following table shows the pin description of the GlueChip FPGA as it applies to theSDB development board. The pins are grouped by their appropriate functionality.

CPU bus

Name Pincount

GlueChip Pin Description

CPU_D<15:0> 16

24, 23, 21, 18,17, 16, 15, 14,13, 12, 8, 7, 6,

5, 4, 3

CPU data bus

CPU_A<12:1> 12

130, 132, 133,134, 135, 136,137, 138, 139,141, 142, 143

CPU address bus

CPU_A<20:18> 3 122, 123, 124 CPU address bus

CPU_A<23> 1 121 CPU address bus

CPU_CS1_N 1 113 Chip select SRAM

CPU_CS2_N 1 114Chip select GlueChip andProASIC

CPU_WR_N 1 118 Write enable

CPU_OE_N 1 117 Output enable

CPU_UB_N 1 119 Upper byte enable

CPU_LB_N 1 120 Lower byte enable

CPU_WAIT_N 1 116 CPU wait

CPU_IRQ2 1 111 Interrupt request

LCD Interface

Name Pincount


DISP_D<7:0> 892, 93, 94, 95,96, 97,100, 103

LCD data

DISP_A0 1 106 LCD address

DISP_RWN 1 105 Read/ write not

DISP_CS 1 104 Chip select



SRAM

Name Pincount


BANK_SEL<1:0> 2 26, 25 SRAM bank select

SRAM_CONFIG<1:0> 2 107, 108 SRAM configuration

RCK

Name Pincount


GC_RCK 1 110 RCK clock for ProASIC

Power Switch

Name Pincount


EBL_DCDC_N 1 27 DC-DC controller enable

CF_EBL_33_N 1 32 CompactFlash 3.3v enable

CF_EBL_50_N 1 31 CompactFlash 5v enable

Global Signals

Name Pincount


RESET_N 1 126 Global reset

CLKA_TO_GC 1 125 Global Clock

CLK_TO_GC 1 60Global Clock (Dedicated input:Hard wire Clock HCLK)

TEST PORTS

Name Pincount


PRA / CF_BVD2 1 131Probe A / Can be connectedto CF_BVD2

PRB 1 54 Probe B

GC_TMS 1 9JTAG Test mode select(dedicated input)

GC_TCK 1 144 JTAG Test clock

GC_TRST 1 22 JTAG Reset



Name Pincount


GC_TDI 1 2 JTAG Test data input

GC_TDO 1 71 JTAG Test data output

CompactFlash

Name Pincount


CF_D<15:0> 16

77, 82, 84, 86,88, 34, 37, 39,78, 83, 85, 87,91, 38, 40, 42

Data

CF_A<10:0> 1174, 67, 65, 63,61, 55, 52, 50,

48, 46, 43Address

CF_CE1_N 1 76 Chip enable

CF_CE2_N 1 75 Chip enable

CF_VS1_N 1 72 Voltage select

CF_VS2_N 1 53 Voltage select

CF_RESET 1 51 Reset

CPU_GPIO_SDA /SDA_IORDN

1 69I2C SDA / can be connectedto CF IO read

CPU_GPIO_SCL /SCL_IOWRN

1 66I2C SCL / can be connectedto CF IO write

CF_WE_N 1 64 Write enable

CF_OE_N 1 70 Output enable

CF_RDYBSY_N 1 62 Ready/busy not

CF_WAIT_N 1 49 Wait indicator

CF_INPACK_N 1 47 INPACK

CF_REG_N 1 45 Register write enable

CV_BVD1 1 41 BVD1

CF_CSEL_N 1 59 Card select

CF_WP 1 35 Write protect

CF_CD1_N 1 112 Card detection 1

CF_CD2_N 1 33 Card detection 2



3.1.4. Flash

The SDB development board is designed for Intel's StrataFlash device family. The SDBboard logic can support memory sizes of 32Mb, 64Mb and 128Mb. The SDB developmentboard is by default delivered with a 32Mb Flash.

The Flash is 16-bit wide and supports byte access. It is connected to cpu_cs0_n which maps

the 16MB memory block between 0x01000000 and 0x01FFFFFF as explained in theMemory Mapping section of this document.

The following special enhancements have been made on the SDB development board.

• The Flash memory is placed in a socket. This allows the user to have different imagesof the system without the need for reprogramming.

• The Flash programming status indicator (STS) signal is available on the cpu_gpio andthe ProASICPLUS I/O port. Thereby allowing the system to control the reprogrammingcycle of the Flash memory.

Please verify with the Intel memory datasheet mentioned in the reference section fordetailed specifications about this chip.

3.1.5. SRAM

The SDB development board supports a total of 16-Mbit SRAM. The SRAM block aredivided into two banks each being 16-bit wide.

The chip select signal is connected to cpu_cs1_n which maps the 16MB memory block

between 0x02000000 and 0x02FFFFFF as explained in the Memory Mapping sectionearlier in this document.

The chip is manufactured in four different memory sizes while using the same packageinformation (SOJ-36, 400 mil). This allows the SDB development board to be assembledwith either one of the following memory types 128kx8, 256kx8 or 512kx8. The SDBdevelopment board is by default delivered with 4 x 512kx8 SRAMs.

In case the user wishes to upgrade the memory to a bigger size, the SRAM configurationlinks LK7 have to be changed as well. For further information please verify the IDTdatasheet mentioned in the reference section or contact Inicore for additional detail onsetting the LK7 configuration links.



3.2. Power Regulators

The SDB development board comes equipped with one external 5V power supply. However,the ProASICPLUS FPGA requires two additional voltage levels to be programmed within thesystem.

To provide this functionality, the SDB contains two on-board DC-DC converters. They arespecified as follow:

• VDDPP: +16.2V ±300mV @ 30mA

• VDDPN: -13.6V ±200mV @ 20mA

The following configuration is used to provide the necessary signals:

These DC-DC converters can be controlled using the register settings of the GlueChipFPGA. For additional information please refer to the GlueChip section above.


Figure 12 - DC-DC converter configuration

DC-DCVDDPP VDDPP

DC-DCVDDNP VDDNP

VDDDCDC

100k


3.3. Reset Logic

The next figure gives an indication of the reset logic and its connecting components.

A power-on-reset circuit is used to initialize the system upon power-up. As it can be seen inthe figure above, the reset logic controls the ProASICPLUS, the CPU and the GlueChip.

The following figure gives additional details on the implementation of the reset logic.

If desired, the ProASICPLUS FPGA could be implemented as a reset controller using a time-out watchdog. In that type of application the watchdog (ProASICPLUS) can pull the reset_nline to low in order to reset the CPU and GlueChip.

For the timing of the reset signal, please refer to the CPU and FPGA specifications.

Note: The reset line should be implemented using an open collector output so that theFPGA doesn't drive the reset_n line to high state.


Figure 13 - Reset Logic block diagram

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4


JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1


SDRAM DIMM

UIO 1

UIO 2

PM

CP

MC

PM

CP

MC

I2C

RT

C CP

U-B

us

Reset

CPU

GlueChipFPGA


Clock

ProASIC+

LVPECL

User Interface

Figure 14 - Reset Logic

POR

PA+

N25

GLUEchip

126

CPU

10k

reset_n


3.4. Prototyping Area

The following block diagram indicates the prototyping area that is integrated on the SDBdevelopment board.

As indicated above, the prototyping area is connected directly to the ProASICPLUS FPGA.

A 16x16 through-hole solder point area is provided for prototyping as indicated below.

The top row is connected to VDD33 and the bottom row of the prototyping area is connectedto GND.

In addition, there are two different types of signal path preconditioned on the SDBdevelopment board.


Figure 15 - Prototyping area block diagram

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4


JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1


SDRAM DIMM

UIO 1

UIO 2

PM

CP

MC

PM

CP

MC

I2C

RT

C CP

U-B

us

Reset

CPU

GlueChipFPGA


Clock

ProASIC+

LVPECL

User Interface

Figure 16 - Prototyping Area

16x16Solder points

<0><1>

<3><4><5>

<17>

<2>

pa_gpio1_<18:0>

VDD33

<18>

<16>GND

GND

GND


1. The upper half two rows on the left of the area are the signals named withpa_gpio1_<9:0>. They are directly connected between the ProASICPLUS FPGA and theprototyping area.

2. The lower half two rows on the left of the area with the signal names pa_gpio1_<18:10>are provisioned for high-speed I/O. This means that they have no vias on the signal pathbetween the ProASICPLUS and the prototyping area. In addition there are GND signalspositioned in between two high speed signals that terminate on the first left hand row.

All solder points are through-whole and allow to assemble parts on either side of the SDBdevelopment board.



3.5. CANbus

The figure below shows the CANbus connectivity of the SDB development board.

As indicated above, two standard CANbus ports are available on two external connectors.These ports are connected to the ProASICPLUS FPGA through an on-board 5V transceiver asindicated in the following figure.

Three jumper blocks are available to configure the CANbus interface (J5, J6 and J9). Theyare used as explained in the following tables.


Figure 18 - CANbus network

Figure 17 - CANbus block diagram

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4


JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1


SDRAM DIMM

UIO 1

UIO 2

PM

CP

MC

PM

CP

MC

I2C

RT

C CP

U-B

us

Reset

CPU

GlueChipFPGA


Clock

ProASIC+

LVPECL

User Interface

PA+

CANL

GND

CAN 1

CAN 2

J5_1

pa_can_rx1D26

D24

12

0R

0R

J5_2

*) level shifter

pa_can_tx1

rxd1

CANL

GND

J6_1

pa_can_rx2C26

D25

12

0R

0R

J6_2pa_can_tx2

Rxd2

J36

J35


3.5.0.1. J5: CAN Port 1 Configuration


None The ProASICPLUS FPGA pin is a GPIO pin ⊗

A-B The CAN1 RX signal is connected to the ProASICPLUS FPGA


None The ProASICPLUS FPGA pin is a GPIO pin

A-B The CAN1 TX signal is connected to the ProASICPLUS FPGA ⊗

3.5.0.2. J6: CAN Port 2 Configuration






A-B The CAN2 TX signal is connected to the ProASICPLUS FPGA

3.5.0.3. J9: CAN Bus Termination

The CAN bus network termination can be set using the J9_1/J9_2 jumpers as follow.


None The CAN bus 1 is not terminated ⊗

A-B The CAN bus 1 is terminated with 120Ω



A-B The CAN2 bus 2 is terminated with 120Ω

Note: The input cells of the ProASICPLUS FPGA are not 5V compliant, therefore two levelshifters were used in connection with the CANbus RX signals. If your CAN systemruns with 500kbaud or less, you might consider enabling the CAN transceiver'sslew rate control by exchanging R1 and R2 with a different value based on yourslew rate requirements and the specification of the 82C250.



3.6. LVPECL Differential Data

The block diagram of the LVPECL differential data interface can be seen below

One pair of standard SMA connectors are available to feed a data stream or an externalclock to the LVPECL inputs on the eastern side of the ProASICPLUS FPGA. The signal lines

are 50Ω impedance matched with their respective termination as indicated in the followingfigure.


Figure 19 - LVPECL block diagram

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4


JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1


SDRAM DIMM

UIO 1

UIO 2P

MC

PM

C

PM

CP

MC

I2CR

TC C

PU

-Bus

Reset

CPU

GlueChipFPGA


Clock

ProASIC+

LVPECL

User Interface

Figure 20 - LVPECL impedance match

P5

N4

100Ω

PA+


3.7. User Interface

The next figure indicates the components of the user interface.

The user interface is comprised of two elements:

1. One 2 lines x 16 characters intelligent LCD. It has an on-board LCD controller and drivercircuit. The device can display up to 160 characters (numericals, letters, symbols andKana letters), as well as up to eight custom designed characters. Please refer to theappropriate specification for further information.

2. Five mechanical keyswitches that allow entering and selecting information according tothe user programming. The five switches have the following functions using the pre-installed demo application:

KeySwitch Function

UP By pressing this switch once, the previous menu is displayed on the LCD

DOWN By pressing this switch once, the next menu is displayed on the LCD

CANCEL By pressing this switch once, the current menu choice is terminated

SELECT By pressing this switch once, the current menu is selected

RESET By pressing this switch once, the SDB development board is forced into ahardware reset

As the above figure indicates, the LCD is controlled by the GlueChip. In addition keyswitchevents such as pressing a button can be processed either by the CPU or the ProASICPLUS

FPGA.


Figure 21 - User Interface block diagram

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4


JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1


SDRAM DIMM

UIO 1

UIO 2P

MC

PM

C

PM

CP

MC

I2CR

TC C

PU

-Bus

Reset

CPU

GlueChipFPGA


Clock

ProASIC+

LVPECL

User Interface


3.8. Real Time Clock

The real time clock block is highlighted in the following figure.

The RTC (real time clock) is used to provide a time reference for the SDB developmentboard. The RTC IC is connected to the CPU and the ProASICPLUS through the I2C bus.

The RTC is operational even when the board is disconnected from an external power sourcesince it uses its own battery that is located underneath the LCD. The power source is a coincell Lithium battery with 3V,180mAh and Ref #: CR2032.

In order to replace the battery, the LCD has to be disconnected by removing the two screwsthat mount the unit onto the SDB development board.


Figure 22 - RTC block diagram

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4


JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1


SDRAM DIMM

UIO 1

UIO 2

PM

CP

MC

PM

CP

MC

I2C

RT

C CP

U-B

us

Reset

CPU

GlueChipFPGA


Clock

ProASIC+

LVPECL

User Interface


4 . E X TE R N A L H AR D W AR E

The SDB development board supports three hardware extensions via standardizedconnectors as indicated in the following figure.

The ProASICPLUS FPGA can be used to control the PMC and the SDRAM interface withappropriate programming, whereas the GlueChip is preprogrammed to interface theCompactFlash Card in memory mode.

4.1. Overview

These three standard interfaces that are supported with the SDB development board are asfollow:

1. One standard 3.3V PCI Mezzanine card interface where PTMC specifications are met fortelecommunication busses up to 50MHz. This includes such standards as UTOPIA level1 & 2, POS-PHY, RMII, IEEE 802.3 and others.The user can either connect the external hardware through the PMC connector bus or viaUIO2 and UIO3 directly to the ProASICPLUS FPGA.

2. Standardized 168-pin SDRAM DIMM connector where up to 256MB additional memorycan be provided for the ProASICPLUS FPGA.

3. A CompactFlash plug in interface that allows to connect one memory card with up to16MB. This memory card is used to hold STAPL files for ProASICPLUS FPGA in-circuitprogramming downloads.

© 2003, INICORE INC. External Hardware - Page 49

Figure 23 - External Hardware block diagram

CPU Sub-System

Flash

LCD

SRAMSRAM

SRAMSRAM

B1-4


JTA

G

UIO 4

UIO 3

Com

pact

Fla

sh

CPU Extension 2

CPU Extension 1


SDRAM DIMM

UIO 1

UIO 2

PM

CP

MC

PM

CP

MC

I2C

RT

C CP

U-B

us

Reset

CPU

GlueChipFPGA


Clock

ProASIC+

LVPECL

User Interface


4.2. PCI Mezzanine card (PMC)

Any standardized 3.3V PCI Mezzanine card can directly be plugged into the SDBdevelopment board. The SDB platform supports either 32-bit or 64-bit PMC hardware. If the32-bit PCI is used, bits <63:32> are usable through the UIO2 extension connector for otherpurposes. When using the 64-bit PCI, the UIO2 connector is not available for otherfunctions.

The host interface is also PTMC compatible so that PCI Telecom Mezzanine cards can beused.

Please refer to the PCI Mezzanine Card User Guide for additional information about how toconnect and operate PCM cards.

4.2.1. SDRAM-DIMM

A standard 168-pin DIMM connector is available to plug in an unbuffered SDRAM DIMM ifdesired. The SDRAM signals are directly connected to the ProASIC FPGA.

The I2C interface for the configuration PROM is connected to the local I2C bus of the SDBdevelopment board.

The following information is specific for the SDB development board usage:

• The serial PD base address is configured at: 0b10100000

• The serial PD write protect is not connected

• Registered DIMM can be configured using the provided SMLink

• The higher 4-bytes of the data bus are available on the UIO1 connector for systemswhere not the entire 64-bit wide memory is required. However, the user should verifythat the respective DQMB<7:4> bits are used accordingly within the system.

4.3. Compact Flash

The CompactFlash socket allows downloading different ProASICPLUS configurations. Usingthis technology provides a faster way to download ProASICPLUS configurations comparedwith using the conventional JTAG interface.

The CompactFlash controller resides inside the GlueChip FPGA on the SDB developmentboard. All required signals are directly connected to this FPGA. For additional registerinformation please refer to the GlueChip section of this document.

The following information are specific to the SDB development board:

• The socket is configured for 3.3V operation.

• The Life insertion function for CompactFlash Memory cards is supported

• Per default, the CompactFlash device is memory mapped into the CPU address spaceas indicated in the memory mapping section described above.

© 2003, INICORE INC. External Hardware - Page 50


5 . S OFT W AR E

This section gives an overview of the memory mapping, the RedBoot monitor, howapplication programs are downloaded and the functionality of the demo application that isincluded with the delivery of the SDB development board.

The following figure gives an overview of the software structure that is used for the SDBdevelopment board.

Two different applications are delivered with the SDB development board.

1. RedBoot monitor from RedHat with specific configuration files

2. Demo Application from Inicore, Inc. to exhibit the different features

Each application uses the eCos library for ARM processors during compilation in order tocreate downloadable software versions for the SDB.

For additional information on eCos or how to install the library for Windows environments,please refer to the RedHat website at http://sources.redhat.com/ecos/.

© 2003, INICORE INC. Software - Page 51

Figure 24 - Layer structure

SDB-750/1000 Hardware

Demo Application /RedBoot

eCos ARM


5.1. Program Memory Mapping

The following memory mapping indicates where the RedBoot monitor and the DemoApplication have been pre-installed on the SDB. Furthermore, it indicates where userapplications are located either for RAM or ROM memory execution.

The following table is only a section of the entire memory space. For additional details referto the memory mapping section under the ATMEL CPU above.

Address Peripheral Application

0x01000000

0x0101FFFF

Flash RedBoot Monitor

0x01020000

0x01FFFFFF

Flash User Application

0x02000000

0x02FFFFFF

RAM User Application

Note: After reset the program execution begins at the address 0x0.If the Cancel key is pressed during reset, the RedBoot Monitor will be executed at0x01000000. Otherwise the program at address 0x1020000 is executed.

Please do not modify the section between 0x1000000 and 0x1020000. This would corruptthe RedBoot Monitor what could make it impossible to load software upgrades withoutexternally reprogramming the Flash chip with the original RedBoot Monitor software.

5.2. RedBoot Monitor

The RedBoot Monitor is located in the Flash memory and is pre-loaded with the SDB. It canbe activated when pressing the Cancel key during a board Reset cycle.

The program provides the following features:

• Serial interface through UART1 connection with the PC

• Allows downloading new software on to the SDB and re-programming the software Flash

• Provides system functions such as read and write operations into specific memoryaddresses

• Allows to process ARM CPU in-circuit information for debugging purposes

• Provides GDB (GNU debugger) port using UART1



The RedBoot Monitor can be operated via PC and terminal software through the UART1interface.

The following commands are available in the RedBoot monitor:

• Manage aliases kept in FLASH memory

• Manage machine caches

• Display/switch console channel

• Compute a 32bit checksum [POSIX algorithm] for a range of memory

• Display (hex dump) a range of memory

• Manage FLASH images

• Manage configuration kept in FLASH memory

• Execute code at a location

• Help about help?

• Load a file

• Reset the system

• Display RedBoot version information

• Display (hex dump) a range of memory

In addition there is a help library included in the RedBoot monitor that provides detailedinformation for each function. It can be retrieved when typing help followed by thecommand.

Please refer to the RedBoot on-line help for additional details on the operation of thesecommands.



5.3. Application Installation Process

For the installation process of the application there is a straight forward process as indicatedin the following figure.

The application group has access to the *.bin files that contain the compiled program.

The following section describes the above process for the application group.


Figure 25 - Installation process

Application Mode

Activate RedBoot

Initiate terminal software

Type command

Download file

Program Flash

Execute Program


5.3.1. Application Mode Installation

This section gives step-by-step instructions on how to download an application when thefinalized *.bin file is available and the program location has been determined.

# User action System reaction

1. Link the SDB development board to the host PC by usingthe serial cable on the UART1 connector.

2. Start up terminal software (Minicom, HyperTerminal, etc.) Screen for portconfiguration appears

3. Configure the following protocol values:

• Baudrate: 38,400

• Data bits: 8

• Parity: None

• Stop bits: 1

• Flow Control: None

The terminal softwarewaits for activation

4. Press the Reset button on the SDB development boardwhile pushing the Cancel button to activate the RedBootMonitor

The RedBoot Monitorprompt "RedBoot>" willappear in the terminalwindow

5. Type the following command in the terminal window:

>load -r -m ymodem -b <ram address>

example: >load -r -m ymodem -b 0x2020000

After pressing return, theRedBoot Monitor waits forthe file to download

6. Send the file using the menu command and the ymodemprotocol for the transfer

• Transfer -> send File (make a note of the file lengthused for step 8 below)

The file is downloadedinto the SDBdevelopment board

7. If the program is compiled for RAM execution pleasecontinue with step 9, otherwise the file has to be written intothe Flash memory before execution.

8. Use the "fis" command to program the flash as follow:

>fis write -f <Flash addr> -b <ram addr> -l <file length>

example: >fis write -f 0x1020000 -b 0x2020000 -l 0x20000

The file is downloadedfrom the RAM into theFlash memory

9. Execute the program by typing the following command:

>go <address>

The program is executed

Note: For ROM execution the file has to be located on address 0x1020000 or higher.If the address area is locked, the Flash memory can't be programed. Type "helpfis" for more information.



5.4. Demo Application Overview

The following figure gives an overview of the pre-loaded demo application and itsfunctionality.


Figure 26 - Demo Application screen flow

Version

LED Set

ISP Configuration

RTC

ID Code

Monitor

Start Monitor

DC-DC on/off

RCK on/off

RCK precShow ISP

Status

Save

Count Down/Turn Off

Count up/Turn On

Up

Down

Show Date & Time

Save Status

Show LEDStatus

LED Off

LED On

Up

Down

LED4

LED5

LED6

Up

Down

UpDown

Show ID

SelectCancel

Select

Select

Select

Select

Select

Select

Select

Cancel

Cancel

Cancel

Cancel

Cancel

Select

Cancel

Cancel

Cancel

Cancel

Cancel

Up

Up

Up

Up

Down

Down

Down

Down

Down


Please refer to the separate application note of the demo design for additional informationon the programming of the demo application. This document can be downloaded from theInicore, Inc. website at http://www.inicore.com.

5.5. Addit ional Tools

Although the SDB development boards comes with many features and tools, the followingtwo additional investments would help the developer to be more efficient to speed up thedevelopment process.

Even though the ARM processor supports the use of the UART1 for debugging of CPUsoftware, it is highly recommended to purchase additional hardware such as the JEENIJTAG embedded ICE Ethernet Interface for ARM(http://www.epitools.com/products/arm/hardware/jeeni.shtml) in order to speed up theprocess.

With the current release of the SDB development board software V1.1, autonomous in-system programming of the ProASICPLUS FPGA is not yet supported. In order to program theProASICPLUS FPGA an external FlashPro programmer from Actel Corporation can be used.For additional information please refer to the FlashPro programmer product specification atActel's website. (http://www.actel.com/products/tools/flashpro/index.html)



6 . CON FIG URATIO N

This section contains the technical details of the SDB development board. The jumpersettings are explained within the document as well at their appropriate locations, whereasthe assembly options are for your information only.

For additional questions, please refer to the Inicore, Inc. website at www.inicore.com

6.1. Jumper Settings

This section summarizes the jumper settings for the SDB development board.

6.1.1. J1: JTAG Source Select

J1 Function Setting

None The external JTAG header is the JTAG source for the SDB ⊗

A-B The CPU is the JTAG source

6.1.2. J2: JTAG PCI Mezzanine card

J2 Function Setting

A-B The PMC TAP controller is NOT part of the JTAG chain.(TDI/TDO shortcut for the JTAG is activated)

⊗

B-C The PMC TAP controller is part of the JTAG chain.

(TDI/TDO shortcut for the JTAG is deactivated)

6.1.3. J3: UART 1 Source Select



B-C The ProASICPLUS UART port is used for receiving signals



B-C The ProASICPLUS UART port is used for transmitting signals

© 2003, INICORE INC. Configuration - Page 58


6.1.4. J4: UART 2 Source Select



B-C The ProASICPLUS pre-configured UART port is used forreceiving signals



B-C The ProASICPLUS pre-configured UART port is used fortransmitting signals

6.1.5. J5: CAN Port 1 Configuration







6.1.6. J6: CAN Port 2 Configuration









6.1.7. J7: CPU Disable

J7 Function Setting

None The CPU is operational ⊗

A-B The CPU is disabled

6.1.8. J8: Clock Jumpers


A-B The Clock buffer 1 is driven by the clk1_from_pa signal.



A-B The Clock buffer 2 is driven by the clk2_from_pa signal



A-B The Clock buffer 3 is driven by the clk_to_cpu_from_pa signal


6.1.9. J9: CAN Bus Termination



A-B The CAN bus 1 is terminated with 120Ω



A-B The CAN2 bus 2 is terminated with 120Ω



6.2. Options

The following tables describe different options for the SDB development board. These

options are achieved by using 0Ω resistors to specify the functionality that is describedwithin the tables.

Note: Modifying the board with a soldering iron voids the warranty of the SDB.

6.2.1. LK1: JTAG PMC Enable

The JTAG control signal are available on the mezzanine card but can be disconnectedby changing the following settings if desired.

LK1_1 Function Setting

A-B The JTAG-TMS signal of the mezzanine card is tied <High> ⊗

B-C The JTAG-TMS signal is connected to the mezzanine card's

TMS signal.


A-B The JTAG-TCK signal of the mezzanine card is tied <High>

B-C The JTAG-TCK signal is connected to the mezzanine card's

TCK signal.⊗


A-B The JTAG-TRST signal of the mezzanine card is tied <High>

B-C The JTAG-TRST signal is connected to the mezzanine

card's TRST signal.⊗

6.2.2. LK2: JTAG GlueChip FPGA Enable

The GlueChip's TAP controller can be included in the JTAG chain if desired.


A-B The JTAG-TMS signal of the GlueChip FPGA is tied <High> ⊗

B-C The JTAG-TMS signal is connected to the GlueChip FPGA'sTMS signal




A-B The GlueChip's TAP controller is NOT included in the JTAGchain (JTAG-TDI/TDO shortcut is activated)

⊗

B-C The GlueChip's TAP controller is included in the JTAG chain(JTAG-TDI/TDO shortcut is disconnected)

6.2.3. LK3: Flash Byte Mode Select

To select the byte mode option of the Intel Flash memory. This option can be used whena 8-bit CPU core is integrated into the ProASICPLUS FPGA design.

LK3 Function Setting

A-B The 16-bit mode is enabled for the Flash memory ⊗

B-C The 8-bit mode is enabled for the Flash memory

6.2.4. LK4: DC-DC Converter

Instead of using the on-board DC-DC converters for the two programming voltages of theProASICPLUS FPGA, an external power supply can be used.


None The external programming voltage VDDPP is used.

A-B The VDDPP signal is generated by the on-board DC-DCconverters

⊗


None The external programming voltage VDDNP is used.

A-B The VDDNP signal is generated by the on-board DC-DCconverters

⊗

Note: The power source for the DC-DC converters can be turned off using the GlueChipregisters.



6.2.5. LK5: Registered SDRAM DIMM Configuration

This configuration option is used to define the type of SDRAM modules. The choices areeither select buffered or registered mode. This SMLink option is left open for unbufferedDIMMs.


None Select unbuffered DIMM mode ⊗

A-B Select buffered DIMM mode

B-C Select registered DIMM mode

6.2.6. LK6: BVD2 Enable

The PRA port from the GlueChip can be connected to the CompactFlash BVD2 port.


None The PRA port is defined as a test port ⊗

A-B The PRA port is defined as an input port and connected tothe CF_BVD2 signal

6.2.7. LK7: SRAM Configuration

The SDB development board can be assembled with different SRAM devices. Using thefollowing table, the respective decoding logic can be selected.

LK7_1 LK7_2 Function Setting

A-B A-B Configured for 128kx8 SRAM

A-B B-C Configured for 256kx8 SRAM

B-C A-B Configured for 512kx8 SRAM ⊗

Note: All banks have to be assembled with the same type of SRAM devices. However, itis possible to only assemble bank 0 and leave bank 1 unused.

6.2.8. LK8, LK9: ProASICP L U S Power

These two SMLinks are used to provide the ProASICPLUS FPGA with optional power levelsand they can not be reconfigured.



6.2.9. LK10: I2C / CF_IO signals

With these SMLinks, it is possible to select which signals are connected to GlueChip.


A-B The CPU_GPIO_SCL signal is connected to pin 64 of theGlueChip

B-C The CF_IOWR_N signal is connected to pin 64 of theGlueChip

⊗


A-B The CPU_GPIO_SDA signal is connected to pin 65 of theGlueChip

B-C The CF_IORD_N signal is connected to pin 65 of theGlueChip

⊗

6.2.10. LK11: Boot-Mode Select


A-B The CPU boots from a 8-bit external flash memory

B-C The CPU boots from a 16-bit external flash memory ⊗

6.2.11. LK12: Shutdown - INTC Select


A-B The DC-DC converters on the mezzanine board are drivenby the GlueChip

⊗

B-C The PMC_INTC_N signal is linked to the PMC connector

6.2.12. LK13: RCK - INTD Select


None The PMC_INTD_N signal is linked to the PMC connector

A-B The RCK signal that is used during the ProASICPLUS FPGAprogramming cycle is generated by the PMC.

⊗



6.3. Connector Definitions

The following tables provide a summary of the connector signal definitions as they pertain tothe SDB development board.

6.3.1. Power

6.3.2. PMC connectors

The following four connectors describe the pinout for the PMC connectors.

6.3.2.1. J11: PMC-Jn1

Signal Pin Pin Signal Signal Pin Pin

Signal

PMC_TCK 1 2 VDDN12 PMC_FRAME_N 33 34 GND

GND 3 4 PMC_INTA_N GND 35 36 PMC_IRDY_N

PMC_INTB_N 5 6 INTCN_SHDN PMC_DEVSEL_N 37 38 VDD50

PMC_BM1_N 7 8 VDD50 GND 39 40 PMC_LOCK_N

PMC_INTD_N 9 10 N/C CPU_GPIO_SCL 41 42 CPU_GPIO_SDA

GND 11 12 VDD33 PMC_PAR 43 44 GND

CLK_TO_PMC 13 14 GND VDD33 45 46 PMC_AD15

GND 15 16 PMC_GNT_N PMC_AD12 47 48 PMC_AD11

PMC_REQ_N 17 18 VDD50 PMC_AD9 49 50 VDD50

VDD33 19 20 PMC_AD31 GND 51 52 PMC_CBE0_N

PMC_AD28 21 22 PMC_AD27 PMC_AD6 53 54 PMC_AD5

PMC_AD25 23 24 GND PMC_AD4 55 56 GND

GND 25 26 PMC_CBE3_N VDD33 57 58 PMC_AD3

PMC_AD22 27 28 PMC_AD21 PMC_AD2 59 60 PMC_AD1

PMC_AD19 29 30 VDD50 PMC_AD0 61 62 VDD50

VDD33 31 32 PMC_AD17 GND 63 64 PMC_REQ64_N


Figure 27 - Power connector

+ 12V (optional)- 12V (optional)

GND+ 5V


6.3.2.2. J12: PMC-Jn2

Signal Pin Pin Signal Signal Pin Pin SignalVDD12 1 2 PMC_TRST GND 33 34 N/C

PMC_TMS 3 4 PMC_TDO PMC_TRDY_N 35 36 VDD33

PMC_TDI 5 6 GND GND 37 38 PMC_STOP_N

GND 7 8 N/C PMC_PERR_N 39 40 GND

N/C 9 10 N/C VDD33 41 42 PMC_SERR_N

PMC_BM2_N 11 12 VDD33 PMC_CBE1_N 43 44 GND

PMC_RST_N 13 14 PMC_BM3_N PMC_AD14 45 46 PMC_AD13

VDD33 15 16 PMC_BM4_N PMC_M66E 47 48 PMC_AD10

PCM_PME_N 17 18 GND PMC_AD8 49 50 VDD33

PMC_AD30 19 20 PMC_AD29 PMC_AD7 51 52 N/C

GND 21 22 PMC_AD26 VDD33 53 54 N/C

PMC_AD24 23 24 VDD33 N/C 55 56 GND

PMC_IDSEL 25 26 PMC_AD23 N/C 57 58 N/C

VDD33 27 28 PMC_AD20 GND 59 60 N/C

PMC_AD18 29 30 GND PMC_ACK64_N 61 62 VDD33

PMC_AD16 31 32 PMC_CBE2_N GND 63 64 N/C

6.3.2.3. J13: PMC-Jn3

Signal Pin Pin Signal Signal Pin Pin SignalPMC_J3_1 1 2 GND GND 33 34 PMC_AD48

GND 3 4 PMC_CBE7_N PMC_AD47 35 36 PMC_AD46

PMC_CBE6_N 5 6 PMC_CBE5_N PMC_AD45 37 38 GND

PMC_CBE4_N 7 8 GND PMC_VIO3 39 40 PMC_AD44

PMC_VIO1 9 10 PMC_PAR64 PMC_AD43 41 42 PMC_AD42

PMC_AD63 11 12 PMC_AD62 PMC_AD41 43 44 GND

PMC_AD61 13 14 GND GND 45 46 PMC_AD40

GND 15 16 PMC_AD60 PMC_AD39 47 48 PMC_AD38



PMC_VIO2 21 22 PMC_AD56 PMC_AD35 53 54 PMC_AD34


PMC_AD53 25 26 GND PMC_VIO4 57 58 PMC_AD32

GND 27 28 PMC_AD52 PMC_J3_2 59 60 PMC_J3_3

PMC_AD51 29 30 PMC_AD50 PMC_J3_4 61 62 GND

PMC_AD49 31 32 GND GND 63 64 PMC_J3_5



6.3.2.4. J14: PMC-Jn4

Signal Pin Pin Signal Signal Pin Pin SignalPMC_UIO1 1 2 GND GND 33 34 PMC_UIO24

GND 3 4 PMC_UIO2 PMC_UIO26 35 36 PMC_UIO25

PMC_UIO4 5 6 PMC_UIO3 PMC_UIO27 37 38 GND

PMC_UIO5 7 8 GND PMC_UIO29 39 40 PMC_UIO28

PMC_UIO6 9 10 PMC_UIO7 PMC_UIO31 41 42 PMC_UIO30


PMC_UIO10 13 14 GND GND 45 46 PMC_UIO33










6.3.3. J15 : I2C

The I2C system bus is available on a standard 4-pin header.

Signal Pin Pin SignalVDD33 1 2 CPU_SDA

CPU_SCL 3 4 GND



6.3.4. J16: JTAG ProASICP L U S

This connector is configured for the ProASICPLUS FPGA.

Signal Pin Pin SignalN/C 1 2 N/C

N/C 3 4 N/C

N/C 5 6 N/C

GND 7 8 N/C

GND 9 10 GND

N/C 11 12 TCK

N/C 13 14 TDI

N/C 15 16 TDO

N/C 17 18 TMS

N/C 19 20 RCK

N/C 21 22 TRST

N/C 23 24 N/C

N/C 25 26 N/C

6.3.5. J17: JTAG ProASIC

This connector is only available when the board is assembled with a ProASIC device.

6.3.6. J18: JTAG-ICE

An ARM-standard 20-pin box header is provided for the CPU internal JTAG-ICE port.

Signal Pin Pin SignalVDD33 1 2 VDD33

N/C 3 4 GND

JI_TDI 5 6 GND

JI_TMS 7 8 GND

JI_TCK 9 10 GND

JI_TCK 11 12 GND

JI_TDO 13 14 GND

JI_TRST 15 16 GND

N/C 17 18 GND

N/C 19 20 GND



6.3.7. J19: SDRAM DIMM (PC100)

Pin Signal Pin Signal Pin Signal Pin Signal1 GND 43 GND 85 GND 127 GND

2 SD_DQ0 44 N/C 86 SD_DQ32 128 SD_CKE

3 SD_DQ1 45 SD_S2_N 87 SD_DQ33 129 SD_S3_N

4 SD_DQ2 46 SD_DQMB2 88 SD_DQ34 130 SD_DQMB6

5 SD_DQ3 47 SD_DQMB3 89 SD_DQ35 131 SD_DQMB7

6 VDD33 48 N/C 90 VDD33 132 SD_A13

7 SD_DQ4 49 VDD33 91 SD_DQ36 133 VDD33

8 SD_DQ5 50 N/C 92 SD_DQ37 134 N/C

9 SD_DQ6 51 N/C 93 SD_DQ38 135 N/C

10 SD_DQ7 52 N/C 94 SD_DQ39 136 N/C

11 SD_DQ8 53 N/C 95 SD_DQ40 137 N/C

12 GND 54 GND 96 GND 138 GND

13 SD_DQ9 55 SD_DQ16 97 SD_DQ41 139 SD_DQ48




17 SD_DQ13 59 VDD33 101 SD_DQ45 143 VDD33

18 VDD33 60 SD_DQ20 102 VDD33 144 SD_DQ52

19 SD_DQ14 61 N/C 103 SD_DQ46 145 N/C

20 SD_DQ15 62 N/C 104 SD_DQ47 146 N/C

21 N/C 63 SD_CKE 105 N/C 147 J_REGE

22 N/C 64 GND 106 N/C 148 GND

23 GND 65 SD_DQ21 107 GND 149 SD_DQ53

24 N/C 66 SD_DQ22 108 N/C 150 SD_DQ5425 N/C 67 SD_DQ23 109 N/C 151 SD_DQ55

26 VDD33 68 GND 110 VDD33 152 GND

27 SD_WE0_N 69 SD_DQ24 111 SD_CAS_N 153 SD_DQ56

28 SD_DQMB0 70 SD_DQ25 112 SD_DQMB4 154 SD_DQ57

29 SD_DQMB1 71 SD_DQ26 113 SD_DQMB5 155 SD_DQ58

30 SD_S0_N 72 SD_DQ27 114 SD_S1_N 156 SD_DQ59

31 N/C 73 VDD33 115 SD_RAS_N 157 VDD33

32 GND 74 SD_DQ28 116 GND 158 SD_DQ60

33 SD_A0 75 SD_DQ29 117 SD_A1 159 SD_DQ61

34 SD_A2 76 SD_DQ30 118 SD_A3 160 SD_DQ62

35 SD_A4 77 SD_DQ31 119 SD_A5 161 SD_DQ63

36 SD_A6 78 GND 120 SD_A7 162 GND

37 SD_A8 79 CLK_SD2 121 SD_A9 163 CLK_SD2

38 SD_A10 80 N/C (WP) 122 SD_BA0 164 N/C

39 SD_BA1 81 N/C 123 SD_A11 165 GND (SA0)

40 VDD33 82 SD_SDA 124 VDD33 166 GND (SA1)

41 VDD33 83 SD_SCL 125 CLK_SD1 167 GND (SA2)

42 CLK_SD1 84 VDD33 126 SD_A12 168 VDD33



6.3.8. J20, J21: CPUext 1 , CPUext 2 respectivelyTwo 80-pin headers that can be used to connect an external memory extension daughtercard or to connect a different CPU to the SDB development board.

Signal Pin Pin SignalGND 1 2 GND

CPU_WR_N 3 4 CPU_UB_N

CPU_OE_N 5 6 CPU_WAIT_N

CLK_FROM_CPU 7 8 CLK_TO_EXT1

CPU_CS0_N 9 10 CPU_CS1_N


VDD33 13 14 RESET_N

CPU_LB_N 15 16 CPU_A1

CPU_A2 17 18 CPU_A3

CPU_A4 19 20 CPU_A5

CPU_A6 21 22 CPU_A7

GND 23 24 GND

CPU_A8 25 26 CPU_A9

CPU_A10 27 28 CPU_A11

CPU_A12 29 30 CPU_A13

CPU_A14 31 32 CPU_A15

VDD33 33 34 VDD33

CPU_A16 35 36 CPU_A17

CPU_A18 37 38 CPU_A19

CPU_A20 39 40 CPU_A21

CPU_A22 41 42 CPU_A23

GND 43 44 GND

CPU_D0 45 46 CPU_D1

CPU_D2 47 48 CPU_D3

CPU_D4 49 50 CPU_D5

CPU_D6 51 52 CPU_D7

VDD33 53 54 VDD33

CPU_D8 55 56 CPU_D9

CPU_D10 57 58 CPU_D11

CPU_D12 59 60 CPU_D13

CPU_D14 61 62 CPU_D15

GND 63 64 GND

CPU_GPIO_IRQ_0 65 66 CPU_GPIO_IRQ_1

CPU_GPIO_IRQ_2 67 68 CPU_GPIO_FIRQ

CPU_GPIO_SDA 69 70 CPU_GPIO_SCL

CPU_GPIO_TMS 71 72 CPU_GPIO_TDI

CPU_GPIO_TCK 73 74 CPU_GPIO_TDO

CPU_GPIO_TRST 75 76 CPU_GPIO_KEY_0

CPU_GPIO_KEY_1 77 78 CPU_GPIO_KEY_2

CPU_GPIO_KEY_3 79 80 CPU_GPIO_FLASH_BUSY



6.3.9. J22: Display Connector

A 1x14 header connects the GlueChip directly to the LCD module.

Signal Pin Pin SignalGND 1 2 VDD50

VDD50 3 4 DISP_A0

DISP_RWN 5 6 DISP_CS

DISP_D0 7 8 DISP_D1

DISP_D2 9 10 DISP_D3



6.3.10. J23, J24: LVPECL Data

Two SMA footprints are provided to connect an external differential LVPECL high speeddata or clock source.

6.3.10.1. J23: EPECLIN, Positive PECL

Pin Signal1 GND

2 EPECLIN

6.3.10.2. J24: EPECLREF, Negative PECL

Pin Signal1 GND

2 EPECLREF



6.3.11. J25: CompactFlash

The CompactFlash connector is configured for 3.3V operation. The default operating modeis 'memory mapped' which defines the port names accordingly.

Signal Pin Pin SignalGND 1 26 CF_CD1_N

CF_D3 2 27 CF_D11

CF_D4 3 28 CF_D12

CF_D5 4 29 CF_D13

CF_D6 5 30 CF_D14

CF_D7 6 31 CF_D15

CF_CE1_N 7 32 CF_CE2_N

CF_A10 8 33 CF_VS1

CF_OE_N 9 34 CF_IORD_N

CF_A9 10 35 CF_IOWR_N

CF_A8 11 36 CF_WE_N

CF_A7 12 37 CF_RDYBSY_N

VDDCF 13 38 VDDCF

CF_A6 14 39 CF_CSEL_N

CF_A5 15 40 CF_VS2

CF_A4 16 41 CF_RESET

CF_A3 17 42 CF_WAIT_N

CF_A2 18 43 CF_INPACK_N

CF_A1 19 44 CF_REG_N

CF_A0 20 45 CF_BVD2

CF_D0 21 46 CF_BVD1

CF_D1 22 47 CF_D8

CF_D2 23 48 CF_D9

CF_WP 24 49 CF_D10

CF_CD1_N 25 50 GND

6.3.12. J26: User IO 1

The upper 32-bit of the 64-bit SDRAM signals are available on connector UIO1

Signal Pin Pin SignalGND 1 2 SD_DQ32

SD_DQ33 3 4 SD_DQ34

SD_DQ35 5 6 SD_DQ36

GND 7 8 SD_DQ37

SD_DQ38 9 10 SD_DQ39

SD_DQ40 11 12 SD_DQ41

GND 13 14 SD_DQ42

SD_DQ43 15 16 SD_DQ44



Signal Pin Pin SignalSD_DQ45 17 18 SD_DQ46

GND 19 20 SD_DQ47

SD_DQ48 21 22 SD_DQ49

SD_DQ50 23 24 SD_DQ51

GND 25 26 SD_DQ52

SD_DQ53 27 28 SD_DQ54

SD_DQ55 29 30 SD_DQ56

GND 31 32 SD_DQ57

SD_DQ58 33 34 SD_DQ59

SD_DQ60 35 36 SD_DQ61

GND 37 38 SD_DQ62

SD_DQ63 39 40 GND

6.3.13. J27: User IO 2

The signal mapping on this connector is compatible to the PTMC J3 pin mapping.

Signal Pin Pin Signal Signal Pin Pin SignalPMC_J3_1 1 2 GND GND 33 34 PMC_AD48

GND 3 4 PMC_CBE7_N PMC_AD47 35 36 PMC_AD46

PMC_CBE6_N 5 6 PMC_CBE5_N PMC_AD45 37 38 GND

PMC_CBE4_N 7 8 GND PMC_VIO3 39 40 PMC_AD44

PMC_VIO1 9 10 PMC_PAR64 PMC_AD43 41 42 PMC_AD42



GND 15 16 PMC_AD60 PMC_AD39 47 48 PMC_AD38



PMC_VIO2 21 22 PMC_AD56 PMC_AD35 53 54 PMC_AD34


PMC_AD53 25 26 GND PMC_VIO4 57 58 PMC_AD32

GND 27 28 PMC_AD52 PMC_J3_2 59 60 PMC_J3_3

PMC_AD51 29 30 PMC_AD50 PMC_J3_4 61 62 GND

PMC_AD49 31 32 GND GND 63 64 PMC_J3_5



6.3.14. J28: User IO 3

The signal mapping on this connector is compatible to the PTMC J4 pin mapping.

Signal Pin Pin Signal Signal Pin Pin

Signal

















6.3.15. J29: User IO 4

The UIO4 represents the GPIO port 2 of the ProASICPLUS FPGA.

Signal Pin Pin SignalVDD33 1 2 GND

PA_GPIO2_0 3 4 PA_GPIO2_1




PA_GPIO2_8 11 12 GND

VDD33 13 14 GND



6.3.16. J30, J31, J32: Debug Header

The following three connectors can be used for an ICE to connect directly to the CPU.

6.3.16.1. J30: CPU_CTRL

Signal Pin Pin SignalGND 1 2 CPU_LB_N

CPU_WR_N 3 4 CPU_UB_N

CPU_OE_N 5 6 CPU_WAIT_N



CPU_IRQ0 11 12 CPU_IRQ1

CPU_IRQ2 13 14 CPU_FIRQ

6.3.16.2. J31: CPU_Addr

Signal Pin Pin SignalGND 1 2 CPU_A1

CPU_A2 3 4 CPU_A3

CPU_A4 5 6 CPU_A5

CPU_A6 7 8 CPU_A7

CPU_A8 9 10 CPU_A9

CPU_A10 11 12 CPU_A11

CPU_A12 13 14 CPU_A13

CPU_A14 15 16 CPU_A15

CPU_A16 17 18 CPU_A17

CPU_A18 19 20 CPU_A19

CPU_A20 21 22 CPU_A21

CPU_A22 23 24 CPU_A23

6.3.16.3. J32: CPU_Data

Signal Pin Pin SignalGND 1 2 GND

CPU_D0 3 4 CPU_D1

CPU_D2 5 6 CPU_D3

CPU_D4 7 8 CPU_D5

CPU_D6 9 10 CPU_D7

CPU_D8 11 12 CPU_D9

CPU_D10 13 14 CPU_D11

CPU_D12 15 16 CPU_D13

CPU_D14 17 18 CPU_D15

GND 19 20 GND



6.3.17. J33, J34: UART 1, UART 2 respectively

The next figure indicates the front view pinout of the DB9 female connector:

The pins in the following table are provided with signals on the connector:

Pin Signal Description

2 uart_rx Receive data

3 uart_tx Transmit data

5 GND Signal ground

6.3.18. J35, J36: CAN 1, CAN 2 respectively

The next figure shows the front view pinout of the DB9 male connector:

The pins in the following table are provided with signals on the connector:

Pin Signal Description

2 can_l CAN_L bus line, dominant <Low>

3 GND Ground

7 can_h CAN_H bus line, dominant <High>

6.3.19. J37, J38, J39, J40, J41: Local Power Connectors

These 2-pin connectors are connected to the different power suppliers on the board. Pinone of each is connected to -12V, +12V, 5V, 3.3V and 2.5V respectively, pin two isconnected to ground.


Figure 29 - CANbus connector pinout

(Front View)

Figure 28 - UART connector pinout

(Front View)

1

9

1

9


6.4. Test Points

There are 14 test points on the board that allow easy access to several signals.

Test Point Source Color

TP1 GlueChip PRA yellow

TP2 GlueChip PRB yellow

TP3, TP4, TP5, TP6, TP7 OSC1, CLK1_TO_PA, OSC2,CLK2_TO_PA, CLK_TO_CPU

yellow

TP8, TP9, TP10, TP11, TP12, TP13 GND black

6.5. Prototyping Area

The following table indicates the pin assigment between the ProASICPLUS FPGA and theprototyping area of the SDB development board.

PROTOPIN

Signal name

0 PA_GPIO1_0

1 PA_GPIO1_1

2 PA_GPIO1_2

3 PA_GPIO1_3

4 PA_GPIO1_4

5 PA_GPIO1_5

6 PA_GPIO1_6

7 PA_GPIO1_7

8 PA_GPIO1_8

9 PA_GPIO1_9

11 PA_GPIO1_10(GL)

13 PA_GPIO1_11

15 PA_GPIO1_12

17 PA_GPIO1_13

19 PA_GPIO1_14

21 PA_GPIO1_15

23 PA_GPIO1_16

25 PA_GPIO1_17

27 PA_GPIO1_18



6.6. SDB-750/1000 connectivity table

The following tables provides the pin-to-pin association between the ProASICPLUS FPGA andits connecting devices.

6.6.1. CPU

PROASICPLUS

PIN

CPUPIN

Signal name

P23 31 CPU_D0

P22 32 CPU_D1

R24 33 CPU_D2

R23 34 CPU_D3

R22 35 CPU_D4

T24 37 CPU_D5

T23 38 CPU_D6

T22 39 CPU_D7

U26 40 CPU_D8

U25 41 CPU_D9

U24 42 CPU_D10

U23 43 CPU_D11

U22 45 CPU_D12

V26 46 CPU_D13

V25 47 CPU_D14

V24 48 CPU_D15

V23 3 CPU_A1

V22 4 CPU_A2

W26 5 CPU_A3

W25 6 CPU_A4

W24 7 CPU_A5

W23 8 CPU_A6

Y26 9 CPU_A7

Y25 11 CPU_A8

Y24 12 CPU_A9

Y23 13 CPU_A10

AA26 14 CPU_A11

AA25 15 CPU_A12

AA24 16 CPU_A13

AA23 17 CPU_A14

AB26 20 CPU_A15

PROASICPLUS

PIN

CPUPIN

Signal name

AB25 21 CPU_A16

AB24 22 CPU_A17

AB23 23 CPU_A18

AC26 24 CPU_A19

AD26 25 CPU_A20

AC25 26 CPU_A21

AD25 29 CPU_A22

AF24 30 CPU_A23

AD23 97 CPU_CS0_N

AE22 98 CPU_CS1_N

AF22 99 CPU_CS2_N

AE21 100 CPU_CS3_N

AF21 60 CPU_IRQ0

AC20 63 CPU_IRQ1

AD20 64 CPU_IRQ2

AE20 66 CPU_FIRQ

AF20 93 CPU_WR_N

AC19 92 CPU_OE_N

AD19 77 CPU_UB_N

AE19 1 CPU_LB_N

AF19 96 CPU_WAIT_N

6.6.2. PMC J1 & J2

PROASICPLUS

PIN

PMC

PINSignal name

E2 J1/4 PMC_INTA_N

E1 J1/6 PMC_INTC_N

F4 J1/5 PMC_INTB_N

F3 J1/7 PMC_BM1_N



PROASICPLUS

PIN

PMC

PINSignal name

F2 J1/9 PMC_INTD_N

F1 J2/11 PMC_BM2_N

G4 J2/14 PMC_BM3_N

G3 J2/13 PMC_RST_N

G2 J2/16 PMC_BM4_N

G1 J1/16 PMC_GNT_N

H4 J2/17 PMC_PME_N

H3 J1/17 PMC_REQ_N

H2 J2/20 PMC_AD29

H1 J2/19 PMC_AD30

J5 J1/20 PMC_AD31

J4 J2/22 PMC_AD26

J3 J1/22 PMC_AD27

J2 J1/21 PMC_AD28

J1 J2/23 PMC_AD24

K5 J1/23 PMC_AD25

K4 J2/26 PMC_AD23

K3 J2/25 PMC_IDSEL

K2 J1/26 PMC_CBE3_N

K1 J2/28 PMC_AD20

L5 J1/28 PMC_AD21

L4 J1/27 PMC_AD22

L3 J2/29 PMC_AD18

L2 J1/29 PMC_AD19

L1 J2/32 PMC_CBE2_N

M5 J2/31 PMC_AD16

M4 J1/32 PMC_AD17

M3 J1/33 PMC_FRAME_N

N2 J2/35 PMC_TRDY_N

M1 J1/36 PMC_IRDY_N

N1 J2/38 PMC_STOP_N

P1 J1/37 PMC_DEVSEL_N

P2 J2/39 PMC_PERR_N

P3 J1/40 PMC_LOCK_N

P4 J2/42 PMC_SERR_N

R1 J2/43 PMC_CBE1_N

R2 J1/43 PMC_PAR

R3 J2/46 PMC_AD13

PROASICPLUS

PIN

PMC

PINSignal name

R4 J2/45 PMC_AD14

R5 J1/46 PMC_AD15

T1 J2/48 PMC_AD10

T2 J2/47 PMC_M66E

T3 J1/48 PMC_AD11

T4 J1/47 PMC_AD12

T5 J2/49 PMC_AD8

U1 J1/49 PMC_AD9

U2 J2/51 PMC_AD7

U3 J1/52 PMC_CBE0_N

U4 J1/54 PMC_AD5

U5 J1/53 PMC_AD6

V1 J1/55 PMC_AD4

V2 J1/58 PMC_AD3

V3 J1/60 PMC_AD1

V4 J1/59 PMC_AD2

V5 J2/61 PMC_ACK64_N

W1 J1/61 PMC_AD0

W2 J1/64 PMC_REQ64_N

6.6.3. PMC J3 & J4

PROASICPLUS

PIN

PMC

PINSignal name

W3 J4/1 PMC_UIO1

W4 J3/1 PMC_J3_1

Y1 J4/4 PMC_UIO2

Y2 J3/4 PMC_CBE7_N

Y3 J4/6 PMC_UIO3

Y4 J4/5 PMC_UIO4

AA1 J3/6 PMC_CBE5_N

AA2 J3/5 PMC_CBE6_N

AA3 J4/7 PMC_UIO5

AA4 J3/7 PMC_CBE4_N

AB1 J4/10 PMC_UIO6

AB2 J4/9 PMC_UIO7

AB3 J3/10 PMC_PAR64



PROASICPLUS

PIN

PMC

PINSignal name

AB4 J3/9 PMC_VIO1

AC1 J4/12 PMC_UIO8

AC2 J4/11 PMC_UIO9

AC3 J3/12 PMC_AD62

AD1 J3/11 PMC_AD63

AD2 J4/13 PMC_UIO10

AD4 J3/13 PMC_AD61

AE3 J4/16 PMC_UIO11

AE4 J3/16 PMC_AD60

AF3 J4/18 PMC_UIO12

AF4 J4/17 PMC_UIO13

AC5 J3/18 PMC_AD58

AD5 J3/17 PMC_AD59

AE5 J4/19 PMC_UIO14

AF5 J3/19 PMC_AD57

AC6 J4/22 PMC_UIO15

AD6 J4/21 PMC_UIO16

AE6 J3/22 PMC_AD56

AF6 J3/21 PMC_VIO2

AC7 J4/24 PMC_UIO17

AD7 J4/23 PMC_UIO18

AE7 J3/24 PMC_AD54

AF7 J3/23 PMC_AD55

AB8 J4/25 PMC_UIO19

AC8 J3/25 PMC_AD53

AD8 J4/28 PMC_UIO20

AE8 J3/28 PMC_AD52

AF8 J4/30 PMC_UIO21

AB9 J4/29 PMC_UIO22

AC9 J3/30 PMC_AD50

AD9 J3/29 PMC_AD51

AE9 J4/31 PMC_UIO23

AF9 J3/31 PMC_AD49

AB10 J4/34 PMC_UIO24

AC10 J3/34 PMC_AD48

AD10 J4/36 PMC_UIO25

AE10 J4/35 PMC_UIO26

AF10 J3/36 PMC_AD46

PROASICPLUS

PIN

PMC

PINSignal name

AB11 J3/35 PMC_AD47

AC11 J4/37 PMC_UIO27

AD11 J3/37 PMC_AD45


AF11 J4/39 PMC_UIO29

AB12 J3/40 PMC_AD44

AC12 J3/39 PMC_VIO3



AF12 J3/42 PMC_AD42

AB13 J3/41 PMC_AD43


AD13 J3/43 PMC_AD41


AF13 J3/46 PMC_AD40



AD14 J3/48 PMC_AD38

AE14 J3/47 PMC_AD39


AB15 J3/49 PMC_AD37


AD15 J3/52 PMC_AD36



AB16 J3/54 PMC_AD34

AC16 J3/53 PMC_AD35


AE16 J3/55 PMC_AD33



AC17 J3/58 PMC_AD32

AD17 J3/57 PMC_VIO4



AB18 J3/60 PMC_J3_3

AC18 J3/59 PMC_J3_2




PROASICPLUS

PIN

PMC

PINSignal name

AE18 J3/61 PMC_J3_4


AB19 J3/64 PMC_J3_5

6.6.4. SDRAM

PROASICPLUS

PIN

SDRAMPIN

Signal name

E4 2 SD_DQ0

E3 3 SD_DQ1

D3 86 SD_DQ32

D2 4 SD_DQ2

D1 87 SD_DQ33

C4 88 SD_DQ34

C2 5 SD_DQ3

B4 89 SD_DQ35

B3 8 SD_DQ5

A4 7 SD_DQ4

A3 91 SD_DQ36

D5 92 SD_DQ37

C5 9 SD_DQ6

B5 93 SD_DQ38

A5 10 SD_DQ7

D6 94 SD_DQ39

C6 11 SD_DQ8

B6 95 SD_DQ40

A6 13 SD_DQ9

D7 97 SD_DQ41

C7 14 SD_DQ10

B7 98 SD_DQ42

A7 15 SD_DQ11

D8 99 SD_DQ43

C8 16 SD_DQ12

B8 100 SD_DQ44

A8 17 SD_DQ13

E9 101 SD_DQ45

D9 19 SD_DQ14

C9 103 SD_DQ46

B9 20 SD_DQ15

A9 104 SD_DQ47

E10 27 SD_WEO_N

D10 111 SD_CAS_N

C10 28 SD_DQMB0

B10 112 SD_DQMB4

PROASICPLUS

PIN

SDRAMPIN

Signal name

A10 29 SD_DQMB1

E11 113 SD_DQMB5

D11 30 SD_S0_N

C11 114 SD_S1_N

B11 115 SD_RAS_N

A11 33 SD_A0

E12 117 SD_A1

D12 34 SD_A2

C12 118 SD_A3

B12 35 SD_A4

A12 119 SD_A5

E13 36 SD_A6

D13 120 SD_A7

C13 37 SD_A8

B13 121 SD_A9

A13 38 SD_A10

E14 122 SD_BA0

D14 39 SD_BA1

C14 123 SD_A11

B14 126 SD_A12

A14 45 SD_S2_N

E15 129 SD_S3_N

D15 46 SD_DQMB2

C15 130 SD_DQMB6

B15 47 SD_DQMB3

A15 131 SD_DQMB7

E16 132 SD_A13

D16 55 SD_DQ16

C16 139 SD_DQ48

B16 56 SD_DQ17

A16 140 SD_DQ49

E17 57 SD_DQ18

D17 141 SD_DQ50

C17 58 SD_DQ19

B17 142 SD_DQ51

A17 60 SD_DQ20

E18 144 SD_DQ52

D18 65 SD_DQ21

C18 149 SD_DQ53

B18 66 SD_DQ22

A18 150 SD_DQ54

E19 67 SD_DQ23

D19 151 SD_DQ55

C19 69 SD_DQ24

B19 153 SD_DQ56

A19 70 SD_DQ25



PROASICPLUS

PIN

SDRAMPIN

Signal name

D20 154 SD_DQ57

C20 71 SD_DQ26

B20 155 SD_DQ58

A20 72 SD_DQ27

D21 156 SD_DQ59

C21 74 SD_DQ28

B21 158 SD_DQ60

A21 75 SD_DQ29

D22 159 SD_DQ61

C22 76 SD_DQ30

B22 160 SD_DQ62

A22 77 SD_DQ31

C23 161 SD_DQ63

H25 63, 128 SD_CKE

6.6.5. Prototype Area

PROASICPLUS

PIN

PROTOPIN

Signal name

K24 0 PA_GPIO1_0

K23 1 PA_GPIO1_1

K22 2 PA_GPIO1_2

L25 3 PA_GPIO1_3

L24 4 PA_GPIO1_4

L23 5 PA_GPIO1_5

L22 6 PA_GPIO1_6

M24 7 PA_GPIO1_7

M23 8 PA_GPIO1_8

P24 9 PA_GPIO1_9

M22 11 PA_GPIO1_10(GL)

L26 13 PA_GPIO1_11

M26 15 PA_GPIO1_12

M25 17 PA_GPIO1_13

P25 19 PA_GPIO1_14

R26 21 PA_GPIO1_15

R25 23 PA_GPIO1_16

T26 25 PA_GPIO1_17

T25 27 PA_GPIO1_18

6.6.6. Keyboard

PROASICPLUS

PINSignal name

E23 cpu_gpio_key0

E24 cpu_gpio_key1

E25 cpu_gpio_key2

E26 cpu_gpio_key3

6.6.7. PA_GPIO's

PROASICPLUS

PIN

UIO4PIN

Signal name

K25 2 PA_GPIO2_0

K26 3 PA_GPIO2_1

J22 4 PA_GPIO2_2

J23 5 PA_GPIO2_3

J24 6 PA_GPIO2_4

J25 7 PA_GPIO2_5

J26 8 PA_GPIO2_6

H23 9 PA_GPIO2_7

H24 10 PA_GPIO2_8

6.6.8. UART 1/2 (Transceiver)

PROASICPLUS

PIN

UART1 /UART2

PINSignal name

C25 UART1 /TX

PA_TX1

B24 UART2 /TX

PA_TX2

A23 UART1 /RX

PA_RX1

A24 UART2 /RX

PA_RX2



6.6.9. CANbus 1/2

PROASICPLUS

PIN

CAN1 /CAN2PIN

Signal name

D24 CAN1 / TX PA_TX1

D25 CAN2 / TX PA_TX2

D26 CAN1 / RX PA_RX1

C26 CAN2 / RX PA_RX2

6.6.10. Clocks and Reset

PROASICPLUS

PINSignal name

N23 OSC1

F23 CLK1_FROM_PA

F24 CLK1_TO_PA

F25 OSC2

F26 CLK2_FROM_PA

M2 CLK2_TO_PA

G26 CLK_TO_CPU_FROM_PA

G25 CLK32K

N25 RESET_N

6.6.11. PECL

PROASICPLUS

PINSignal name

N4 WPECLIN

P5 WPECLREF

N5 AVDDW

N3 AGNW

P26 EPECLIN

N22 EPECLREF

PROASICPLUS

PINSignal name

N24 AVDDE

N26 AGNE

6.6.12. JTAG

PROASICPLUS

PINSignal name

AF23 TDI

AC22 PA_TDO

AD21 TCK

AE24 TRST

AC21 TMS

6.6.13. Programming

PROASICPLUS

PINSignal name

AE23 VPN

AD22 VNN

AC24 RCK

6.6.14. Miscellaneous

PROASICPLUS

PINSignal name

B23 FLASH-STATUS

H26 LED1

G23 LED2

G24 LED3



7 . S C H E M A TI C

The schematic of the board is shown on the following few pages.

© 2003, INICORE INC. Schematic - Page 84

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CH

_01_

0010

1.06

PA

D-M

ain

: C

PU

& C

PU

Ext

enti

on a

nd J

TA

G-I

CE

(c)

INIC

OR

E I

nc.

56

00 M

owry

Sch

ool R

d. S

uite

180

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

B

110

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

P24

/BM

S

CP

U_G

PIO

_TX

2

VDD33

VDD33

CP

U_G

PIO

_TD

I

CP

U_D

11C

PU

_D9

CP

U_G

PIO

_TC

K

VD

D33

CP

U_A

1

CP

U_G

PIO

_KE

Y1

CP

U_G

PIO

_TR

ST

CP

U_C

S2_

N

GN

D

CP

U_A

7

CP

U_C

S1_

N

CP

U_A

15

CP

U_C

S3_

N

CP

U_D

15

CP

U_A

17

GN

D

VD

D33

CP

U_D

6

CP

U_C

S0_

NC

LK_F

RO

M_C

PU

CP

U_O

E_N

CP

U_D

7

VD

D33

CP

U_W

AIT

_NC

PU

_UB

_N

CP

U_A

20

CP

U_A

10

GN

D

CP

U_L

B_N

GN

D

CP

U_G

PIO

_FLA

SH

_BU

SY

CP

U_A

19

CP

U_A

6

CP

U_G

PIO

_SC

L

CP

U_A

21

CP

U_A

5

CP

U_D

14C

PU

_D12

GN

D

VD

D33

GN

D

VD

D33

CP

U_A

14

CP

U_G

PIO

_KE

Y2

CP

U_G

PIO

_KE

Y0

CP

U_G

PIO

_TD

O

CP

U_D

3

CLK

_TO

_EX

T2

CP

U_G

PIO

_SD

A

CP

U_D

2

CP

U_A

16

CP

U_A

11

CP

U_I

RQ

2C

PU

_IR

Q0

CP

U_D

10

CP

U_A

2

GN

D

CP

U_A

9

RE

SE

T_N

CP

U_G

PIO

_KE

Y3

CP

U_G

PIO

_TM

S

CP

U_D

8

CP

U_D

0

CP

U_A

12

CP

U_F

IRQ

CP

U_I

RQ

1

CP

U_D

13

CP

U_A

3

CP

U_A

22

CP

U_A

18

CP

U_A

8

CP

U_A

4

CP

U_A

23

CP

U_A

13

GN

D

CP

U_D

5

CP

U_D

1

CP

U_D

4

CP

U_

WR

_N

RE

SE

T_N

CP

U_A

7

VD

D33

CP

U_A

15

CP

U_

WR

_N

GN

D

CP

U_G

PIO

_TC

K

CP

U_D

14

CP

U_G

PIO

_KE

Y3

CP

U_D

3C

PU

_D2

CP

U_D

0

GN

D

CP

U_D

12

CP

U_A

9

CP

U_I

RQ

0

CP

U_L

B_N

CP

U_C

S0_

N

CP

U_G

PIO

_KE

Y2

VD

D33

CP

U_C

S3_

N

CP

U_D

11

CP

U_O

E_N

CP

U_A

17

GN

D

CP

U_A

5

CP

U_D

4

VD

D33

CP

U_A

21

CP

U_G

PIO

_FLA

SH

_BU

SY

CP

U_A

10

CP

U_G

PIO

_KE

Y0

GN

D

CLK

_TO

_EX

T1

CP

U_G

PIO

_TR

ST

GN

D

CP

U_I

RQ

1

CP

U_A

12

CLK

_FR

OM

_CP

U

CP

U_F

IRQ

CP

U_A

20

CP

U_A

4

CP

U_C

S2_

N

CP

U_A

3

CP

U_A

16

GN

D

CP

U_A

18

CP

U_G

PIO

_TM

S

CP

U_A

2

CP

U_A

11

VD

D33

CP

U_U

B_N

GN

D

CP

U_A

14

CP

U_D

15

CP

U_D

6

GN

D

CP

U_D

13

CP

U_G

PIO

_TD

IC

PU

_GP

IO_T

DO

CP

U_A

6

CP

U_A

8

CP

U_A

19

CP

U_I

RQ

2

CP

U_A

1

CP

U_D

9

CP

U_G

PIO

_KE

Y1

CP

U_A

13

CP

U_D

5

CP

U_W

AIT

_N

CP

U_D

8

CP

U_D

1

CP

U_G

PIO

_SD

A

CP

U_D

10

VD

D33

CP

U_A

22

CP

U_C

S1_

N

CP

U_D

7

CP

U_G

PIO

_SC

L

CP

U_A

23

CP

U_I

RQ

0

CP

U_I

RQ

1

CP

U_I

RQ

2

CP

U_G

PIO

_SD

A

CP

U_G

PIO

_SC

L

CP

U_F

IRQ

JI_T

MS

JI_T

RS

TJI

_TD

O

JI_T

CK

VDD33

GND

CP

U_G

PIO

_TD

O

CP

U_G

PIO

_TX

1

GN

D

CP

U_A

9

CP

U_A

7

CP

U_A

3

CP

U_A

1JI_TMS

RESET_N

CP

U_G

PIO

_TX

2

CP

U_G

PIO

_TD

I

GN

D

CPU_D9

CPU_D5

CP

U_A

13

CLK_FROM_CPU

CP

U_F

IRQ

CP

U_G

PIO

_TC

KC

PU

_A20

CP

U_A

12

LED

4

CPU_CS3_N

CP

U_G

PIO

_RX

1

CPU_D15

CPU_D0

CP

U_A

19

GN

D

JI_T

DI

JI_TCKJI_TDO

GND

CP

U_G

PIO

_TR

ST

CPU_D2

CP

U_A

5

CPU_WR_N

CPU_GPIO_RX2

CP

U_G

PIO

_TM

S

CPU_D12VDD33

GN

D

CP

U_A

10

CPU_OE_N

GND

CP

U_A

17

CP

U_A

4

JI_TDI

CP

U_G

PIO

_JT

AG

_SE

L

CPU_D8

CPU_D1

P24/BMS

CPU_UB_N

CPU_A22

CP

U_A

8V

DD

33

CP

U_A

6

LED

5

CPU_CS2_N

VDD33

CP

U_G

PIO

_FLA

SH

_BU

SY

CPU_D13

CPU_D10

CPU_D4

CPU_A23

CP

U_A

15

VDD33

VDD33

VD

D33

CPU_GPIO_SDA

CP

U_A

16

CP

U_A

2

CP

U_L

B_N

CLK_TO_CPU

LED

4

CPU_D7

GN

D

GND

CP

U_A

11

CPU_A21

CPU_CS0_NCPU_WAIT_N

GND

CP

U_I

RQ

0

CPU_D3

GN

D

CPU_CS1_N

CP

U_A

14

CPU_D11

LED

5

VD

D33

CP

U_G

PIO

_SC

L

CPU_D14

CPU_D6

VDD33VDD33

CP

U_A

18

CP

U_I

RQ

1C

PU

_IR

Q2

CP

U_G

PIO

_KE

Y1

CP

U_G

PIO

_KE

Y2

CP

U_G

PIO

_KE

Y3

CPU_GPIO_KEY0

CPU_GPIO_KEY1

CP

U_W

AIT

_N

LED

6

LED

6

CP

U_G

PIO

_KE

Y[3

:0]

CP

U_D

[15:

0]

CP

U_I

RQ

[2:0

]

CP

U_A

[23:

1]

CP

U_F

IRQ

RE

SE

T_N

CLK

_TO

_EX

T1

CLK

_TO

_EX

T2

CP

U_

WR

_N

CP

U_U

B_N

CP

U_L

B_N

CP

U_O

E_N

CP

U_C

S2_

NC

PU_C

S1_N

CPU

_CS3

_N

CPU

_CS0

_N

CLK

_TO

_CP

U

CP

U_W

AIT

_N

CP

U_G

PIO

_RX

1C

PU

_GP

IO_T

X1

CP

U_G

PIO

_RX

2C

PU

_GP

IO_T

X2

CP

U_G

PIO

_SC

LC

PU

_GP

IO_S

DA

CP

U_G

PIO

_JT

AG

_SE

LC

PU

_GP

IO_T

RS

TC

PU

_GP

IO_T

DO

CP

U_G

PIO

_TM

SC

PU

_GP

IO_T

CK

CP

U_G

PIO

_TD

I

CP

U_G

PIO

_FLA

SH

_BU

SY

VD

D33

VDD

33

VDD

33

VDD

33

VDD

33

VDD

33

100n

F

C92

10pF

C86

R15

94K

7

100n

F

C94

J7 JUM

PE

R1

12

10pF

C89

U32

AT9

1X40

/TQ

FP10

0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

51525354555657585960616263646566676869707172737475

76

7877

798081828384858687888990919293949596979899100

A0/

NLB

GN

D_2

A1

A2

A3

A4

A5

A6

A7

VD

D_1

0A

8A

9A

10A

11A

12A

13A

14G

ND

_18

GN

D_1

9A

15A

16A

17A

18A

19P

28/A

20/C

S7

P29/A21/CS6VDD_27VDD_28P30/A22/CS5P31/A23/CS4D0D1D2D3D4GND_36D5D6D7D8D9D10D11VDD_44D12D13D14D15P0/TCLK0P1/TIOA0

P2/

TIO

B0

GN

D_5

2G

ND

_53

P3/

TC

LK1

P4/

TIO

A1

P5/

TIO

B1

P6/

TC

LK2

P7/

TIO

A2

P8/

TIO

B2

P9/

IRQ

0V

DD

_61

VD

D_6

2P

10/I

RQ

1P

11/I

RQ

2G

ND

_65

P12

/FIQ

P13

/SC

K0

P14

/TX

D0

P15

/RX

D0

P16

P17

P18

P19

P20

/SC

K1

P21

/TX

D1/

NT

RI

P22/RXD1

GND_78NWR1/NUB

NRSTNWDOVF

VDD_81MCKI

P23P24/BMS

P25/MCKOGND_86GND_87

TMSTDI

TDOTCK

NRD/NOENWR0/NWE

VDD_94VDD_95

NWAITNCS0NCS1

P26/NCS2P27/NCS3

R16

24K

7

D9

LED

6

2 1

100n

F

C97

R16

340

0K

R15

310

K

22pF

C90

R15

74K

7

100n

F

C95

LK11

SM

LIN

K(4

K7)

a b c

100n

F

C82

R15

21K

2R

101K

2

R16

14K

7

10nF

C76

J20

CP

U E

XT

1

21 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

100n

F

C96

J21

CP

U E

XT

2

21 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79

4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80

100n

F

C83

R5

4K7

D8 LE

D5

2 1

R15

84K

7

R15

11K

2

10nF

C77

R15

510

K

100n

F

C84

J18

JTA

G_I

CE

12

34

56

78

910

1112

1314

1516

1718

1920

10pF

C85

100n

F

C93R

160

4K7

10pF

C87

R15

410

K

D7 LE

D4

2 1

R15

610

K

10pF

C88

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

The

pow

erpl

ane

for

the

cloc

k ge

nera

tors

is is

olat

edfr

om th

e bo

ard

pow

erpl

ane

by a

ferr

ite b

ead

PA

_WP

EC

LRE

F a

nd P

A_W

PE

CLI

N a

re 5

0 O

hm tr

ansm

issi

on li

nes.

N

ote

the

follo

win

g ru

les

for t

hese

sig

nal t

race

s:a)

The

y sh

ould

hav

e eq

ual d

elay

leng

th a

nd ru

n ad

just

to e

ach

othe

r. b)

Avo

id s

har

p an

gles

on

thes

e tra

ces.

c) N

o vi

as o

n th

ese

trace

s.d)

To

prev

ent c

ross

talk

, avo

id r

outin

g o

ther

sig

nal t

race

s in

par

alle

l.e)

Loc

ate

the

130

Ohm

and

82

Ohm

term

inat

ion

resi

stor

s as

clo

sed

toth

e P

roA

SIC

pin

s as

pos

sibl

e.

One

cap

acito

r fo

r ea

ch O

SC

and

one

for e

ach

clk

Buf

fer

(PI

6CV

304)

.See

clk

_lay

out.p

df.

Con

nect

or fo

r h

ighs

peed

dat

a. P

rint o

n P

CB

ne

ar J

24 P

EC

LRE

F,

near

J23

PE

CLI

N.

EP

EC

LRE

F a

nd E

PE

CLI

N a

re

50 O

hm tr

ansm

issi

on li

nes.

N

ote

the

follo

win

g r

ules

for t

hese

sig

nal t

race

s:a)

The

y sh

ould

hav

e eq

ual d

elay

leng

th

and

run

adju

st to

eac

h ot

her.

b) A

void

sh

arp

angl

es o

n th

ese

trace

s.c

) No

vias

on

thes

e tra

ces.

d) T

o pr

even

t cro

ssta

lk, a

void

rou

ting

othe

r sig

nal t

race

s in

par

alle

l.e)

Loc

ate

the

130

Ohm

and

82

Ohm

ter

min

atio

n re

sist

ors

as c

lose

d to

the

Pro

AS

IC's

pin

s as

pos

sibl

e.

4-P

in O

scila

tor S

ocke

t

4-P

in O

scila

tor S

ocke

t

NO VIAS ON CLOCK TRACES AND MAKE THEM AS SHORT AS POSSIBLE

a-b

: Clk

buf

fer 1

is d

riven

by

clk1

_fro

m_p

ab-

c : C

lk

buffe

r 1 is

driv

en b

y os

c1(d

efau

lt)

a-b

: Clk

buf

fer 2

is d

riven

by

clk2

_fro

m_p

ab-

c : C

lk

buffe

r 2 is

driv

en b

y os

c2(d

efau

lt)

a-b

: Clk

buf

fer

3 is

driv

en b

y cl

k_to

_cpu

_fro

m_p

ab-

c : C

lk b

uffe

r 3

is d

riven

by

osc2

(def

ault)

R16

8 is

not

fact

ory

fitte

d.

R16

9 is

not

fact

ory

fitte

d.

PA

DM

A_S

CH

_01_

0010

1.06

PA

D-M

ain

: C

lock

cir

cuit,

LV

PE

CL,

50

Ohm

Tra

nsm

issi

on li

ne a

nd I

sola

ted

pow

erpl

ane

(c)

INIC

OR

E I

nc.

56

00 M

owry

Sch

ool R

d. S

uite

180

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

B

210

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

VD

DO

SC

GN

D

GN

D

GN

D

VD

D33

GN

DV

DD

OS

C

GND

VDD33

VD

DO

SC

VD

DO

SC

VD

D33

VD

D33

VD

D33

VD

D33

VD

D33

VD

D33

CLK

1_T

O_P

A

CLK

1_F

RO

M_P

A

OS

C1

OSC

2

CLK

2_T

O_P

A

CLK

2_F

RO

M_P

A

CLK

_TO

_PM

C

CLK

_SD

1

CLK

_SD

2

CLK

_TO

_EX

T2

CLK

_TO

_CP

U

CLK

_TO

_EX

T1

EP

EC

LIN

EP

EC

LRE

F

PA

_WP

EC

LIN

PA

_WP

EC

LRE

F

CLK

_TO

_CP

U_F

RO

M_P

A

CLK

A_T

O_G

C

CLK

_TO

_GC

VD

D33

VD

DO

SC

VD

D33

VDD

33

VDD

33

J24

PE

4117

1

2

JUM

PE

R2-

1J8_1

12

3

a b c

100n

F

C74

TP

5O

SC

2

1

100n

F

C69

U26

PI6

CV

2304

L

1 2 3 45678

CLK

_IN

OE

Y0

GN

DY

1V

DD

33Y2

Y3

R15

082

R16

910

0

R13

933

U23 P

I6C

V23

04L

1 2 3 45678

CLK

_IN

OE

Y0

GN

DY

1V

DD

33Y2

Y3

R14

633

R13

833

R14

713

0U

27

SE

L343

1C-1

52.5

2

14 871

VC

CP

EC

LG

ND

PE

CL

R14

013

0

100n

F

C75

Y3

OS

C14

DIP

14 871

VC

CO

UT

GN

DN

C

TP

3O

SC

1

1

R14

533

TP

4C

LK1

1JU

MP

ER

2-1

J8_3

12

3

a b cR14

433

R14

213

0

R16

810

0

100n

F

C71

U25

PI6

CV

2304

L

1 2 3 45678

CLK

_IN

OE

Y0

GN

DY

1V

DD

33Y2

Y3

R14

882

Y2

OS

C14

DIP

14 871

VC

CO

UT

GN

DN

C

J23

PE

4117

1

2

L4

FE

RR

ITE

BE

AD 2

1

R14

182

JUM

PE

R2-

1

J8_2

12

3

a b c

+C

72 10uF

100n

F

C73

100n

F

C70

TP

6C

LK2

1

R14

913

0

R14

382

TP

7C

PU

_CLK

1

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

TQ

FP

144

Soc

ket f

or P

roto

type

Prin

t on

PC

B

UP

, DO

WN

, CA

NC

EL

and

SE

LEC

T,

and

plac

e th

e ke

ys a

s sh

own

here

.

SM

LIN

K fo

r I2C

Inte

rface

.a-

b : S

X-F

PG

A p

ins

64, 6

5 ar

e co

nnec

ted

to I2

C b

us. (

Def

ault)

b-c

: SX

-FP

GA

pin

s 64

, 65

are

conn

ect

ed to

CF

_IO

RD

_N a

nd C

F_I

OW

R_N

.

LK6,

BV

D2

Ena

ble

:op

en

: BV

D2

from

CF

not

con

nect

ed t

o G

C. (

Def

ault)

clos

ed :

BV

D2

from

CF

con

nect

ed to

GC

pin

131

(PR

A/IO

).

LK6

Prin

t on

PC

B th

e po

sitio

n of

a,b

and

c

R71

is n

otfa

ctor

yfit

ted.

PA

DM

A_S

CH

_01_

0010

1.06

PA

D-M

ain

: S

X-F

PG

A,

Com

pact

Fla

sh c

onne

ctor

and

I/O

But

tons

(c)

INIC

OR

E I

nc.

56

00 M

owry

Sch

ool R

d. S

uite

180

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

B

310

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

RESET_N

CPU_A20

CPU_A8

CPU_A5

CPU_A7

CPU_IRQ2

CPU_A6

CPU_A9

CPU_A11

CPU_A19

CPU_WR_N

CPU_A18

CPU_CS1_N

CPU_A3

CPU_OE_N

CPU_A10

CPU_CS2_N

CPU_A4

CPU_LB_NCPU_UB_N

CPU_WAIT_N

CF_CD1_N

CPU_A12

CPU_A2CPU_A1

CLKA_TO_GC

CPU_A23

GND

GND

GN

D

GN

D

GN

D

GN

D

GN

D

CP

U_D

8C

PU

_D9

CP

U_D

14

CP

U_D

5

CP

U_D

13

CP

U_D

7

CP

U_D

0

CP

U_D

3

CP

U_D

11C

PU

_D12

CP

U_D

1C

PU

_D2

CP

U_D

10

CP

U_D

4

CP

U_D

6

CP

U_D

15

CLK_TO_GC

CF

_A10

CF_A9

CF_A8

CF_A7

CF_A6

CF_A5

CF_A4

CF_A3

CF_A2

CF_A1

CF_A0

GND

CF_OE_N

CF

_EB

L33_

NC

F_E

BL5

0_N

CF

_EB

LDC

DC

_N

CF

_D13

CF

_D12

CF

_D10

CF

_D15

CF_D9

CF

_D14

DIS

P_D

0D

ISP

_CS

DIS

P_R

WN

DIS

P_A

0

GN

D

DIS

P_D

1

GND

BA

NK

_SE

L1B

AN

K_S

EL0

PRA

PRB

VDD25

VD

D25

VD

D25

VD

D25

VD

D25

VDD25

VDD33

VDD33

VD

D33

VDD33

VDD33

VD

D33

VD

D33

VD

D25

VD

D33

VDD33

VDD50

GC

_TM

S

TR

ST

TCK

GC_TDO

DIS

P_D

7

VDDCF

GN

D

VD

DC

F

CF

_W

P

CF

_CS

EL_

N

CF

_WE

_N

CF

_VS

1_N

CF

_RD

YB

SY

_N

CF

_IN

PA

CK

_N

CF

_D10

CF

_BV

D2

CF

_D11

CF

_CD

2_N

CF

_D12

CF

_D13

CF

_IN

PA

CK

_N

CF

_RD

YB

SY

_N

CF

_IO

RD

_N

CF

_RE

SE

TC

F_V

S2_

N

CF

_WA

IT_N

CF

_WA

IT_N

CF

_D9

CF

_IO

WR

_N

CF

_BV

D1

CF

_D8

CF

_D15

CF

_CE

2_N

CF

_CD

1_N

CF

_CD

1_N

CF

_RE

G_N

CF

_D14

SR

AM

_CO

NF

IG1

CF_RESET

CF_BVD1

GN

D

CF_WAIT_N

PRB

DIS

P_D

2

CF_REG_N

CF

_W

P

SR

AM

_CO

NF

IG0

CF_VS2_N

CF_VS1_N

GC

_RC

K

GN

D

CF

_VS

1_N

CF

_VS

2_N

CP

U_G

PIO

_SC

L

CF

_IO

WR

_N

CP

U_G

PIO

_SD

A

CF

_IO

RD

_N

SC

L_IO

WR

N

SD

A_I

OR

DN

CF

_CD

2_N

VDD25

CP

U_G

PIO

_KE

Y0

CP

U_G

PIO

_KE

Y1

CP

U_G

PIO

_KE

Y2

CP

U_G

PIO

_KE

Y3

CF

_A4

CF

_A0

CF

_A6

CF

_A7

CF

_D3

CF

_A5

CF

_CD

2_N

CF

_OE

_N

CF

_A2

CF

_D5

CF

_D1

CF

_A10

CF

_D6

CF

_CE

1_N

CF

_D2

CF

_W

P

GN

D

CF

_D7

CF

_D4

CF

_A1

CF

_A3

VD

DC

F

CF

_A9

CF

_D0

CF

_A8

CF_RDYBSY_N

CF

_D3

CF

_D5

CF_D0

CF

_D7

CF_D1

CF_D2CF_D8

CF

_D6

CF

_D4

CF

_D11

CF_CSEL_N

CF_INPACK_N

SCL_IOWRN

CF

_CE

2_N

CF

_CE

1_N

SDA_IORDN

CF_WE_N

DIS

P_D

4

DIS

P_D

6

DIS

P_D

3

DIS

P_D

5

CF

_BV

D2

PR

A

GN

DP

A_T

DO

CP

U_G

PIO

_KE

Y[3

:0]

CP

U_I

RQ

[2:0

]

CP

U_A

[23:

1]

CP

U_D

[15:

0]

TR

ST

TC

K

PA

_TD

OG

C_T

MS

GC

_TD

OG

C_R

CK

CP

U_C

S2_

NC

PU_C

S1_N

CP

U_F

IRQ

CP

U_W

AIT

_N

CP

U_

WR

_N

CP

U_U

B_N

CP

U_L

B_N

CP

U_O

E_N

CLK

_TO

_GC

CLK

A_T

O_G

CR

ES

ET

_N

BA

NK

_SE

L0BA

NK_

SEL1

CF

_EB

L33_

NC

F_EB

L50_

NC

F_E

BLD

CD

C_N

CP

U_G

PIO

_SC

LC

PU

_GP

IO_S

DA

SR

AM

_CO

NF

IG1

SRAM

_CO

NFI

G0

VD

D33

VDD

50V

DD

CF

VD

D33

VD

DC

F

VD

D33

VDD

25

VDD

33

VDD

33VD

D33

VDD

33

VDD

50

VDD

25VD

D33

VDD

50

100n

F

C10

2

R13

6 4K7

R70

0R

R16

74K

7

R12

947

k

100n

F

C11

0

R16

5

0R

SW

2 UP

100n

F

C10

7

R12

847

k

100n

F

C98

TP

1P

RA 1

100n

F

C10

3

R71

100K

R13

547

k

100n

F

C11

1J25

CONN25x2/CF

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100n

F

C10

8

100n

F

C99

TP

2P

RB 1

SW

5

SE

LEC

T

100n

F

C10

4

R16

6 4K7

U21

SX

-A F

PG

A

1 2 3 4 5 6 9 10 117 8 12 13 14 15 2216 17 18 20

37

21 23 24 25 26 27 3531 32 33 34

54

302819

38

60

39404142

4443

454647

71

48

36

4950515253

56

29

55

59

616263646566

80

57

81

72

7475767778

67

706968

82838485

58

79 73929394959697 91 88 87 8689909899101

100

103

104

105

106

107

108

110111112113114

116117118119120121122123124

130

102

109

115

128129

140

125126127

131

144

132133134135136137138139

141142143

GN

D_1

TD

I,I/

OI/

O3

I/O

4I/

O5

I/O

6

TM

SV

DD

33_1

0G

ND

_11

I/O

7I/

O8

I/O

12I/

O13

I/O

14I/

O15

TR

ST

,I/O

I/O

16I/

O17

I/O

18

VD

D25

_20 I/O37

I/O

21

I/O

23I/

O24

I/O

25I/

O26

I/O

27

I/O

35

I/O

31I/

O32

I/O

33I/

O34

PRB,I/O

VD

D25

_30

GN

D_2

8

NC

19

I/O38

HCLK

I/O39I/O40I/O41I/O42

VDD33_44I/O43

I/O45I/O46I/O47

TDO,I/O

I/O48

GN

D_3

6

I/O49I/O50I/O51I/O52I/O53

VDD25_56

VD

D33

_29

I/O55

I/O59

I/O61I/O62I/O63I/O64I/O65I/O66

VD

D33

_80

GND_57

GN

D_8

1

I/O72

I/O

74I/

O75

I/O

76I/

O77

I/O

78

I/O67

I/O70I/O69VDD33_68

I/O

82I/

O83

I/O

84I/

O85

NC58

VD

D25

_79

GN

D_7

3

I/O

92I/

O93

I/O

94I/

O95

I/O

96I/

O97

I/O

91

I/O

88I/

O87

I/O

86

VD

D25

_89

NC

90

VD

D25

_98

GN

D_9

9

GN

D_1

01I/

O10

0

I/O

103

I/O

104

I/O

105

I/O

106

I/O

107

I/O

108

I/O110I/O111I/O112I/O113I/O114

I/O116I/O117I/O118I/O119I/O120I/O121I/O122I/O123I/O124

I/O130

VD

D33

_102

GND_109

VDD33_115

GND_128VDD25_129

VDD33_140

CLKACLKB

NC127

PRA,I/O

TCK,I/O

I/O132I/O133I/O134I/O135I/O136I/O137I/O138I/O139

I/O141I/O142I/O143

R13

74K

7

LK10

_1

SM

LIN

K(0

R)

a b c

R13

447

k

100n

F

C11

2

100n

F

C10

0

R13

147

k

100n

F

C10

5

SW

3

CA

NC

EL

LK10

_2S

MLI

NK

(0R

)

a b c

SW

4

DO

WN

J22 LCD DISP

1 2 3 4 5 6 7 8 9 10 11 12 13 14

100n

F

C10

1

R13

047

k

100n

F

C10

9

R13

247

k

100n

F

C10

6

100n

F

C15

3

R12

74K

7

R13

347

k

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

JTA

G P

A

JTA

G P

A+

Jum

per o

pen

:

E

xter

nal J

TA

G-H

eade

r

is J

TA

G s

ourc

e (D

efau

lt).

Jum

per c

lose

d :

C

PU

is J

TA

G s

ourc

e.

SM

LIN

K fo

r SX

-FP

GA

JT

AG

A-B

: JT

AG

sig

nal

s ar

e sh

ort c

uted

. SX

-FP

GA

is n

ot in

JT

AG

cha

in.(D

efau

lt)B

-C :

SX

-FP

GA

is in

JT

AG

cha

in .

SM

LIN

K b

lock

for P

MC

JT

AG

Sig

nals

P

MC

_TM

S, P

MC

_TC

K a

nd P

MC

_TR

ST

:A

-B :

JTA

G s

igna

ls a

re b

y-pa

ssed

. PM

C is

not

c

onne

cted

to J

TA

G c

hain

.B

-C :

PM

C is

con

nec

ted

to J

TA

G c

hain

. (D

efau

lt)

Pul

lups

for T

MS

, TR

ST

, TC

K a

nd T

DI

for C

PU

and

JT

AG

con

nect

ors.

Res

isto

r not

fact

ory

fitte

d

Act

el J

tag

Hea

der

See

jtag

_hea

der.p

dffo

r foo

tprin

t

Act

el J

tag

Hea

der

See

jtag

_hea

der.p

df fo

r foo

tprin

tN

ot fa

ctor

y fit

ted

Jum

per f

or J

TA

G S

igna

l TD

O:

A-B

: P

MC

is

not i

n JT

AG

cha

in. (

Def

ault)

B-C

: P

MC

is in

JT

AG

cha

in.

LK13

Prin

t on

PC

B th

e po

sitio

n of

a,b

and

c

Prin

t on

PC

B th

e po

sitio

n of

a,b

and

c

Prin

t on

PC

B th

e po

sitio

n of

a,b

and

c

PA

DM

A_S

CH

_01_

0010

1.06

PA

D-M

ain

: JT

AG

-Cha

in

(c)

INIC

OR

E I

nc.

56

00 M

owry

Sch

ool R

d. S

uite

180

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

B

410

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

GN

D

VD

D25

VD

DP

P

VD

D33

VD

DP

GN

D

TR

ST

_A

VD

DL

GN

D

TD

O

GN

D

VD

DL

GN

D

TD

O

VD

DP

VD

DL

RC

K_A

VD

D25

VD

D33

GN

D

VD

D25

VD

DN

P

VD

D33 C

PU

_GP

IO_J

TA

G_S

EL

RC

K_A

TD

IG

ND

GN

D

CP

U_G

PIO

_TD

I

TM

S_A

VD

D33

TD

I_A

TD

I_A

TM

S_A

TM

S

TR

ST

_A

VD

D33

GN

D

GN

D

TM

S_A

TC

K_A

CP

U_G

PIO

_TC

KT

CK

_A

PM

C_T

DI

VD

D33

GC

_TM

ST

MS

TD

OP

MC

_TD

O

PA

_TD

OP

MC

_TD

IG

C_T

DO

VD

D33

PM

C_T

MS

TM

S

TC

KP

MC

_TC

KV

DD

33

PM

C_T

RS

T

GND

VDD33

GC

_RC

K

VDD25

PM

C_I

NT

D_N

TR

ST

VD

D33

TR

ST

_AT

CK

_A

TM

S_A

TD

I_A

CP

U_G

PIO

_TM

S

CP

U_G

PIO

_TC

KC

PU

_GP

IO_T

DI

RC

K_A

RC

K

RX

D2

RX

D1

PA

_RX

D2

PA

_RX

D1

CP

U_G

PIO

_TR

ST

CP

U_G

PIO

_TM

S

RC

K

VDDL

VDDP

VDDPP

VDDNP

CP

U_G

PIO

_TR

ST

TR

ST

TD

I_A

TC

K_A

TC

K

TD

O

TR

ST

TC

K

TM

S

TD

I

RC

KG

C_R

CK

GC

_TM

SG

C_T

DO

PA

_RX

D1

PA_R

XD2

RX

D1

RXD

2P

A_T

DO

PM

C_T

DI

PM

C_T

MS

PM

C_T

DO

PM

C_T

RS

T

PM

C_T

CK

CP

U_C

S0_

N

CP

U_

WR

_N

CP

U_L

B_N

CP

U_O

E_N

PM

C_I

NT

D_N

CP

U_G

PIO

_TM

S

CP

U_G

PIO

_JT

AG

_SE

LC

PU

_GP

IO_T

RS

TC

PU

_GP

IO_T

DI

CP

U_G

PIO

_TC

K

CP

U_G

PIO

_TD

O

VD

D33

VDD

25

VDD

33

VDD

33

VD

DL

VD

DP

VD

DP

PV

DD

NP

VD

D33

R11

510

K

JUM

PE

R2-

1

J21

23

a b c

R12

60R

R11

410

KR

121

10K

R11

610

KR

123

10K

LK1_

2

SM

LIN

K(0

R)

a b c

R11

310

K

100n

F

C81

R12

010

K

LK2_

1 SM

LIN

K(0

R)

a b c

R12

547

0

R12

210

K

100n

F

C80

U20

MM

74H

C15

7/T

SS

OP

16

1 2 3 4 5 6 7 8

16 9101112131415S

elec

t1A 1B 1Y 2A 2B 2Y G

ND

VD

D33 3Y3B3A4Y4B4AS

T

J17

JTAG_PA2 4 6 8 10 12 14 16 18 20 22 24 26

1 3 5 7 9 11 13 15 17 19 21 23 25

LK1_

1

SM

LIN

K(0

R)

a b c

U19

MM

74H

C15

7/T

SS

OP

161 2 3 4 5 6 7 8

16 9101112131415S

elec

t1A 1B 1Y 2A 2B 2Y G

ND

VD

D33 3Y3B3A4Y4B4AS

T

R12

4

10K

J16

JTAG_PA+

2 4 6 8 10 12 14 16 18 20 22 24 26

1 3 5 7 9 11 13 15 17 19 21 23 25

LK1_

3

SM

LIN

K(0

R)

a b c

J1JU

MP

ER

112

LK2_

2SM

LIN

K(0

R)

a b c

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Pro

AS

IC P

lus h

as tw

o is

ola

ted p

ow

er is

lands.

One 2

.5 V

olt

and

one 3

.3 V

olt.

Each o

f th

ese p

ow

er is

lands

is c

onnect

ed w

ithfo

ur

0R

resis

tors

and four

100nF

ca

ps

on e

ach

sid

e o

f Pro

AS

ICP

lus to the m

ain

pow

er su

pply

.

These F

ilters

should

be p

lace

d c

lose

toth

e p

ackage p

ins a

nd m

inim

ize in

duct

ance

on c

apacito

rs, re

sis

tors

and tr

ace

s as

much a

s p

oss

ible

.

BG

A456 S

ocket fo

r P

roto

types.

Pla

ce P

roA

SIC

clo

se t

o P

MC

-Connect

ors

.N

o V

ias o

n P

MC

_clo

ck,

PM

C_IR

DY

_N

and

PM

C_T

RDY

_N

.

LK

8L

K9

PA

DM

A_S

CH

_01_

0010

1.06

PA

D-M

ain

: P

roA

SIC

Plu

s

(c)

INIC

OR

E I

nc.

5

600

Mow

ry S

choo

l Rd.

Sui

te 1

80

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

D

510

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent N

umbe

rR

ev

Dat

e:S

heet

of

VDD33

GND

VDDPP

VDDNP

VDD25

PA

_LE

D2

PA

_LE

D1

AG

ND

W

AV

DD

E

VDDL

VDDP

GND

VDDL

VDDP

VD

DP

VD

DP

VD

DP

PM

C_A

D23

PM

C_R

EQ

_N

PMC_UIO22

PMC_UIO30

PMC_J3_4

PMC_AD33

PMC_UIO33

PMC_AD60

PMC_UIO46

PMC_UIO44

PMC_UIO29

PMC_UIO13

CP

U_A

19

CP

U_A

10

CP

U_D

2

PA

_GP

IO1_

8

PA_GPIO1_10

CP

U_G

PIO

_KE

Y2

SD_DQ10

SD_DQ44

PA_RX1

GNDGND

VDDL

PM

C_U

IO6

AGNDW

PM

C_P

ER

R_N

PMC_IRDY_N

PM

C_I

NTD

_N

PMC_AD39

PMC_AD46

RCK

PA_TDO

CP

U_A

18

CP

U_A

4

PA

_GP

IO1_

9

PA

_LE

D2

SD_WEO_N

SD_DQ55

SD_DQ28

SD_A11

SD_A8

SD_DQ8

GND

GND

VD

DP

VD

DP

VD

DP

VDDLVDDL

VD

DP

AVDDE

PM

C_A

D13

PM

C_A

D19

PM

C_C

BE

2_N

PM

C_G

NT_

N

PM

C_I

NTC

_N

PMC_AD34

PMC_AD47

PMC_AD48

PMC_AD58

PMC_AD57

CP

U_A

21

CP

U_A

6

CP

U_D

10

PA

_GP

IO1_

2

CLK

_TO

_CP

U_F

RO

M_P

AC

LK32

K

CP

U_G

PIO

_KE

Y3

SD_S0_N

SD_DQ46

SD_DQMB4

SD_DQ35

GND

GND

VD

DP

PM

C_A

D15

PM

C_C

BE

3_N

PM

C_P

ME

_N

CPU_IRQ1

PMC_J3_2

PMC_AD45

PMC_AD51

PMC_UIO31

TRST

TDI

PA

_GP

IO1_

14

OS

C2

SD_CAS_NSD_DQMB0

SD_DQ12

SD_DQ5

SD_DQMB7

SD_DQ11

GND

GND

GND

GND

GNDGND

GND

VDDL

VDDL

VDDL

PM

C_A

D63

PM

C_U

IO3

PM

C_A

D9

PM

C_A

D11

PM

C_A

D21

PMC_UIO27

PMC_VIO4

PMC_AD36

PMC_UIO14

CPU_WR_N

PMC_UIO36

PMC_AD49

CP

U_D

8

SD_DQMB2

CPU_GPIO_FLASH_BUSY

SD_DQ62

SD_DQ29

SD_DQMB1

GND

GND

VDDL

VDDL

EPECLREF

PM

C_A

D2

PM

C_C

BE

0_N

PM

C_C

BE

1_N

PM

C_A

D16

PM

C_A

D30

CPU_CS3_N

PMC_UIO21

CP

U_D

6

OSC1

PA

_GP

IO1_

3

PA

_GP

IO2_

0P

A_G

PIO

1_0

PA

_GP

IO1_

1

PA

_GP

IO2_

4

PA

_GP

IO2_

2

CLK

2_F

RO

M_P

A

CLK

1_F

RO

M_P

A

PA

_TX

D2

SD_DQMB5

SD_DQ45

SD_DQ25

AV

DD

W

VDDL

GND

VDDL

VDDL

VD

DP

VD

DP

VD

DP

PM

C_U

IO10

PM

C_C

BE

7_N

PM

C_A

D7

PM

C_A

D12

PM

C_A

D20

PM

C_A

D29

PMC_J3_5

PMC_UIO34

PMC_AD44

PMC_UIO32

PMC_AD52

PMC_AD40

CP

U_A

5

CP

U_D

1

PA

_GP

IO1_

12

PA

_GP

IO2_

8

SD_BA0

SD_A4

SD_DQ42

PA_RX2

SD_A0

SD_DQ36

PA

_LE

D3

GND

PM

C_A

D62

PA_WPECLREF

PM

C_A

D6

PMC_UIO42

PMC_AD43

PMC_AD50

CPU_UB_N

PMC_AD41

PMC_VIO2

CP

U_D

9

PA

_GP

IO1_

4

PA

_LE

D1

PA

_TX

1

SD_DQ23

SD_S3_N

SD_A2

SD_DQ63

SD_DQ24

SD_DQ38

SD_DQ31

SD_DQ47

SD_DQ4

GND

GND

GND

VD

DP

VD

DP

PA_WPECLIN

PM

C_A

D8

PM

C_P

AR

PM

C_D

EV

SE

L_N

PM

C_B

M1_

N

PMC_UIO24

PMC_UIO38

PMC_UIO28

CPU_A23

CPU_WAIT_N

PMC_UIO39

CP

U_A

22

CP

U_A

12

CP

U_D

3

CP

U_G

PIO

_KE

Y0

SD_DQ21

SD_DQ26

SD_S1_N

SD_DQ56

SD_DQ15

CLK2_TO_PA

GND

GND

GND

VDDNP

PM

C_P

AR

64

PM

C_U

IO4

PM

C_U

IO1

PM

C_A

D5

PM

C_L

OC

K_N

PM

C_S

TOP

_N

PM

C_A

D27

SD

_DQ

3

PMC_UIO17

PMC_AD54

PMC_AD42

TMS

CP

U_D

14

CP

U_D

12P

A_G

PIO

1_17

EPECLIN

PA

_GP

IO2_

5

SD

_CK

E

SD_DQ18

SD_A6

SD_DQ14

SD_DQ43

SD_A12

PM

C_T

RD

Y_N

GND

VDDL

VD

DP

VDDL

VDDL

PM

C_U

IO8

AGNDE

PM

C_R

EQ

64_N

PM

C_A

D25

PM

C_I

DS

EL

PM

C_A

D26

PM

C_A

D28

SD

_DQ

1P

MC

_IN

TA_N

PMC_UIO23

CPU_IRQ0

CP

U_A

17

CP

U_D

5

PA_TX2

SD_A5

SD_DQ7

VDDL

GND

GND

VD

DP

VD

DP

VDDPP

PM

C_C

BE

6_N

PM

C_A

D1

PM

C_R

ST_

N

SD

_DQ

2

PMC_J3_3

PMC_AD37

PMC_AD53

PMC_UIO45

CPU_CS2_N

TCK

CP

U_A

9

PA

_GP

IO1_

5

PA

_GP

IO2_

1

PA

_TX

D1

SD_DQ61

SD_A7

SD_DQ30

SD_DQ34

SD_DQ51

SD_DQMB3

SD_A9

SD_RAS_N

SD_S2_N

VDDL

VDDL

VDDL

VDDL

VD

DP

VD

DP

PM

C_U

IO9

PM

C_A

D3

PM

C_A

D4

PM

C_M

66E

PM

C_S

ER

R_N

SD

_DQ

33

PMC_AD32

CPU_CS0_N

PMC_AD59

PMC_AD61

CPU_FIRQ

CPU_LB_N

PMC_UIO43

PMC_UIO26

PMC_AD56

CP

U_A

1

PA

_GP

IO1_

16

PA

_GP

IO2_

3

PA

_RX

D2

SD_BA1

SD_DQ39

SD_DQ19

SD_DQMB6

SD_DQ13

VD

DP

VD

DP

VD

DP

PM

C_C

BE

4_N

PM

C_C

BE

5_N

AVDDW

PM

C_U

IO2

PM

C_A

D0

PM

C_A

D31

PM

C_A

D24

PM

C_B

M3_

N

SD

_DQ

0

PMC_UIO35

PMC_UIO15PMC_UIO16

PMC_UIO11

PMC_UIO41

PMC_AD55

CP

U_A

20

CP

U_A

11

CP

U_A

14C

PU

_A7

CP

U_D

13

CP

U_D

4

CP

U_D

0

PA

_GP

IO2_

6

PA

_RX

D1

SD_A13

SD_DQ60

SD_DQ58

SD_DQ49

SD_A10

SD_DQ9

AG

ND

E

VDDL

GNDGND

GND

PM

C_J

3_1

PM

C_A

CK

64_N

PM

C_A

D17

PM

C_A

D18

PMC_VIO3

PMC_AD38

CP

U_A

15

CP

U_A

8

CP

U_D

15

PA

_GP

IO1_

18

PA

_GP

IO1_

7

PA

_GP

IO1_

11

SD_DQ16

SD_A3

SD_DQ40

VDDL

GND

VDDL

VD

DP

VD

DP

VD

DP

VDDL

PM

C_U

IO5

PM

C_U

IO7

PM

C_A

D10

PM

C_F

RA

ME

_N

PM

C_A

D22

PM

C_I

NTB

_N

PM

C_B

M2_

N

PMC_UIO19

CPU_OE_N

PMC_UIO25

PMC_UIO12

CP

U_A

3

CP

U_A

2

CP

U_D

7P

A_G

PIO

1_15

RE

SE

T_N

PA

_LE

D3

CLK

1_T

O_P

A

CP

U_G

PIO

_KE

Y1

SD_DQ52

SD_DQ59

SD_DQ57

SD_DQ41

SD_DQ37

SD_DQ48

SD_DQ22

SD_DQ17

SD_DQ27

GND

GND

GND

GND

GND

VDDL

PM

C_V

IO1

PM

C_A

D14

PM

C_B

M4_

N

SD

_DQ

32

PMC_AD35

PMC_UIO37

CPU_IRQ2

PMC_UIO40

PMC_UIO20

PMC_UIO18

CPU_CS1_N

CP

U_A

16

CP

U_A

13

CP

U_D

11

PA

_GP

IO1_

13

PA

_GP

IO1_

6

PA

_GP

IO2_

7

SD_A1

SD_DQ50

SD_DQ53

SD_DQ6

SD_DQ54

SD_DQ20

PM

C_A

D[3

1:0]

PM

C_A

D[6

3:32

]

SD

_DQ

[63:

0]

SD

_A[1

3:0]

CP

U_A

[23:

1]

CP

U_D

[15:

0]

CP

U_G

PIO

_KE

Y[3

:0]

CP

U_I

RQ

[2:0

]

PA

_GP

IO2_

[8:0

]

PA

_GP

IO1_

[18:

0]

PM

C_U

IO[4

6:1]

PM

C_I

NTB

_NP

MC

_IN

TC_N

PM

C_I

NTD

_N

PM

C_I

NTA

_NR

ES

ET_

N

CLK

_TO

_PM

CP

MC

_RS

T_N

PM

C_P

AR

64P

MC

_FR

AM

E_N

PM

C_T

RD

Y_N

PM

C_I

RD

Y_N

PM

C_L

OC

K_N

PM

C_S

TOP

_NP

MC

_SE

RR

_NP

MC

_PE

RR

_NP

MC

_RE

Q64

_NP

MC

_AC

K64

_NP

MC

_PM

E_N

PM

C_M

66E

PM

C_D

EV

SE

L_N

PM

C_J

3_1

PM

C_J

3_2

PM

C_J

3_3

PM

C_J

3_4

PM

C_J

3_5

PM

C_P

AR

SD

_CA

S_N

SD

_RA

S_N

SD

_S0_

NS

D_S

1_N

SD

_S2_

NS

D_S

3_N

SD

_DQ

MB

0S

D_D

QM

B1

SD

_DQ

MB

2S

D_D

QM

B3

SD

_DQ

MB

4S

D_D

QM

B5

SD

_DQ

MB

6S

D_D

QM

B7

PM

C_V

IO1

PM

C_V

IO2

PM

C_V

IO3

PM

C_V

IO4

PM

C_G

NT_

NP

MC

_RE

Q_N

PM

C_I

DS

EL

PM

C_B

M1_

NP

MC

_BM

2_N

PM

C_B

M3_

NP

MC

_BM

4_N

PM

C_C

BE

0_N

PM

C_C

BE

1_N

PM

C_C

BE

2_N

PM

C_C

BE

3_N

PM

C_C

BE

4_N

PM

C_C

BE

5_N

PM

C_C

BE

6_N

PM

C_C

BE

7_N

EP

EC

LIN

EP

EC

LRE

F

PA

_WP

EC

LRE

FP

A_W

PE

CLI

N

CP

U_G

PIO

_FLA

SH

_BU

SY

CLK

32K

CLK

1_T

O_P

AC

LK2_

TO_P

AO

SC

1O

SC

2C

LK1_

FR

OM

_PA

CLK

2_FR

OM

_PA

CLK

_TO

_CP

U_F

RO

M_P

A

CP

U_W

AIT

_NC

PU

_FIR

Q

CP

U_C

S0_

NC

PU

_CS

1_N

CP

U_C

S3_

NC

PU

_CS

2_N

CP

U_W

R_N

CP

U_O

E_N

CP

U_L

B_N

CP

U_U

B_N

TMS

PA

_TD

O

TRS

TTD

I

RC

K

TC

K

PA

_TX

2P

A_T

X1

PA

_RX

2P

A_R

X1

PA

_TX

D2

PA

_TX

D1

PA

_RX

D2

PA

_RX

D1

SD

_BA

1S

D_B

A0

SD

_WE

O_N

SD

_CK

E

VD

DP

PV

DD

25V

DD

33V

DD

NP

VD

D33

VD

DP

VD

DP

VD

D33

VD

D33

VD

DP

VD

D33

VD

DP

VD

D25

VD

D25

VD

D25

VD

DL

VD

DL

VD

D25

VD

DL

VD

DL

VD

DL

VD

DL

VD

DL

VD

DP

R89

0R

R10

00R

R78

0R

R77

0R

R11

25.

1

100n

F C47

R82

0R

R81

0R

D4

LED12 1

R11

11K

2

R95

0R

R10

20R

100n

F C35

R97

0R

100n

F C37

100n

F C51

100n

F C46

R90

0R

R79

0R

100n

F C41

R84

0R

R10

60R

100n

F C53

100n

F C59

100n

F C66

R94

0R

0.22

uF

C67

R11

01K

2100n

F C56

R10

40R

100n

F C62

100n

F C49

R87

0R

100n

F C36

100n

F C60

R80

0R

R96

0R

0.22

uF

C68

R10

10R

R10

91K

2

100n

F C44

100n

F C58

R86

0R

100n

F C63

100n

F C48

100n

F C54

U18

Pro

Asi

c P

lus

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

C25

C26

D24

D25

D26

E23

E24

E25

E26 F23

F24

F25

F26

G23

G24

G25

G26

H23

H24

H25

H26 J2

2J2

3J2

4J2

5J2

6K

22K

23K

24K

25K

26 L22

L23

L24

L25

L26

M22

M23

M24

M25

M26

P26

N23

N25

P22

P23

P24

P25

R22

R23

R24

R25

R26 T2

2T2

3T2

4T2

5T2

6U

22U

23U

24U

25U

26V

22V

23V

24V

25V

26W

23W

24W

25W

26 Y23

Y24

Y25

Y26

AA

23A

A24

AA

25A

A26

AB

23A

B24

AB

25A

B26

AC

25A

C26

AC21AC22

AC24

AD21

AF23

AE24

AD

25A

D26

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF24

AE3

AE4

AE5

AE6

AE7

AE8

AE9

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD23

AC5

AC6

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AB8

AB9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

C2

D1

D2

D3

E1

E2

E3

E4

F1

F2 F3 F4 G1

G2

G3

G4

H1

H2

H3

H4

J1 J2 J3 J4 J5 K1

K2

K3

K4

K5

L1 L2 L3 L4 L5

M1

M3

M4

M5

N1

P1

P2

P3

P4

R1

R2

R3

R4

R5

T1 T2 T3 T4 T5 U1

U2

U3

U4

U5

V1

V2

V3

V4

V5

W1

W2

W3

W4

Y1

Y2

Y3

Y4

N22

N24N26

N4P5

N3N5

AB

1A

B2

AB

3A

B4

AA

1A

A2

AA

3A

A4

AC

1A

C2

AC

3A

D1

AD

2

A1

A2

A25

A26

AA5

AA22

AB5AB6AB7

AB20AB21AB22

AC

4A

C23

AD

3

AD22

AD

24

AE

1A

E2

AE23

AE

25A

E26

AF

1A

F2A

F25

AF2

6

B1

B2

B25

B26

C1

C3

C24

D4

D23

E5E6E7E8

E20E21E22

F5

F22

G5

G22

H5

H22

L16L15L14

L13L12L11

M16M15M14

M13M12M11

N16N15N14

N13N12N11

P16P15P14

P13P12P11

R16R15R14

R13R12R11

T16T15T14

T13T12T11

W5

W22

Y5

Y22

M2

N2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

C25

C26

D24

D25

D26

E23

E24

E25

E26

F23

F24

F25

F26

G23

G24

G25

G26

H23

H24

H25

H26

J22

J23

J24

J25

J26

K22

K23

K24

K25

K26

L22

L23

L24

L25

L26

GL1

M23

M24

M25

M26

EPECLIN

GL2

N25

P22

P23

P24

P25

R22

R23

R24

R25

R26

T22

T23

T24

T25

T26

U22

U23

U24

U25

U26

V22

V23

V24

V25

V26

W23

W24

W25

W26

Y23

Y24

Y25

Y26

AA

23A

A24

AA

25A

A26

AB

23A

B24

AB

25A

B26

AC

25A

C26

TMSTDO

RCK,I/O

TCK

TDI

TRST

AD

25A

D26

AF3

AF4

AF5

AF6

AF7

AF8

AF9

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF24

AE3

AE4

AE5

AE6

AE7

AE8

AE9

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD23

AC5

AC6

AC7

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AB8

AB9

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

C2

D1

D2

D3

E1

E2

E3

E4

F1

F2

F3

F4

G1

G2

G3

G4

H1

H2

H3

H4 J1 J2 J3 J4 J5 K1

K2

K3

K4

K5 L1 L2 L3 L4 L5

GL3

M3

M4

M5

N1

P1

P2

P3

P4

R1

R2

R3

R4

R5 T1 T2 T3 T4 T5 U1

U2

U3

U4

U5

V1

V2

V3

V4

V5

W1

W2

W3

W4

Y1

Y2

Y3

Y4

EPECLREF

AVDDEAGNDE

WPECLINWPECLREF

AGNDWAVDDW

AB

1A

B2

AB

3A

B4

AA

1A

A2

AA

3A

A4

AC

1A

C2

AC

3A

D1

AD

2

VD

DP

_A1

VD

DP

_A2

VD

DP

_A25

VD

DP

_A26

VDDL_AA5

VDDL_AA22

VDDL_AB5VDDL_AB6VDDL_AB7

VDDL_AB20VDDL_AB21VDDL_AB22

VD

DP

_AC

4V

DD

P_A

C23

VD

DP

_AD

3

VPP

VD

DP

_AD

24

VD

DP

_AE

1V

DD

P_A

E2

VPN

VD

DP

_AE

25V

DD

P_A

E26

VD

DP

_AF

1V

DD

P_A

F2

VD

DP

_AF

25V

DD

P_A

F26

VD

DP

_B1

VD

DP

_B2

VD

DP

_B25

VD

DP

_B26

VD

DP

_C1

VD

DP

_C3

VD

DP

_C24

VDDP_D4

VD

DP

_D23

VDDL_E5VDDL_E6VDDL_E7VDDL_E8

VDDL_E20VDDL_E21VDDL_E22

VDDL_F5

VDDL_F22

VDDL_G5

VDDL_G22

VDDL_H5

VDDL_H22

GND_L16GND_L15GND_L14

GND_L13GND_L12GND_L11

GND_M16GND_M15GND_M14

GND_M13GND_M12GND_M11

GND_N16GND_N15GND_N14

GND_N13GND_N12GND_N11

GND_P16GND_P15GND_P14

GND_P13GND_P12GND_P11

GND_R16GND_R15GND_R14

GND_R13GND_R12GND_R11

GND_T16GND_T15GND_T14

GND_T13GND_T12GND_T11

VDDL_W5

VDDL_W22

VDDL_Y5

VDDL_Y22

GL4

N2

100n

F C55

100n

F C38

R91

0R

100n

F C57

100n

F C42

R10

30R

100n

F C40

R88

0R

100n

F C64

R10

85.

1

100n

F C39

R93

0R

R98

0R

R10

50R D

6

LED32 1

D5

LED22 1

R10

70R

100n

F C43

100n

F C65

100n

F C45

100n

F C50

R99

0R

R83

0R

R76

0R

R92

0R

R85

0R

100n

F C61

100n

F C52

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

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- TO

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|- - - - N O T F A C T O R Y F I T T E D - - - -|

No

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Def

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Inte

rrup

t C.

PA

DM

A_S

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_01_

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1.06

PA

D-M

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: P

MC

con

nect

ors

(c)

INIC

OR

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nc.

56

00 M

owry

Sch

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New

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945

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T:

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Thu

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20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

GN

D

PM

C_P

AR

64

PM

C_C

BE

5_N

GN

D

PM

C_C

BE

7_N

PM

C_A

D58

GN

DP

MC

_AD

62

GN

D

PM

C_A

D60

PM

C_A

D46

PM

C_A

D44

PM

C_A

D52

PM

C_A

D54

GN

D

PM

C_A

D48

GN

D

PM

C_A

D56

PM

C_A

D50

GN

D

GN

D

PM

C_A

D32

PM

C_A

D40

PM

C_A

D36

PM

C_A

D42

PM

C_A

D34

PM

C_A

D38

PM

C_J

3_3

GN

D

GN

D

GN

DP

MC

_J3_

5

GN

D

PM

C_M

66E

PM

C_A

D24

PM

C_A

D14

PM

C_A

D16

PM

C_T

RD

Y_N

PM

C_I

DS

EL

GN

D

GN

DP

MC

_AD

18

PM

C_T

DO

GN

D

GN

D

PM

C_B

M2_

N

GN

D

PM

C_S

TO

P_N

PM

C_B

M3_

N

PM

C_S

ER

R_N

PM

C_A

CK

64_N

PM

C_B

M4_

N

VD

D33

PM

C_A

D7

PM

C_A

D23

PM

C_C

BE

1_N

PM

C_P

ER

R_N

PM

C_C

BE

2_N

PM

C_R

ST

_N

PM

C_T

DI

PM

C_P

ME

_N

GN

D

PM

C_T

RS

T

PM

C_A

D13

PM

C_A

D8

GN

D

PM

C_A

D30

VD

DP

12

PM

C_A

D29

PM

C_A

D10

PM

C_T

MS

PM

C_A

D26

PM

C_A

D20

GN

D

GN

D

GN

D

GN

D

VD

D33

VD

D33

VD

D33

VD

D33

VD

D33

VD

D33

VD

D33

VD

D33

PM

C_C

BE

6_N

PM

C_A

D53

PM

C_A

D49

PM

C_A

D41

PM

C_V

IO1

PM

C_V

IO2

PM

C_A

D57

PM

C_V

IO4

GN

D

PM

C_A

D59

PM

C_A

D35

PM

C_A

D55

PM

C_A

D43

PM

C_V

IO3

PM

C_A

D63

PM

C_A

D33

PM

C_J

3_1

PM

C_A

D47

GN

D

PM

C_A

D39

GN

D

GN

D

PM

C_J

3_4

PM

C_A

D37

GN

D

GN

D

PM

C_J

3_2

PM

C_A

D61

PM

C_C

BE

4_N

PM

C_A

D51

GN

D

PM

C_A

D45

VDD50

VDDP12

VDDN12

GND

VDD33

PM

C_A

D55

PM

C_A

D38

PM

C_A

D51

PM

C_A

D35

PM

C_A

D54

PM

C_A

D48

PM

C_A

D41

PM

C_A

D50

PM

C_A

D34

PM

C_A

D63

PM

C_A

D59

PM

C_A

D47

PM

C_A

D58

PM

C_A

D37

PM

C_A

D62

PM

C_A

D33

PM

C_A

D46

PM

C_A

D61

PM

C_A

D40

PM

C_A

D57

PM

C_A

D32

PM

C_A

D45

PM

C_A

D49

PM

C_A

D53

PM

C_A

D43

PM

C_A

D56

PM

C_A

D39

PM

C_A

D60

PM

C_A

D52

PM

C_A

D44

PM

C_A

D42

PM

C_A

D36

VD

D50

VD

D33

PM

C_A

D21

PM

C_C

BE

3_N

VD

D33

GN

D

PM

C_A

D28

PM

C_P

AR

INT

CN

_SH

DN

VD

DN

12

VD

D33

PM

C_A

D2

PM

C_A

D31

GN

D

PM

C_A

D3

PM

C_I

NT

A_N

GN

D

PM

C_T

CK

PM

C_F

RA

ME

_N

PM

C_I

NT

D_N

PM

C_A

D0

GN

D

GN

D

PM

C_G

NT

_N

PM

C_L

OC

K_N

PM

C_I

RD

Y_N

GN

D

PM

C_A

D6

PM

C_A

D1

PM

C_A

D25

VD

D33

PM

C_A

D11

PM

C_A

D22

PM

C_A

D9

GN

D

PM

C_B

M1_

N

GN

D

PM

C_A

D17

GN

D

PM

C_D

EV

SE

L_N

GN

D

PM

C_A

D12

PM

C_A

D15

GN

D

GN

D

PM

C_A

D19

PM

C_C

BE

0_N

PM

C_A

D27

PM

C_A

D4

PM

C_A

D5

PM

C_R

EQ

64_N

GN

D

PM

C_R

EQ

_N

PM

C_I

NT

B_N

VD

D33

CLK

_TO

_PM

C

VD

D50

VD

D50

VD

D50

VD

D50

VD

D50

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

PM

C_U

IO1

PM

C_U

IO2

PM

C_U

IO3

PM

C_U

IO4

PM

C_U

IO6

PM

C_U

IO7

PM

C_U

IO10

PM

C_U

IO12

PM

C_U

IO14

PM

C_U

IO17

PM

C_U

IO20

PM

C_U

IO21

PM

C_U

IO24

PM

C_U

IO25

PM

C_U

IO28

PM

C_U

IO30

PM

C_U

IO33

PM

C_U

IO34

PM

C_U

IO37

PM

C_U

IO38

PM

C_U

IO41

PM

C_U

IO43

PM

C_U

IO5

PM

C_U

IO8

PM

C_U

IO9

PM

C_U

IO11

PM

C_U

IO13

PM

C_U

IO15

PM

C_U

IO18

PM

C_U

IO22

PM

C_U

IO23

PM

C_U

IO26

PM

C_U

IO27

PM

C_U

IO29

PM

C_U

IO31

PM

C_U

IO35

PM

C_U

IO36

PM

C_U

IO39

PM

C_U

IO40

PM

C_U

IO32

PM

C_U

IO19

PM

C_U

IO45

PM

C_U

IO46

PM

C_U

IO42

PM

C_U

IO44

PM

C_U

IO16

CP

U_G

PIO

_SD

AC

PU

_GP

IO_S

CL

INT

CN

_SH

DN

INT

CN

_SH

DN

PM

C_A

D[6

3:32

]

PM

C_A

D[3

1:0]

PM

C_A

D[6

3:32

]

PM

C_U

IO[4

6:1]

PM

C_L

OC

K_N

PM

C_P

ER

R_N

PM

C_J

3_3

PM

C_R

ST

_NP

MC

_J3_

1

PM

C_R

EQ

64_N

PM

C_M

66E

PM

C_J

3_4

PM

C_A

CK

64_N

PM

C_S

ER

R_N

PM

C_P

ME

_N

PM

C_J

3_5

PM

C_P

AR

PM

C_P

AR

64

PM

C_D

EV

SE

L_N

CLK

_TO

_PM

C

PM

C_I

RD

Y_N

PM

C_T

RD

Y_N

PM

C_S

TO

P_N

PM

C_J

3_2

PM

C_C

BE

5_N

PMC

_CBE

4_N

PMC

_CBE

7_N

PMC

_CBE

3_N

PMC

_CBE

0_N

PMC

_CBE

2_N

PMC

_CBE

6_N

PMC

_CBE

1_N

PM

C_F

RA

ME

_N

PM

C_V

IO2

PMC

_VIO

1

PMC

_VIO

3PM

C_V

IO4

PM

C_T

DO

PM

C_T

RS

TP

MC

_TM

SP

MC

_TD

IP

MC

_TC

K

PM

C_B

M2_

NPM

C_B

M3_

N

PM

C_I

DS

EL

PM

C_B

M1_

N

PMC

_BM

4_N

PM

C_R

EQ

_NP

MC

_GN

T_N

CP

U_G

PIO

_SC

LC

PU

_GP

IO_S

DA

PM

C_I

NT

A_N

PM

C_I

NT

D_N

PMC

_IN

TC_N

SH

DN P

MC

_IN

TB

_N

VD

D50

VD

DN

12V

DD

P12

VD

D33

VDD

33

VDD

33

VDD

33

VDD

50

VDD

33

100n

F

C12

7

R51

20K

R56

20K

R29

20K

R46

20K

LK12

SM

LIN

K(0

R)

a b c

R58

20K

R61

20K

R26

20K

J12

PMC-Jn2

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64

R23

20K

100n

F

C11

3

R73

4K7

R67

20K

100n

F

C11

8

R43

20K

J13

PMC-Jn3

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64

100n

F

C12

4

R38

20K

100n

F

C12

9

100n

F

C13

2

R35

20K

100n

F

C12

6

R55

20K

R21

20K

R49

20K

R30

20K

R60

20K

R48

20K

R25

20K

100n

F

C13

0

R22

20K

R62

20K

R65

20K

100n

F

C11

4

R41

20K

R74

4K7

R40

20K

100n

F

C12

5

100n

F

C11

7

100n

F

C11

9

100n

F

C12

1

R33

20K

R53

20K

R50

20K

R32

20K

R28

20K

R59

20K

R47

20K

J11

PMC-Jn1

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64

R64

20K

R42

20K

R72

4K7

100n

F

C12

8

R66

20K

J14

PMC-Jn4

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64

100n

F

C11

5

R39

20K

100n

F

C12

3

R34

20K

R52

20K

100n

F

C13

1

100n

F

C12

0

R54

20K

R57

20K

R31

20K

100n

F

C12

2

100n

F

C11

6

R27

20K

R24

20K

R45

20K

R63

20K

R75

4K7

R20

20K

R44

20K

R37

20K

R36

20K

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

Pla

ce th

e G

roun

d-P

ins

dist

ribut

ed o

n th

e bo

ard.

See

reco

mm

ende

d la

yout

.

Not

fact

ory

fitte

d !

-14.

5V

LK4_

2

LK4_

1

17V

For

DC

-DC

con

vert

er c

ircui

t use

the

sam

e la

yout

as

aps.

not

e D

C23

3F.p

df (r

ecom

men

ded

layo

ut).

C25

has

a lo

w E

SR

.

LK12

PA

DM

A_S

CH

_01_

0010

1.06

PA

D-M

ain

: P

ower

con

nect

or,

DC

DC

con

vert

ers

and

Pow

er s

witc

h

(c)

INIC

OR

E I

nc.

56

00 M

owry

Sch

ool R

d. S

uite

180

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

B

710

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

GN

D

GN

D

GN

D

VD

DP

12

CF

_EB

L33_

N

CF

_EB

L50_

N

CF

_EB

LDC

DC

_N

VD

D50

VD

DN

12

CF

_EB

L50_

NC

F_EB

L33_

N

CF

_EB

LDC

DC

_N

SH

DN

VD

D33

VD

DC

F

VD

D50

VDD

25

VDD

50V

DD

N12

VD

DP

12

VD

D33

VDD

33

VD

DD

CD

CV

DD

NP

VD

DD

CD

CV

DD

PP

VD

D25

VDD

33VD

D50

VD

DP

12V

DD

N12

VD

DD

CD

C

L310

uH

100n

F

C34

+C

21

100u

F

+C

3015

uF

+C

28

33uF

J10

PW

R

1234

+C

16

15uF

J39

CO

NN

PC

B 2

1 2

J37

CO

NN

PC

B 2

1 2

R11

91K

2

TP

9

GN

D

1

100n

F

C27

R19

0R

R17

033

K

100n

F

C14

9

+C

23

10uF

D11

LED

8

2 1

R8

0R

1uF C

25

+C

24

33uF

D2

DIO

DE

SC

HO

TT

KY

+

C31

15uF

D3

DIODE SCHOTTKY

J40

CO

NN

PC

B 2

1 2

TP

10

GN

D

1

J38

CO

NN

PC

B 2

1 2

L210

uH

R15

100K

100n

F

C19

U16

LT19

30E

S5

1 2 345

SW

GN

D

FB

SH

DN

VIN

R16 10

0K

L110

uH

R17

118

K

R9

100K

100n

F

C15

2

R11

71K

2

100n

F

C26

+

C20

100u

F+

C91

100u

F

TP

11

GN

D

1

J41

CO

NN

PC

B 2

1 2

R12

0R

1uF

C33

R68

110

1uF

C18

U17

LT19

31E

S5

1 2 345

SW

GN

D

FB

SH

DN

VIN

R11 8.

06k

R14

100K

+C

1515

uF

TP

12

GN

D

1

R13

10K

100n

F

C22

R11

81K

2

D12

LED

9

2 1

R17

9.53

K

U13LM

S15

85A

CT

-AD

J

32

1

4IN

OU

T

ADJTA

B

R69

180

TP

13

GN

D

1

100n

F

C29

100n

F

C17

R18

47K

TP

8

GN

D

1

U15

IRU

1010

-25C

Y

12

34

GNDOU

TIN

TA

B

+C

14

10uF

U14

TP

S20

43A

/SO

P16

1 2 3 4 5 6 7 891011121315 1416

GN

D_1

IN1

EN

1EN

2G

ND

_5IN

2E

N3

NC

_8N

C_9

NC

_10

OU

T3

OC

3O

C2

OU

T1

OU

T2

OC

1

D10

LED

7

2 1

100n

F

C32

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

BA

NK

0 ,

LOW

BY

TE

BA

NK

0 ,

HIG

H B

YT

EB

AN

K 1

, H

IGH

BY

TE

BA

NK

1 ,

LOW

BY

TE

SM

LIN

K fo

r Fla

sh-m

ode

sele

ctio

n fit

ted

with

400

K re

sist

or:

A-B

:

Fla

sh in

16-

bit m

ode

(Def

ault)

.B

-C

: F

lash

in 8

-bit

mod

e.

SM

LIN

K f

or S

DR

AM

mod

e se

lect

ion

:A

-B

: R

egis

tere

d D

IMM

mod

e.B

-C

: B

uffe

red

DIM

M m

ode.

Not

fact

ory

fitte

d

TS

OP

56 S

ocke

t

Whe

n fit

ting

128K

x8 S

RA

M p

arts

, al

ign

pin

1 of

the

SR

AM

to w

here

pin

2 w

ould

be

if a

512K

par

t wer

e fit

ted.

Def

ault

is 1

28K

x8 S

RA

M.

Prin

t on

PC

B th

e po

sitio

n of

a,b

and

c

Prin

t on

PC

B th

e po

sitio

n of

a,b

and

c

1 ca

paci

tor

for

each

pow

er p

in o

f F

lash

and

SR

AM

Prin

t on

PC

B th

e po

sitio

n of

a,b

and

c

SM

LIN

Ks

for S

RA

M c

onfig

urat

ion

:C

onfig

(0) /

Con

fig(1

)A

-B /

A-B

: 12

8Kx8

,(Def

ault)

A-B

/ B

-C :

256K

x8,

B-C

/ A

-B :

512x

8.

Pla

ce C

141

near

SR

AM

s

Pla

ce th

is C

aps

nea

r SD

RA

M C

onne

ctor

(J19

).

PA

DM

A_S

CH

_01_

0010

1.06

PA

D-M

ain

: S

RA

M,

SD

RA

M a

nd F

lash

-Mem

ory

(c)

INIC

OR

E I

nc.

56

00 M

owry

Sch

ool R

d. S

uite

180

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

B

810

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

GN

DG

ND

VD

D33

VD

D33

CP

U_A

19

CP

U_A

18C

PU

_A17

CP

U_A

16

CP

U_O

E_N

CP

U_D

7C

PU

_D6

CP

U_A

13

CP

U_A

11

CP

U_A

15

CP

U_D

5

CP

U_A

14

CP

U_A

12

CP

U_D

4

CP

U_D

0

CP

U_A

1C

PU

_A2

CP

U_A

3C

PU

_A4

CP

U_A

5

CP

U_D

2

CP

U_D

1

CP

U_U

B_N

CP

U_A

10C

PU

_A9

CP

U_A

7C

PU

_A8

CP

U_A

6

BA

NK

_SE

L0C

PU

_A21

CP

U_A

19C

PU

_A18

CP

U_A

20

CP

U_A

16C

PU

_A17

CP

U_A

12

CP

U_A

14

RE

SE

T_N

CP

U_A

13

CP

U_A

15

CP

U_C

S0_

N

CP

U_A

11C

PU

_A10

CP

U_A

7

CP

U_A

8

CP

U_A

4

GN

D

CP

U_A

9

CP

U_A

6C

PU

_A5

CP

U_A

3C

PU

_A2

CP

U_A

1

CP

U_D

3

CP

U_D

9

CP

U_D

11

CP

U_D

8C

PU

_D1

CP

U_D

10

CP

U_D

5

CP

U_

WR

_N

CP

U_D

14

CP

U_D

13

FLA

SH

_BM

_N

CP

U_O

E_N

VD

D33

GN

D

CP

U_L

B_N

CP

U_D

2

CP

U_D

0

CP

U_D

4

CP

U_D

15C

PU

_D7

CP

U_A

23

CP

U_D

12

CP

U_D

6G

ND

VD

D33

FLA

SH

_BM

_N

BA

NK

_SE

L1

CP

U_G

PIO

_FLA

SH

_BU

SY

VD

D33

VD

D33

CP

U_A

22

GND

VDD33

J_R

EG

E

SD

_A4

SD

_DQ

25

SD

_DQ

7

SD

_DQ

55

SD

_DQ

41

SD

_DQ

27

SD

_DQ

9

SD

_BA

0

SD

_DQ

39

VD

D33

VD

D33

SD

_DQ

23

SD

_DQ

62

VD

D33

SD

_A2

SD

_A12

SD

_CK

E

SD

_DQ

MB

6

SD

_A10

SD

_SC

L

SD

_DQ

19

SD

_S1_

N

SD

_DQ

61

SD

_A1

SD

_DQ

43

SD

_S3_

N

GN

D

SD

_DQ

28

SD

_DQ

4

SD

_A11

SD

_DQ

53

SD

_DQ

12

VD

D33

GN

D

SD

_DQ

8

SD

_DQ

49

GN

D

SD

_DQ

11

SD

_DQ

29

VD

D33

VD

D33

SD

_DQ

17

SD

_W

EO

_N

SD

_RA

S_N

SD

_DQ

1

SD

_DQ

MB

7

SD

_A6

GN

D

SD

_BA

1

GN

D

SD

_DQ

38

SD

_DQ

48

SD

_DQ

MB

3

CLK

_SD

2

VD

D33

GN

D

SD

_CA

S_N

VD

D33

VD

D33

SD

_DQ

63

SD

_A3

SD

_DQ

59

GN

D

SD

_DQ

21

SD

_DQ

0

GN

D

VD

D33

SD

_DQ

42

SD

_DQ

18

SD

_DQ

26

SD

_DQ

MB

2

SD

_DQ

58

SD

_DQ

15

SD

_DQ

54

GN

D

VD

D33

SD

_DQ

36

GN

D

SD

_DQ

6

VD

D33

SD

_DQ

13

GN

D

GN

D

SD

_S2_

N

SD

_DQ

14S

D_D

Q47

SD

_DQ

MB

4

SD

_DQ

22

SD

_CK

E

GN

D

VD

D33

SD

_DQ

34

GN

D

SD

_DQ

50

SD

_DQ

5

SD

_DQ

57

SD

_DQ

51

VD

D33

GN

D

SD

_DQ

16

GN

D

SD

_DQ

45

SD

_DQ

33

SD

_A9

SD

_DQ

10

GN

D

SD

_DQ

40

GN

D

SD

_DQ

56

SD

_A5

SD

_A13

SD

_DQ

24

VD

D33

SD

_DQ

60

SD

_DQ

31

SD

_DQ

20

SD

_DQ

3

SD

_DQ

MB

1

SD

_A0

SD

_A8

CLK

_SD

2

SD

_DQ

37

SD

_DQ

46

SD

_DQ

30

SD

_A7

GN

D

SD

_DQ

52

VD

D33

SD

_DQ

2

SD

_DQ

44

VD

D33

GN

D

SD

_DQ

MB

0

CLK

_SD

1

GN

D

SD

_DQ

35

CLK

_SD

1

SD

_S0_

NS

D_D

QM

B5

SD

_DQ

32

J_R

EG

E

SD

_SD

A

SD

_SC

LS

D_S

DA

CP

U_A

12

CP

U_A

17

CP

U_A

10

CP

U_D

15C

PU

_D14

CP

U_O

E_N

GN

D

CP

U_A

11

CP

U_A

14

CP

U_A

13

VD

D33

CP

U_D

13C

PU

_D12

CP

U_A

16

CP

U_A

9

CP

U_A

15

CP

U_A

18

CP

U_A

19

CP

U_D

10

CP

U_A

6

VD

D33

CP

U_A

5

CP

U_A

8

BA

NK

_SE

L0C

PU

_A4

CP

U_D

8

CP

U_A

7

CP

U_A

2C

PU

_A3

GN

D

CP

U_D

9

CP

U_A

1

CP

U_D

11

CP

U_A

1

CP

U_D

8

CP

U_A

18

CP

U_D

11

CP

U_A

6

CP

U_D

9

CP

U_A

19

VD

D33

CP

U_A

2

CP

U_A

5

CP

U_A

8

CP

U_A

3

GN

D

CP

U_A

4

CP

U_D

10

CP

U_A

7C

PU

_A9

CP

U_A

15

CP

U_D

14

CP

U_O

E_N

CP

U_A

10

GN

D

CP

U_D

15

CP

U_A

14

CP

U_A

17

CP

U_D

13V

DD

33

CP

U_A

13C

PU

_A12

CP

U_A

11

CP

U_D

12

CP

U_A

16

CP

U_A

9

CP

U_A

15

CP

U_D

6

CP

U_O

E_N

CP

U_A

10

GN

D

CP

U_D

7

CP

U_A

14

CP

U_A

17

CP

U_D

5V

DD

33

CP

U_A

13C

PU

_A12

CP

U_A

11

CP

U_D

4

CP

U_A

16

CP

U_A

18

CP

U_A

4

CP

U_A

2

GN

DC

PU

_D2

CP

U_A

5

CP

U_D

1

BA

NK

_SE

L1

CP

U_A

19

CP

U_A

3

CP

U_A

8C

PU

_A7

CP

U_A

1

VD

D33

CP

U_D

0

CP

U_A

6

CP

U_U

B_N

CP

U_

WR

_N

CP

U_D

3C

PU

_W

R_

NC

PU

_D3

CP

U_D

[15:

0]

CP

U_A

[23:

1]

SD

_A[1

3:0]

SD

_DQ

[63:

0]

SD

_DQ

MB

2

SD

_BA

1SD

_BA0

SD

_DQ

MB

4

SD

_CA

S_N

SD

_S0_

NSD

_S1_

N

SD

_W

EO

_N

SD

_DQ

MB

1

SD_D

QM

B7

SD_D

QM

B5

SD

_RA

S_N

SD

_S3_

N

SD

_DQ

MB

3

SD_D

QM

B0

SD_D

QM

B6

SD

_S2_

N

CP

U_G

PIO

_FLA

SH

_BU

SY

CP

U_C

S0_

N

CP

U_

WR

_N

CP

U_O

E_N

CP

U_U

B_N

CLK

_SD

2C

LK_S

D1

BA

NK

_SE

L1BA

NK_

SEL0

CP

U_G

PIO

_SD

AC

PU

_GP

IO_S

CL

CP

U_l

B_N

SR

AM

_CO

NF

IG1

SRAM

_CO

NFI

G0

SD

_CK

ER

ES

ET

_N

VD

D33

VDD

33

VDD

33

VDD

33

VDD

33

VDD

33

VDD

33VD

D33

100n

F

C12

100n

F

C14

8

100n

F

C14

0

100n

F

C13

7

LK3

SM

LIN

K(0

R)

a b c

100n

F

C14

5

100n

F

C13

100n

F

C13

8

U11

512K

x8_S

RA

M/S

OJ3

6

107 8 11 12

33 32 2117

23 22 20

1 2 3 4 5 14 15 16 18

2428 2526293031

136

3435

927 1936

GN

D_1

0

D0

D1

D2

D3

A14

A13 A

9A

7

A11

A10 A

8

A17

A0

A1

A2

A3

A4

A5

A6

A18

A12

GN

D_2

8

D4

D5

D6

D7

OE

WE

CE

A15

A16

VC

CV

CC

_27

NC

_19

NC

_36

100n

F

C13

5

+C

141

10uF

LK7_

1

SM

LIN

K(0

R)

a b c

U10

FLA

SH

/TS

OP

_I_5

6

1 2 3 28272625242322201918171312111087654 9 14 15 16 21

29303132333435363738394041424344454647484950515253545556A

22C

E1

A21

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

Vcc

_9

CE

0V

PE

NR

P

Vss

_21

CE

2A

23B

YT

EA0

DQ

0D

Q8

DQ

1D

Q9

Vcc

_37

DQ

2D

Q10

DQ

3D

Q11

Vss

_42

VC

CQ

DQ

4D

Q12

DQ

5D

Q13Vss

DQ

6D

Q14

DQ

7D

Q15

ST

SO

EW

EN

C56

100n

F

C14

7

100n

F

C13

3

U9

512K

x8_S

RA

M/S

OJ3

6

107 8 11 12

33 32 2117

23 22 20

1 2 3 4 5 14 15 16 18

2428 2526293031

136

3435

927 1936

GN

D_1

0

D0

D1

D2

D3

A14

A13 A

9A

7

A11

A10 A

8

A17

A0

A1

A2

A3

A4

A5

A6

A18

A12

GN

D_2

8

D4

D5

D6

D7

OE

WE

CE

A15

A16

VC

CV

CC

_27

NC

_19

NC

_36

LK5

SM

LIN

K(0

R)

a b c

U8

512K

x8_S

RA

M/S

OJ3

6

107 8 11 12

33 32 2117

23 22 20

1 2 3 4 5 14 15 16 18

2428 2526293031

136

3435

927 1936

GN

D_1

0

D0

D1

D2

D3

A14

A13 A

9A

7

A11

A10 A

8

A17

A0

A1

A2

A3

A4

A5

A6

A18

A12

GN

D_2

8

D4

D5

D6

D7

OE

WE

CE

A15

A16

VC

CV

CC

_27

NC

_19

NC

_36

100n

F

C14

4

100n

F

C9

100n

F

C13

9

100n

F

C13

4

100n

F

C14

2

100n

F

C14

3

100n

F

C10

100n

F

C14

6

100n

F

C15

0

100n

F

C13

6

U12

512K

x8_S

RA

M/S

OJ3

6

107 8 11 12

33 32 2117

23 22 20

1 2 3 4 5 14 15 16 18

2428 2526293031

136

3435

927 1936

GN

D_1

0

D0

D1

D2

D3

A14

A13 A

9A

7

A11

A10 A

8

A17

A0

A1

A2

A3

A4

A5

A6

A18

A12

GN

D_2

8

D4

D5

D6

D7

OE

WE

CE

A15

A16

VC

CV

CC

_27

NC

_19

NC

_36

100n

F

C11

LK7_

2SM

LIN

K(0

R)

a b c

R7

2K5

J19

SDRAM-SOCKET

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

I2C

Con

nect

or

A-B

: C

PU

is c

onne

cted

to

RS

232

trans

ceiv

er.(D

efau

lt)B

-C :

PA

is c

onne

cted

to R

S23

2 tra

nsce

iver

.

10 p

F C

apac

itor i

sno

t fac

tory

fitte

d.

Res

et T

hres

hold

= 3

.08V

Res

et h

eld

low

for

140m

s m

in.

Mak

e th

e cl

ock

trace

as

shor

t as

poss

ible

Pla

ce O

SC

and

C7

foot

prin

t as

nea

r as

poss

ible

toR

S5C

37

PA

DM

A_S

CH

_01_

0010

1.06

PA

D-M

ain

: U

AR

T,

CA

N

and

I2C

Int

erfa

ce,

Res

et a

nd

Rea

l Tim

e C

lock

Cir

cuit

(c)

INIC

OR

E I

nc.

56

00 M

owry

Sch

ool R

d. S

uite

180

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

B

910

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

RX

DG

ND

GN

D

T1I

NT

2IN

R1O

UT

R2O

UT

R2O

UT

T2I

NP

A_T

X1

PA

_RX

2P

A_R

X1

T1I

NC

PU

_GP

IO_T

X2

R1O

UT

GN

DC

PU

_GP

IO_S

DA

CP

U_G

PIO

_SC

LV

DD

33

GND

VDD50

CP

U_G

PIO

_SC

L

CP

U_G

PIO

_SD

A

GN

D

CLK

32K

RE

SE

T_N

GN

D

VDD33

VD

DR

TC

PA

_TX

2

CP

U_G

PIO

_RX

2C

PU

_GP

IO_R

X1

CP

U_G

PIO

_TX

1

GN

D

GN

DV

DD

50

RT

SDC

DD

SR

DT

RC

TSR

XD

TX

D

TX

D

GN

D

GN

D

CP

U_I

RQ

1

RX

D1

PA

_TX

D1

RX

D2

PA

_TX

D2

PA

_RX

2

PA

_TX

D1

PA

_RX

1

PA

_TX

D2

PA

_TX

2

RX

D1

PA

_TX

1

RX

D2

RE

SE

T_N

CP

U_I

RQ

[2:0

]

CLK

32K

CP

U_G

PIO

_RX

2C

PU

_GP

IO_T

X2

CP

U_G

PIO

_RX

1C

PU

_GP

IO_T

X1

CP

U_G

PIO

_SD

AC

PU

_GP

IO_S

CL

VD

D50

VDD

33

VDD

33

VDD

33

VDD

33

VDD

50

VDD

50

VDD

33

VDD

33

J15

CO

N4A

1 32 4

100n

F

C1

JUM

PE

R2-

1

J4_2

12

3

abc

U2

MA

X32

23

1819 11

2 4 5 63 71

1420 16

913 1217

8

15

10

GN

DV

CC

INV

ALI

D

C1+

C1-

C2+

C2-

V+

V-

EN

FO

RC

EO

N

FO

RC

EO

FF

R1I

N

R2I

NT

1IN

T2I

N

T1O

UT

T2O

UT

R1O

UT

R2O

UT

JUM

PE

R2-

1

J3_1

12

3

abc

100n

F

C15

1

J5_1

JUM

PE

R1

12

100n

F

C5

R1

0R

R4

120

J35

CAN1

5 9 4 8 3 7 2 6 1

JUM

PE

R2-

1

J3_2

12

3

abc

Y1

32KHz

100n

F

C78

R6

120

R3

10K

U7 TP

S38

20-3

3

1 2 345

RS

T

GN

D

RS

TM

R

VD

D

JUM

PE

R2-

1

J4_1

12

3

abc

J33

UART1

1 2 3 4 56 7 8 9J5

_2JU

MP

ER

11

2

100n

F

C79

100n

F

C8

D1

BA

T54

C/S

OT

3

12

BT

1

BA

TT

ER

Y/3

V

R16

410

K

J9_1

JUM

PE

R1

12

100n

F

C2

+C

61u

F

R2

0R

100n

F

C3

J6_2

JUM

PE

R1

12

J36

CAN2

5 9 4 8 3 7 2 6 1

J9_2

JUM

PE

R1

12

U6 R

S5C

372A

1 2 3 45678

INT

RB

SC

L

SD

A

GN

DIN

TR

A

OS

CO

UT

OS

CIN

VD

D

U4

PC

A82

C25

0

1 2 3 45678

TX

DG

ND

VC

CR

XD

VR

EF

CA

NL

CA

NH

RS

J34

UA

RT

2

12

34

56

78

9

10pF

C7

SW

1R

eset

U3

PC

A82

C25

0

1 2 3 45678

TX

DG

ND

VC

CR

XD

VR

EF

CA

NL

CA

NH

RS

J6_1

JUM

PE

R1

12

100n

F

C4

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

PA

_GP

IO1_

10 to

PA

_GP

IO1_

18ar

e H

ighs

peed

wire

s.N

o vi

as o

n th

ese

wire

s an

d as

shor

t as

poss

ible

Prin

t o

n P

CB

: U

IO1

and

the

pin

num

bers

1,1

1,21

and

31.

Prin

t on

PC

B :

UIO

2 an

d th

e pi

n nu

mbe

rs 1

,11

, 21,

31,

41,

51

and

61.

Print on PCB: GPIO_1 and the numbers 0 through 18

Prin

t on

PC

B

: U

IO4,

and

the

pin

num

ber 1

Prin

t on

PC

B a

ll si

gnal

nam

es, w

ithou

t pre

fix "

CP

U_"

.

Prin

t on

PC

B :

UIO

3 a

nd th

e pi

n nu

mbe

rs 1

, 11,

21, 3

1, 4

1, 5

1 an

d 61

.

Prin

t on

PC

B a

ll si

gnal

nam

es, w

ithou

t pre

fix "

CP

U_"

.

Prin

t on

PC

B a

ll si

gnal

nam

es, w

ithou

t pre

fix "

CP

U_"

.

PA

DM

A_S

CH

_01_

0010

1.06

PA

D-M

ain

: U

SE

RI/

Os

and

Pro

toty

ping

Are

a

(c)

INIC

OR

E I

nc.

56

00 M

owry

Sch

ool R

d. S

uite

180

New

ark,

CA

945

60

T:

510-

445-

1529

F

: 51

0-65

6-09

95

ww

w.in

icor

e.co

m

B

1010

Thu

rsda

y, D

ecem

ber

20,

2001

Title

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

GN

DC

PU

_D1

CP

U_D

3C

PU

_D5

CP

U_D

13

CP

U_D

7C

PU

_D9

CP

U_D

11

CP

U_D

15

CP

U_A

3C

PU

_A2

CP

U_A

7C

PU

_A4

CP

U_A

5C

PU

_A6

CP

U_A

1G

ND

CP

U_A

11C

PU

_A10

CP

U_A

15C

PU

_A12

CP

U_A

13C

PU

_A14

CP

U_A

9C

PU

_A8

CP

U_A

19C

PU

_A18

CP

U_A

23C

PU

_A20

CP

U_A

21C

PU

_A22

CP

U_A

17C

PU

_A16

CP

U_U

B_N

CP

U_

WR

_N

CP

U_C

S1_

NC

PU

_OE

_NC

PU

_WA

IT_N

CP

U_C

S0_

N

CP

U_L

B_N

GN

D

CP

U_C

S3_

NC

PU

_CS

2_N

GND

VDD33

CP

U_I

RQ

0C

PU

_IR

Q2

CP

U_I

RQ

1

VD

D33

PA

_GP

IO2_

8

PA

_GP

IO2_

2

PA

_GP

IO2_

6P

A_G

PIO

2_4

PA

_GP

IO2_

0

PA

_GP

IO1_

3

PA

_GP

IO1_

1

GN

D

PA

_GP

IO1_

16

PA

_GP

IO1_

15

PA

_GP

IO1_

8

GN

D

GN

D

PA

_GP

IO1_

10

PA

_GP

IO1_

0

PA

_GP

IO1_

6

GN

D

PA

_GP

IO1_

13

PA

_GP

IO1_

9

GN

D

PA

_GP

IO1_

12

PA

_GP

IO1_

11

PA

_GP

IO1_

14

PA

_GP

IO1_

4

GN

D

PA

_GP

IO1_

2

PA

_GP

IO1_

7

PA

_GP

IO1_

5

GN

D

SD

_DQ

46

SD

_DQ

52

SD

_DQ

44

GN

D

GN

D

SD

_DQ

42

SD

_DQ

54

SD

_DQ

41

SD

_DQ

53

SD

_DQ

59

GN

D

SD

_DQ

38S

D_D

Q40

SD

_DQ

32

GN

D

GN

D

GN

DS

D_D

Q62

SD

_DQ

57

GN

DS

D_D

Q39

GN

D

SD

_DQ

51

SD

_DQ

47

SD

_DQ

36

SD

_DQ

55

SD

_DQ

33

SD

_DQ

45

SD

_DQ

49

SD

_DQ

56

SD

_DQ

50

SD

_DQ

43

SD

_DQ

60S

D_D

Q61

SD

_DQ

37

SD

_DQ

63

SD

_DQ

58

SD

_DQ

34

SD

_DQ

48

SD

_DQ

35

PM

C_A

D56

GN

D

GN

D

PM

C_J

3_5

PM

C_A

D34

PM

C_A

D46

PM

C_A

D58

GN

D

PM

C_A

D54

PM

C_J

3_3

PM

C_A

D32

PM

C_A

D44

PM

C_A

D52

GN

D

PM

C_A

D38

GN

D

PM

C_A

D42

PM

C_A

D48

GN

DP

MC

_PA

R64

GN

D

PM

C_A

D60

PM

C_A

D36

GN

D

GN

D

PM

C_A

D62

GN

D

GN

D

PM

C_C

BE

5_N

PM

C_A

D50

GN

D

PM

C_C

BE

7_N

PM

C_A

D40

GN

DP

A_G

PIO

1_17

GN

DP

A_G

PIO

1_18

PM

C_U

IO19

GN

DP

MC

_UIO

22

PM

C_U

IO26

GN

D

PM

C_U

IO20

PM

C_U

IO34

PM

C_U

IO38

PM

C_U

IO1

PM

C_U

IO5

PM

C_U

IO46

PM

C_U

IO32

PM

C_U

IO18

PM

C_U

IO16

PM

C_U

IO37

GN

D

PM

C_U

IO23

PM

C_U

IO17

PM

C_U

IO7

GN

D

PM

C_U

IO33

PM

C_U

IO28

PM

C_U

IO45

GN

D

PM

C_U

IO24

GN

D

PM

C_U

IO43

GN

D

PM

C_U

IO40

PM

C_U

IO15

PM

C_U

IO30

PM

C_U

IO2

PM

C_U

IO14

PM

C_U

IO6

GN

D

PM

C_U

IO21

PM

C_U

IO35

GN

D

PM

C_U

IO25

PM

C_U

IO39

PM

C_U

IO4

PM

C_U

IO13

GN

D

PM

C_U

IO31

PM

C_U

IO44

PM

C_U

IO9

PM

C_U

IO36

PM

C_U

IO12

GN

D

PM

C_U

IO3

PM

C_U

IO11

GN

D

PM

C_U

IO27

GN

D

PM

C_U

IO10

PM

C_U

IO41

GN

D

PM

C_U

IO29

PM

C_U

IO8

PM

C_U

IO42

GN

D

GN

D

GN

D

GN

D

VD

D33

GN

D

GN

D

GN

D

PM

C_V

IO3

PM

C_A

D55

PM

C_C

BE

6_N

GN

D

GN

D

GN

D

PM

C_A

D63

PM

C_A

D35

PM

C_A

D53

PM

C_V

IO1

PM

C_J

3_4

PM

C_A

D43

PM

C_C

BE

4_N

PM

C_A

D39

PM

C_A

D57

PM

C_A

D33

GN

D

PM

C_A

D47

PM

C_V

IO2

PM

C_A

D37

PM

C_A

D49

PM

C_A

D61

PM

C_A

D45

PM

C_A

D51

GN

DG

ND

PM

C_J

3_2

PM

C_A

D59

PM

C_J

3_1

PM

C_V

IO4

PM

C_A

D41

GN

D

PA

_GP

IO2_

7P

A_G

PIO

2_5

PA

_GP

IO2_

1P

A_G

PIO

2_3

GN

D

GN

D

CP

U_D

10

CP

U_D

2C

PU

_D0

CP

U_D

6

GN

D

CP

U_D

4

CP

U_D

14C

PU

_D12

CP

U_D

8

SD

_DQ

[63:

0]

PM

C_U

IO[4

6:1]

PM

C_A

D[3

1:0]

CP

U_A

[23:

1]

CP

U_D

[15:

0]

CP

U_I

RQ

[2:0

]

CPU

_IR

Q[2

:0]

PM

C_A

D[6

3:32

]

PA

_GP

IO1_

[18:

0]

PA_G

PIO

1_[1

8:0]

PA

_GP

IO2_

[8:0

]

CP

U_W

AIT

_N

CP

U_

WR

_N

CP

U_U

B_N

CP

U_L

B_N

CP

U_O

E_N

CP

U_C

S2_

NC

PU_C

S1_N

CPU

_CS3

_N

CPU

_CS0

_N

PM

C_C

BE

5_N

PMC

_CBE

4_N

PMC

_CBE

7_N

PMC

_CBE

6_N

PM

C_P

AR

64

PM

C_V

IO2

PMC

_VIO

1

PMC

_VIO

3PM

C_V

IO4

PM

C_J

3_3

PMC

_J3_

1

PMC

_J3_

4PM

C_J

3_5

PMC

_J3_

2

CP

U_F

IRQ

VD

D33

VDD

33

J28

UIO3

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64

J32

CPU_DATA

1 3 5 7 9 11 13 15 17 19

2 4 6 8 10 12 14 16 18 20

J30

CPU_CTRL

2 4 6 8 10 12 14

1 3 5 7 9 11 13

J27

UIO2

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64

TP

14

SO

LDE

R P

OIN

TS

/16X

16

J26

UIO1

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

J31

CPU_ADDR

2 4 6 8 10 12 14 16 18 20 22 24

1 3 5 7 9 11 13 15 17 19 21 23

J29

UIO4

2 4 6 8 10 12 14

1 3 5 7 9 11 13