probe debugging

Software Engineering Software Engineering Methodology for Methodology for Reconfigurable PlatformsReconfigurable Platforms

Damien Picard and Loic Lagadec Architectures et Systèmes, Lab-STICC

Université de Bretagne Occidentale, France

ESUG’09Brest, France, 2009

2D. Picard, L. Lagadec ESUG’09 - Brest

IntroductionIntroduction Increasing complexity of modern System-on-Chip

Difficulty to program and to validate applications Shrinking time-to-market

Common techniques for hardware validation Testing/debugging at a very low abstraction level

Time-consuming and burdensome

Need for productive methodologies with an higher level approach Software development benefits from very efficient

techniques Our approach: applying software engineering

methodologies to hardware design


Aim of this talkAim of this talk This talk focuses on a key issue: validation of

hardware application targeting RA

An HL synthesis flow for reconfigurable architectures based on MADEO [ESUG 08]

Multi-level simulation: from behavioral to hardware Interfacing with third-party tools through code generation Software-like debugging features embedded in hardware

Advocates for the use of software engineering techniques Short development cycles, use of OO models, code

generation, etc.


OutlineOutline1. Overview of Reconfigurable Architectures

2. OO methodology for synthesis on RA

3. Simulation and testing methodology

4. Software-like debugging for RA

5. Conclusion






5. Conclusion


Reconfigurable ArchitecturesReconfigurable Architectures A reconfigurable architecture is a run-time programmable

architecture based on the hardware reconfiguration

Used as flexible hardware accelerators for intensive computations Based on Look-Up-Table (LUT) = memory General-purpose and high parallelism Slow and area/power-inefficient (routing overhead)

Several reconfigurable platforms FPGAs (vendors, e.g. Xilinx, Altera) eFPGAs (e.g. M2000, Menta) RSoCs (e.g. Morpheus project): RA IP composition

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Reconfigurable Architectures

Trade-off between flexibility/performance Functionality of the circuit determined by a

configuration

Flexibility Performance

Processor Reconfigurable Architecture ASIC

Results

DataProgram Configuration Data Data

Results Results


Reconfigurable Architectures FPGA: a general overview

Organized as a mesh of look-up-tables Possibly heterogeneous

Computingresource

Programmableinterconnection

I1+i2i1

i2

LUT LUT

LUT

LUTLUTLUT

LUT

+

-

i1

i2I1-i2

LUT

LUT IO

µP

I1*i2i1

i2

*






5. Conclusion


The MADEO frameworkThe MADEO framework Loic Lagadec’s talk: “MADEO: A CAD Tool for

Reconfigurable Hardware” [ESUG 08]

MADEO is a generic synthesis framework for RA Set of open tools designed with OO principles for fast

evolution Enables design-space exploration

Application of OO methodology for synthesizing circuits Flexibility through generic OO model with a common API Adapt to new RA “retargetable compiler” Produce circuits from HL pure OO code: Smalltalk


SmalltalkMethod

Netlist

MadeoSynthesis Tools

ConcreteArchitecture

InstantiationAbstractModel

ArchitectureDescription

Application Target

Madeo: Global FlowMadeo: Global Flow

Place&Route

Configuration(bitstream)


sad4p1: p1 p2: p2 | sub0a sub1a sub0b sub1b sub0 sub1 cond0 cond1 p10 p11 p20 p21 | p10 := p1. p11 := p1 bitShift: 8. p20 := p2. p21 := p2 bitShift: 8. sub0a := p10-p20. sub0b := p20-p10. cond0 := sub0a<0. sub0 := cond0 ifTrue:[sub0b] ifFalse:[sub0a]. sub1a := p11-p21. sub1b := p21-p11. cond1 := sub1a<0. sub1 := cond1 ifTrue:[sub1b] ifFalse:[sub1a]. ^sub0+sub1.

A complete implementationA complete implementation




The MADEO frameworkThe MADEO framework Software-engineering concepts applied to logic

synthesis on reconfigurable architectures

MADEO: extensive use of OO methodology Modeling, generic tools through polymorphism

An HL synthesis flow for RSoC based on the MADEO approach with validation methodology Multi-level simulation: from behavioral to hardware Target modeling Interfacing with third-party tools through code generation Software-like debugging features embedded in hardware






5. Conclusion


Global FlowGlobal FlowSmalltalkMethod

High-levelCDFG

Low-levelCDFG

SoC Model

Multi-LevelSimulator

ExportTesting

Netlist

Back-endTools

SystemSimulator

Global Simulation

System BehaviorGantt Diagram

Interaction Diagram

Application BehaviorWaveform

ComponentsFramework

Debugging

Iterations

SynthesisCDFG


Platypus tool

CDFG designCDFG design

CDFG EXPRESS

model

Tool X

Tool YHLL CDFG API (Java)

CDFG instances(STEP files)

CDFG Checker

Madeo+ synthesis tool

CDFG UseCDFG Use

Target 3

Specific Assembly code

Target 2

C like code

Target 1

EDIF

Target architecture description

HLL CDFG API (Smalltalk)

ENTITY HierarchicalNode SUBTYPE OF (Node);localVariables : LIST OF AbstractData;subOperators : LIST [1 : ?] OF Node;

END_ENTITY;

ENTITY AccumulatorNode SUBTYPE OF (HierarchicalNode);init : AbstractData; --”AccumulatorNode.init” the initial value we start accumulating from.toBeAccumulated: AbstractData;

DERIVEcumulatedArguments : LIST OF AbstractData := subOperators [ SIZEOF (subOperators)].outputs;

WHEREtoBeAccumulatedSource: SIZEOF ( cumulatedArguments )=1;typeCompat: cumulatedArguments[1].type = init.type;

END_ENTITY;

APPLICATIONAPPLICATION

16

[Lagadec, ESUG08]


Application Intermediate RepresentationApplication Intermediate Representation Hierarchical Nodes

structuring process sequencing loop conditional Atomic Nodes

compute constants memory access communications/synchronizations


Application refinement at RTL LevelApplication refinement at RTL Level Low-level CDFG

Inherited from the CDFG framework Produced from high-level CDFG mapping Bound to an architecture

Additional constructs for hardware level Primitive operators linked to libraries Registers/flip-flop FSM description (KISS format) Random logic (BLIF format)

Taken as input of: Synthesis tool EDIF generation RTL-level simulator


Link between abstraction-levelsLink between abstraction-levels How keeping the link between HL-CDFG

variables and LL-CDFG signals?

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Software abstraction Implementation in hardware

?Synthesis


Link between abstraction-levelsLink between abstraction-levels HL variable linked to its LL bit vector

HL Variable Signal bit vector1:n


Multi-Level Simulation EnginesMulti-Level Simulation Engines Behavioral specification of the application: Smalltalk

Direct execution by ST virtual machine environment Use of system-level simulator API in code

High-level CDFG produced from Smalltalk code Each node is simulated in function of sequencing nodes CDFG API for design pattern: Visitor, Composite

Low-Level CDFG RTL-Level simulator takes as input a low-level CDFG Link between HL and LL CDFG

For example loop indices Tracing signals

Waveforms generation


System Modeling FrameworkSystem Modeling Framework Component approach

Hierarchical composition Modularity and reusability

Component characteristics Declaration and scheduling of encapsulated processes Port interfaces for connections and communications between

components Local communications between processes through local channels

P3

P1

P2

P1

P2

Component #Main

Component #Unit1 Component #Unit2


System Modeling FrameworkSystem Modeling Framework Component class hierarchy

Connection class hierarchy

Component

User Class #Main User Class #Unit1 User Class #Unit2

AbstractionLevel

Connection

FIFO Blocking Channel

AbstractionLevel

Inheritance relation


System-Level SimulationSystem-Level Simulation Framework of classes

Based on an event-driven simulation kernel [Blue Book] Defines an API for simulating operator latencies,

scheduling, stopping activities System modeling framework inherits from the simulator

Simulator + modeling class hierarchy

SimulationObject

Component Connection

Simulation

User Model


ExampleExample Case Study

Partial modeling of a reconfigurable system-on-chip System activities: DAM transfers, synchronizations, etc.

Application accelerated on a RA

Bus

CPU

ReconfigurableAccelerator

DMA Memory

LocalMem.


System simulationSystem simulation Interaction diagram between components

Behavior of the system and the application


LL-CDFG simulationLL-CDFG simulation Cycle-accurate simulation

Stimuli on LL-CDFG signal interface defined in a method of the accelerator component

Interface between the system and accelerated function

Tracing values for LL-CDFG simulation Simulator defines an API to set probes on the LL-CDFG

signal interface Tracing of the signal values Graph generation


Tracing signalsTracing signals Traced signals and stimuli set through a GUI


LL-CDFG simulationLL-CDFG simulation Traces produced from signals

Values tested against expected results: SUnit testing


Testing methodology: SUnitTesting methodology: SUnit Unit test for synthesis result

Characterization test between two simulations test2 CDFGSynthesisAPI new example: 'example.step' family: 'F4' primitives: true. res := self readResult. CDFGSynthesisAPI new example: 'example.step' family: 'F4' primitives: false. res2 := self readResult. self assert: res = res2

test1 self shouldnt: [CDFGSynthesisAPI example1] raise: TestResult error


Validation with manufacturer toolsValidation with manufacturer tools

SmalltalkMethod

High-levelCDFG

Low-levelCDFG

Export

Netlist

Back-endTools

Synthesis

Mainstream/proprietarysimulation tools

(cell library)


Interfacing with third party toolsInterfacing with third party tools In a classical hardware design flow system activities

interacting with the application’s interface are modeled in a wrapper

An hardware engineer would do: Wrapper is hand-written in HDL (VHDL, Verilog)

Time-consuming and error prone Very low abstraction level and specific

Need deep update for new application

Increasing productivity by scripting and generating HDL wrapper Interfacing with mainstream HDL simulation tools

Application

WrapperInterface


Stand-Alone LL SimulationStand-Alone LL Simulation Dependencies on signals used for interacting with

the LL-CDFG Possibility to script execution scenarios through the

instantiation of dependency objects triggering actions No hardware details (signal declarations, etc.)

Set of interactions between the system and the application defined by a set of dependencies Dependencies ~ mock object


Multi-levelsimulator

Wrapper GenerationWrapper Generation

NetlistVerilog

Results

WrapperVerilog

Simulation script(Mock object creation)

SmalltalkMethod

HL-CDFG

Export

ModelSim

Synthesis

LL-CDFG


Dependency ModelDependency Model Stopping the simulation

Triggering a signal on change

Simulator onChange: (Simulator synthesizedCDFG outputNamed: 'done') relation: '=' value: 1 depName: 'Task Done’ action: Simulator stop.

Simulator onChange: dma_Ack_Read relation: '=' value: 1 depName: 'dma_ack_read' action: (SimulatorForceSignal forceSignal: (dma_Req_Read) to: 0 in: 10).


Generated HDL (Verilog)Generated HDL (Verilog) Stopping the simulation

Triggering a signal on change

Looks shorter but is missing: signal declarations, module declarations, interconnections and other LL details ST coding + generation enable to save 50% of the designer’s coding effort

initial begin @(posedge done); - - HALT $stopend

always @(posedge dma_ack_read) begin #(PERIOD * 10) dma_ack_read = 0;end


Simulation by third party toolsSimulation by third party tools Link: signal/LUT names LL-CDFG HL-CDFG

Enables to go back to the highest abstraction level

Modelsim (Mentor Graphics)






5. Conclusion


After Testing FailedAfter Testing Failed Multi-level simulation enables to test the application

at any flow stage

Use software engineering techniques Testing at all level with SUnit Modeling approach with generic models

Platform , application, interactions

Interfacing with third-party tools Automated code generation

If validation failed… …Time for debugging

Testing

Debugging


Debugging and exploration facilitiesDebugging and exploration facilities Example: Visualworks’ debugger


Methods and Tools for Software DebuggingMethods and Tools for Software Debugging

Debugging facilities in Smalltalk environment Conditional breakpoint and watchpoint inserted/modified

dynamically Hot-code replacement Deep exploration of the execution context Message stack control

Short iterative cycles: edit-compile-run-debug Fast development

These software features do not exist in hardware No symbolic debugging, no execution stack, etc.




Debugging HardwareDebugging Hardware Common hardware debugging methodology for RA

Hardware simulation, embedded logic analyzer… Powerful tools but debugging is performed at hardware level

Trade-off performance/complexity exposed to the designer

Complexity

SystemC

ModelSimHDL

ELA

Software

Trade-off

Hardware

Performance


From Software to Hardware DebuggingFrom Software to Hardware Debugging Reconfigurable circuits can support the main

advantages of software engineering methodology A bridge between software and hardware world

Reconfigurability enables to re-used the circuit Possibility to iterate on a design edit-compile-run ~ edit-synthesize/configure-run Synthesis is time-consuming

Debugging the application in-situ with a specific interface

Gain in performance


Global FlowGlobal FlowSmalltalkMethod

High-levelCDFG

Low-levelCDFG

Multi-LevelSimulatorExport

Probed Netlist

Synthesis

ProbeInsertion

ReconfigurableArchitecture


Probing Hardware : PrinciplesProbing Hardware : Principles From software to hardware probes

Watchpoints and breakpoints concepts

Controllability over hardware execution Software debugger features added to hardware application

Benefit from reconfigurability Debugging support automatically inserted by the design

framework (probes + controller) All debugging features removed once design is validated


Probing signalsProbing signals Breakpoints set through a GUI


Embedding software debugger featuresEmbedding software debugger features Execution is controlled by the debugger

Breakpoints interfaced with a debug controller

OpOp

Op

Op

Op

Op

Op

Op

Synthesis

Debugctrler

Simulator

Schedulecontroller

Control interface

Control interface


Hardwired BreakpointHardwired Breakpoint Freeze the execution when triggered

Limit on conditional operators Hierarchical low-level CDFG

Local Controller

Global OR

TopHier1Hier2

=!=<>

=!=<>

OpN

Op

Conditionnal breakpoint

Conditionnal breakpoint

Value

Value

OpSel

OpSel

i1i2

i1i2

O

O

Enable operatorsControl

Debugging Controller


Hardwired BreakpointHardwired Breakpoint Configurable breakpoints

Pool of probed signals is static Breakpoint condition are configurable and can be enabled/disabled Possibility to speculate and to backtrack execution No-need for re-synthesis

Configuration structure 2-D vector Configuration word: contains operator selection, activation status and

arguments

Extraction of the debug information: two execution modes Running mode Debug mode

Execution control: step-by-step, resume Read back of the debugging information


Hardwired WatchpointHardwired Watchpoint Probed signals are wired to the top interface

Automatically crosses the hierarchies Possibly conditional Trace analysis

Hierarchical low-level CDFG

TopHier1

Hier2

Op

Probed signal


ExampleExample

Execution Frozen






5. Conclusion


ConclusionConclusion Methodology for validating an application running on a

RSoC Multi-level simulation of the application specified as CDFG High-level modeling of platform by a component-based approach

Benefit from software expertise for hardware design Taking advantage of the Smalltalk dynamic language and

environment Debugging techniques from software to hardware Short cycle and iterative developments

Software engineering techniques increase productivity


Future workFuture work Dynamic insertion of HW breakpoints into the

application Synthesizing probes on demand / partial reconfiguration

SUnit embedded in hardware Synthesizing assertions in the netlist

Interfacing the synthesized application with high-level software tools Inspector utility on the circuit Collecting state values of the HW application at high-level


Thank you !Thank you !

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probe debugging

Technology

testing methodology

outline overview

ra simulation

synthesis

debugging

esug 08

madeo