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Probing Strategies for Through-Silicon Stacking

Eric Strid, Ken Smith, Peter Hanaway, Reed Gleason Cascade Microtech – Beaverton, Oregon

Abstract

•  Abstract: Wafer-level screening of die for through-silicon stacking requires various wafer probing strategies, depending upon the application. Probing on microbumps will generally be necessary for screening ICs as their complexity increases, to adequately power the IC, run at-speed or analog tests, check through-silicon via (TSV) connectivity, run parametric tests on I/O drivers, etc. Test throughput and cost can benefit from contacting many more I/Os available at the microbumps vs. limiting test access to larger test pads. Probe cards will need to scale down pitch, tip forces, and cost per area; and practical examples of each are demonstrated. The likelihood of standard microbump footprints favors MEMS probe cards. More footprint standardization is possible and would be beneficial.

Probing Strategies for TSS

•  Motivation

•  Some 3D-TSV applications and test options landscape

•  Status of probe technology for microbumps data

•  Standards would make life much easier speculation

•  Conclusions

Motivation

•  Variety of stack architectures and

•  Unknown IC and stacking yields beget –  A variety of potential test strategies, which imply –  Highly uncertain test requirements

•  Waiting for the market to form does not allow enough development time

How can infrastructure players mitigate these uncertainties?

What puzzle pieces can we fill in?

The Silicon Stacking Revolution •  Pent-up demand for more connectivity and lower power

•  Expect 10X, then 100X or 1000X more I/Os per die

•  Test and probing solutions are truly at a crossroads –  Test strategies and tools must address the explosion in I/O count,

with no decrease in test coverage and no increase in test cost per circuit function

–  Some sort of probing will be necessary for KGD

–  Probe card mechanics must be scaled to smaller pitches and forces

–  Probes must address the tighter pitches and higher pincount, even if the signal count does not increase

–  Probing must be compatible with bonding processes

Probing Strategies for TSS

•  Motivation

•  Some 3D-TSV applications and test options landscape

•  Status of probe technology for microbumps data

•  Standards would make life much easier speculation

•  Conclusions

TSV Application: Stacked Memory Dice

•  Memory ICs stacked with TSVs under the bond pads •  70-100 um pitch •  KGD test: conventional probing by memory vendor •  Logistics: OSATs or IDMs thin, add TSVs (vias-last), stack, test

Face

Back

3D-TSV DRAM Device Test Flow

8 R7 Sept 29, 2011

Burn-In

Sort (s1)

Sort (s2)

Laser Repair

High-Speed Sort (s3)

Die Stacking

Burn- In

Final Test Ship

Wafer-Level Test 3D “Package” Test

Uses Aluminum Sacrificial Pads

On Die

or

Highest Yield by Probing TSV

Highest Yield by Probing TSV

“Traditional” Memory Probe Card

TSV Probe Card

KGD Bare Die

Socket

KGS Socket

•  Memory IC stack (cube) is stacked onto a low-power ASIC

•  ASIC KGD test: Conventional probing on solderballs pre-thinning

ASIC (processor)

Memory Memory “Cube”

•  Probe the TSVs to test continuity? (on carrier wafer?)

•  Stack test: Probe the stack? After package?

•  Memory KGD test: Extra pads & BIST for conventional probing •  Known-good cube test: D2W? Cube handling? Test on extra pads?

TSV Application: Memory Cube on ASIC

TSV Application: 2.5D Interposer •  Higher yields from sorted, smaller die

•  More and shorter interchip I/Os, lower power and latency

•  Better power integrity from capacitance in the interposer

•  KGD test: Must probe the microbump pads

•  Interposer test: Pray or some level of opens-shorts testing

Heatsinking

Die 1 Die 2

Passive interposer

TSV Application: DRAM for ASIC/MPU •  Memory IC stacked F2F onto a high-power processor

–  Vias-mid through the RAM to conventional flip-chip at ~150 um pitch •  ASIC KGD test: Must probe the TSV pads; RAM pads optional •  Memory KGD test: Extra pads & BIST or probe the microbumps •  Stack KGD: Probe the solderballs conventionally •  Logistics: Many questions

Heat sink ASIC (processor)

Package PCB

Memory

⇒ Microbump probing necessary to power & test the ASIC and may be necessary to power and test the RAM

Future: Multi-function Stacks •  Logic, SoC, memory, sensor functions stacked with vias-mid

–  Potential to become the new PCB •  KGD test: Probing the TSVs or microbumps will maximize power

integrity, test coverage, and test throughput •  Other approaches

–  Probe microbumps on one side for scan or functional test –  Probe TSVs on backside for leakage and connectivity –  Self-test and self-heal

Power control Memory

⇒ TSV or microbump probing likely necessary for KGD

Logic Sensor

Probing Strategies for TSS

•  Motivation

•  Some 3D-TSV applications and test options landscape

•  Status of probe technology for microbumps data

•  Standards would make life much easier speculation

•  Conclusions

3D Probing Requires Lower Tip Forces

Force per tip

(gf)

Array Pitch (um) 400 200 100 50 25 12 800 6 3 1600

Spring pins

Conventional probe cards

20

10

5

2

1

0.5

0.2

15

Scaling a Probe Card Technology

100 um pitch ~10 gf/tip

35 um pitch ~1 gf/tip

•  Decrease XYZ dimensions by K •  Same materials •  Decrease Z motions by K •  Force per tip decreases by K2; tip pressure constant

3D Probing Requires a New Cost Structure

Price per pin

DRAM & Flash

Logic/SoC

Technology must be printed, repairable, scalable, compliant Array Pitch (um)

400 200 100 50 25 12 800 6 3 1600

Contact Resistance Proven

Lifetests

Gold Copper Tin

Probe Mark Size and Uniformity

Maximum depth 100 nm Maximum berm 500 nm

Highly uniform

Compatible with thin Au

Routing the New Pitches

•  Fully-routed 40/50 um pitch •  New space transformer technologies

Probing Strategies for TSS

•  Motivation

•  Some 3D-TSV applications and test options landscape

•  Status of probe technology for microbumps data

•  Standards would make life much easier speculation

•  Conclusions

Standard Pad Locations Change the Game •  Required for vendor interchangeability

•  Standard physical specs for pads required—materials, thicknesses, flatness, etc.

•  Standard pad locations enable standard test tooling

Pad locations must survive shrinks Pad

area High-power ICs can use extra P and G pins all over the die ⇒ I/Os are in center instead of periphery

Number of Pads vs. Time •  Driven by I/O bandwidths

–  Processors need ~10X every four years –  Speed of DRAM cells doesn’t scale

•  TSV density ~4X every three years? •  I/O counts not compatible with incumbent ATE

–  Test bandwidth limited by scan methods

2012 2015 2018

Array pitch (um) 40 20 10

# pads in 4X4 mm area 10k 40k 160k

# pads in 8X8 mm area 40k 160k 640k

A Brave New World of Standard Interconnects?

•  Through-silicon stacking eliminates the pitch limitations of assembly and packaging processes

•  Inter-tier connections clustered in middle of die

•  So why not adopt standard pitches? –  Facilitates standard I/O cells –  Facilitates stacking by having interconnects in standard

places –  Facilitates test tooling

•  How would that work?? –  Like every connection on a 40 um grid—or 30, 20, 10 –  Standard pad locations for powers and grounds –  Lots of pads enable layouts to skip unused pads –  Is a general-purpose tiling pattern practical?

Could Standard Pad Locations Enable Stacking Anything on Anything? •  Example: RF on power management on memory on processor •  All with the same pad pattern? •  Dense enough for ultra-wide memory •  Plenty of extra pads everywhere

–  Standard pattern for powers & grounds –  Programmable or redundant I/Os –  Network on chip pad areas

NoC cluster

DRAM cluster

Sea of pads elsewhere Issues: Removing heat! Overhead of TSV pass-throughs

Pad Area Example

Probing Strategies for TSS

•  Motivation

•  Some 3D-TSV applications and test options landscape

•  Status of probe technology for microbumps data

•  Standards would make life much easier speculation

•  Conclusions

Conclusions •  TSS will create many new opportunities and

problems in test, but uncertainties abound

•  Optimal test strategies will depend upon the application, assembly flow, and various yields

•  Increasing complexity of applications will require probing of the TSVs or microbump pads

•  Practical probe cards are capable of 40 um pitch and tip forces below 1 gram-force

•  Pad damage at these low forces is extremely small with scrub marks less than 100 nm deep

•  Probing on TSVs or microbumps appears to be viable

Potential Standards

•  Standard assembly and test flows

•  Standard bonding processes, specs

•  Standard footprints –  Defacto footprint standards from JEDEC memory

footprints

–  More general stacking standards?