process development of a novel wafer level packaging with tsv applied in high-frequency range...

REVIEW PAPER

Process development of a novel wafer level packagingwith TSV applied in high-frequency range transmission

Xiao Chen • Jiajie Tang • Gaowei Xu •

Le Luo

Received: 4 September 2012 / Accepted: 6 December 2012 / Published online: 18 December 2012

� Springer-Verlag Berlin Heidelberg 2012

Abstract The process development of a novel wafer level

packaging with TSV applied in high-frequency range

transmission is presented. A specially designed TSV

structure (a core TSV and six shielding TSVs) is adopted to

connect the components on different sides of the high-

resistivity silicon wafer. And the microstrip line in the

microwave monolithic integrated circuit is used to transmit

high-frequency signal in packaging structure together with

the low permittivity intermediate dielectric polymer, ben-

zocyclobutene. The TSV fabrication process and the multi-

layer interconnection is illustrated in details. The electrical

measurement result of the microstrip lines connected by

TSVs reveals the resistances within 0.719 X, a return loss

better than 23.8 dB and an insertion loss better than

2.60 dB from 14 to 40 GHz.

1 Introduction

Continuous increase in demand for product miniaturization,

high package density, high performance and integration of

different functional chips has lead to the development of

three dimensional (3D) packaging technology, in which

multi-chips are assembled by vertical interconnects by

through silicon vias (TSV) at wafer level packaging. 3D

packaging has higher packaging density, shorter intercon-

nection, lower noise and lower profile (Jang et al. 2007;

Beica et al. 2008; Kumagai et al. 2008). In order to achieve

extremely high-density integration, system-in-package (SiP)

encounters the challenges in package size, process, thermal

and electrical performances (Tummala and Swaminathan

2008). The 3D packaging technology with TSV may offer an

optional solution to this problem.

Using the TSV interconnection on SiP, the multi-layer

interconnection and the active components such as MMIC

chips can be separately integrated on each side of the sil-

icon substrate. Because the MMIC chips may take the risk

of the failures in the fabrication processes (Corrosion,

release and high-temperature annealing) when they are

integrated into the substrate. Owing to TSV, the MMIC

chips can be integrated on one side of the wafer after these

fabrication processes and the assembling of other devices

on the other side. Not only the shortest vertical connec-

tions, less loss and parasitic effect can be ensured, but also

the failure and reliability problems can be greatly

decreased. Accordingly, the mass production of the sub-

strate with integrated active/passive devices, MEMS

devices and optoelectronic devices, etc. can be achieved in

advance. Accordance with the recent references (Ho et al.

2008; Lim et al. 2011; Kannan et al. 2011), some pre-

liminary work on the performance of the single TSV in

high-frequency range have been reported. However, the

aspect ratios (AR) of the TSVs fabricated in these papers

are relatively low (AR = 1–3). Moreover, the microwave

performances of the interconnection structure with TSVs

together with the application of different active compo-

nents such as the MMIC chips assembled in the silicon

substrate based SiP are not involved in the previous work.

X. Chen (&) � J. Tang � G. Xu � L. Luo

State Key Laboratory of Transducer Technology,

Shanghai Institute of Microsystem and Information Technology,

Chinese Academy of Sciences, Shanghai, China

e-mail: [email protected]

L. Luo

e-mail: [email protected]

X. Chen � J. Tang

Graduate School of Chinese Academy of Sciences,

Beijing, China

123

Microsyst Technol (2013) 19:483–491

DOI 10.1007/s00542-012-1712-9

In this paper, a wafer-level SiP structure fabricated

between both sides of the silicon wafer using high AR

TSVs (AR = 7) is presented. A specially-designed TSV

structure (a core TSV and six shielding TSVs) through the

silicon can achieve the inter-side connection of the two

sides of the substrate to transmit the high frequency signal

from the MMIC embedded in the silicon substrate to the

other side of the wafer. To reduce the transmission loss of

TSV in high-frequency, the high-resistivity silicon is

adopted as the substrate with BCB as the intermediate

dielectric layer. Besides, the fabrication steps including the

TSV formation and the BCB process on two sides of wafer

are discussed in details. This new technology of two sides

fabrication is a powerful platform for the high-density

integration of microwave application in the complicated

3D package modules.

2 Design and process flow

The special constructure of microwave transmission con-

tains a microstrip line (MSL) on the MMIC embedded in a

high-resistivity silicon substrate, Cu-TSV, BCB/metal

multilayer interconnection, L1 and L2 (the MSL on the

packaging substrate). Figure 1a, b shows the top and cross-

sectional views of the interconnection configuration.

MMIC is used to achieve planar interconnection with BCB

as the intermediate dielectric layer. Similar to the coaxial

line, the structure is composed of a core TSV and six

shielding TSVs. The core TSV transmits signal, and the

shielding TSVs are around the core and connected to the

ground. According to the simulation results, the perfor-

mance of the proposed structure is very close to the coaxial

line case. The TSV (40 lm in diameter with 280 lm in

depth) with vertical profile is fabricated. To further

improve the high-frequency performance, high-resistivity

silicon (3,000–4,000 X cm) is selected as the substrate

material. BCB is an excellent dielectric material with low

permittivity (2.65) and low dissipation factor (0.0008)

(Ding et al. 2009; Seok et al. 2006). It is utilized for its

good chemical resistance, high planarization, low moisture

absorption and photo-sensitive characteristic as well.

The fabrication steps including the TSV formation [the

blind-via etching, seed layer deposition, blind via filling

and chemical mechanical polish (CMP) of Cu] and the

BCB process on two sides of wafer are discussed in details.

Figure 2 shows the whole designed flow of the intercon-

nection method of SiP. First, a cavity is formed for MMIC

embedding by KOH etching (Fig. 2a). After a SiO2 layer

(2 lm thick) is deposited as hard mask, the blind vertical

vias are etched to the desired depth by Bosch etching

(Fig. 2b). The SiO2 mask is removed and a new SiO2 layer

(2 lm thick) is deposited by thermal oxidation to cover the

sidewalls of vias for electrical isolation and the whole

Fig. 1 The top and cross-

sectional views of the

interconnection configuration:

a top view; b cross-section view

484 Microsyst Technol (2013) 19:483–491

123

surface besides the KOH cavities. And the vias are then

coated by Ti as adhesion layer and Cu as seed layer by

electron beam evaporation (Fig. 2c). In addition, a photo-

resist thin layer, which is a mask, is deposited only in the

KOH cavities by the spray photoresist technology, thus the

Ti/Cu layer cannot be deposited in the cavities. In the Cu

electroplating process, the blind vias are filled without

defect (Fig. 2d). After the electroplating, the Cu over

burden on the top of wafer is removed by CMP and the

wafer backside is thinned down to expose the backside of

the TSVs (Fig. 2e). Afterwards, a new seed layer of

TiW/Au (50 nm/300 nm) is sputtered for the multilayer

interconnection. Then the ground layer is fabricated by

electroplating (Fig. 4f). And a BCB layer with a thickness

of approximately 25 lm is deposited followed by BCB

exposure and development. The tapered via-holes take

shape through BCB (Tang et al. 2011). Then a Cr/Au

(50 nm/300 nm) seed layer is deposited on the wafer sur-

face by the magnetron sputtering. Following the lithogra-

phy process, inter-layer connection and L2 are patterned

and electroplated to 3 lm. Thus, the tapered hollow vias

are formed. After removing the photo-resist, the seed layer

is etched by the ion-beam (Fig. 4g) (Tang et al. 2011).

After that, the wafer is turned over. An MMIC chip is

embedded and stuck on the bottom of the trench with silver

paste. After leveling, the embedded wafer is baked in a

150 �C oven for 1 h to solidify the Ag paste (Fig. 4h)

(Tang et al. 2011). A layer of photo-BCB with a thickness

of approximately 25 lm is spin-coated, placed horizontally

for planarization and then baked. (Fig. 2i). Then the

BCB/metal interconnection is fabricated (Fig. 2j) (Tang

et al. 2011).

3 Key technologies of fabrication

In this section, the key technologies, such as the seed layer

deposition into deep vias, Cu electroplating with no voids

and the BCB process will be discussed in details.

3.1 Seed layer deposition into deep blind-vias

The silicon wafer is etched using Bosch deep reactive ion

etch process for a blind vertical via with 40 lm diameter

and 280 lm depth in surface technology system (Fig. 3).

And a SiO2 layer is deposited by thermal oxidation for

electrical isolation, and the vias are then coated by the

adhesion layer and seed layer.

Fig. 2 Process flow of the

interconnection in SiP

Fig. 3 The silicon substrate

with the blind vias and the

trench

Microsyst Technol (2013) 19:483–491 485

123

In this study, the electron beam evaporation technology

is developed to deposit barrier and seed layers into deep

vias. To improve the adhesion and step coverage of the

layers into deep microvias, a deposition program composed

of heating silicon and multi-step evaporation method is

used in evaporation process. And a 0.2 lm titanium layer

as barrier and adhesion layer and a 0.5 lm copper seed

layer are deposited into the vertical deep vias by electron

beam evaporation carried on Sccot-380 equipment. The

electron beam evaporation parameter is summarized in

Table 1. The layer deposition performed on vertical vias

shows a depth of 280 lm and a diameter of 40 lm. The

profile of the thin-film distribution is analyzed from cross-

section of the sample by SEM (Hitachi-S4800). As shown

in Fig. 4, the Ti/Cu layer is very thin on the sidewall of the

deeper vertical vias, and the sidewall is rough due to

BOSCH etching process. The thin seed layer also forms a

continuous conductive layer with thickness ranging from

96 to 320 nm on the vertical sidewall, which remains

acceptable for the copper electroplating of the blind vias.

3.2 Cu electroplating for deep blind-vias

To realize the copper fast-filling without voids into deep

microvias, in this study we use a commercial electroplating

solution (Model: UTP SYS-3320) including three electro-

lyte additives (accelerator, suppressor or leveler) from

Sinyang. In general, the accelerators enhance copper

deposition while the suppressors and levelers suppress the

deposition. The accelerators have much higher diffusion

rates than suppressors and levelers and they are distributed

uniformly in the high AR fast-filling case. The suppressors

and levelers are distributed mostly at the top region of deep

via, only a little at the bottom. Therefore, faster deposition

at the bottom of deep via while suppressing the deposition

at the top is needed for achieving void free filling (Fang

et al. 2011; Tsui et al. 2009), as indicated in Fig. 5.

In the electroplating process, the ultra-sonic treatment is

firstly used to fill the deep via with copper electroplating

solution. Subsequently, the electroplating process for verti-

cal deep via is developed with Cu plating solution. The

current density of the power source is the most important

parameter for improving the via filling quality. After Cu

electroplating into the blind vias, the void appears at the

bottom or the middle of vertical deep via as shown in Fig. 6a, b.

In order to avoid voids in the via, a multi-step electroplating

process is used. First, a low current density (0.8 ASD) is

adopted to realize a most fully filling at the bottom of vias

Table 1 Parameters of the electron beam evaporation

Variable Value

Evaporation rate of Ti 0.2 nm/s

Evaporation rate of Cu 1/3/5 nm/s

Evaporation time of Cu 50/50/60 s

Si temperature 200 �C

Chamber pressure 7.5 9 10-7–8.9 9 10-7 torr

Silicon rotational speed 15 rpm

Fig. 4 SEM images of barrier

layer (Ti) and seed layers (Cu)

deposited in the blind via


123

and the plating time is 2 h. Secondly, the electroplating

current density and plating time are 1.0 ASD and 2 h,

respectively, resulting in a fully filling in the middle. In the

end, the electroplating current density and plating time are

also 1.2 ASD and 1.5 h. In Fig. 6c, the deep via is filled with

copper without any defect (voids or seams).

A thick layer of Cu overburden (15–20 lm) is plated on

the wafer surface. The CMP with a commercial slurry

(Model: STSV2000) from Anji is developed for removal of

the copper. The top image of the vias after CMP is shown

in Fig. 7. Subsequently, the wafer backside is thinned

down to expose the backside of the TSV and the fine

grinding is then used for planarization. After the CMP

process, the Cu of both sides of the TSVs columns is easily

oxidized to form Cu oxidation. Followed by BCB/metal

multilayer interconnection preparation, the Cu oxidation is

etched by 0.5 lm thick to expose Cu by the ion-beam

process. And two new seed layers of TiW–Au are depos-

ited on both surfaces of the wafer and then the Au layers

are electroplated to 3 lm thick in case of the Cu oxidation

in the lateral process.

3.3 The BCB of process on the two sides of wafer

In this work, the photosensitive BCB process on the two

sides of wafer is used. The process flow of BCB includes

BCB spin-coating, pre-baking, lithography, pre-develop-

ment baking, development, post-development baking,

curing (Tang et al. 2011). On the first side of wafer, the

BCB layer is spun at 1100 rpm for 30 s and a thickness of

about 25 lm BCB was achieved. And then the pre-baking

process is performed on an enclosed hotplate for 90 s at

110 �C with flowing nitrogen. And the wafer is exposed to

deep UV light with the exposure dose ranges from 1,800 to

2,000 mJ/cm2. After UV exposure, the wafer is immersed

in 40 �C BCB developer (DS3000) following the pre-

develop baking. The last step was a hard cure for 60 min in

a nitrogen atmosphere.

To adapt to the two sides interconnection of wafer, some

adjustments of process should be made on the other side of

the wafer. Both the baking and the cure which use a heating

plate in conventional BCB process are replaced by oven

baking in the atmosphere of nitrogen to prevent the structure

on the backside from being destroyed. The temperature and

the time of the pre-baking step are 120 �C and 12 min,

respectively. And those of pre-development baking and post-

Fig. 5 Model of the absorption of electrolyte additives

Fig. 6 Cross-section image of vias with different current density and

plating time

Fig. 7 The top image of the core TSV and six shielding TSVs after

CMP


123

development baking are set to be 120 �C and 5 min, sepa-

rately. Since the BCB layers fabricated on the first side of the

wafer will be cured again, the cure temperature on BCB of

the first side could be reduced to 180 �C. And in the last BCB

cure step on the other side, the cure temperature will be rise

back to 210 �C in the standard BCB soft cure process. In

addition, the silicon is very fragile on the BCB process and

can thus not be handled with standard semiconductor

equipment for subsequent process. In order to overcome this

issue, the TSV wafer is mounted temporary on support wafer

for dry etching, lithography and electroplating. In the tem-

porary bonding process, the photoresist (Model: Shipley

6112), as the bonding material, is spun on a support wafer.

Then the TSV wafer is bonded to the support wafer on a

heating plate at 120 �C for 2 min. The method for debonding

is that the bonded wafers are immersed in the organic solu-

tion of stripping photoresist (acetone). The debonding tem-

perature is the room temperature.

In the process of BCB spin-coating, BCB accumulate or

hole occurs on the edge of TSV as shown in Fig. 8. The

nonuniform coating of BCB may arise from the difference

in height between the top of the TSVs and the substrate

silicon in the process of spin-coating. To avoid the non-

uniform, the BCB is spined on the wafer until BCB dripped

down covers the TSVs, and the standing time of wafer

coated by BCB is extended to 1 h. In addition, the BCB

accumulation also occurs in interval space between MMIC

chip and trench etched (Fig. 9a). The height of MMIC

embedded in trench and the depth of the trench need to be

accurately measured. If the height difference of MMIC in

the trench above the substrate silicon is less than 5 lm, the

BCB accumulation could be avoided (Fig. 9b).

4 Simulation and measurement results

The coaxial line structure through silicon substrate cannot

be achieved in the fabrication process. In this work, a

specially-designed TSV structure through the silicon,

which is composed of a core TSV and six shielding TSVs,

is used (Fig. 7). The core TSV transmits signal, and the

shielding TSVs are around the core and connected to the

ground. In the simulation of the microwave transmission

performance, the same MSL using one single TSV with no

shielding TSV and using coaxial line to achieve the inter-

side connection are also simulated and compared to the

results of the proposed structure. As shown as Fig. 10, the

performance of the proposed structure is very close to

the coaxial line case. Both the return loss is better than

30 dB from 18 to 30 GHz. The insertion loss of propose

structure is 0.55 dB at 24 GHz which is 0.04 dB larger than

the coaxial line case. However, the S21 of the case with no

shielding TSV is nearly 1 dB at 24 GHz. The microwave

transmission performance of the proposed structure is as

good as the case of the coaxial line and easier to be

fabricated.

The specimen of the proposed BCB/metal interconnec-

tion accompanied by TSVs for two sides connection is

fabricated and the Fig. 11 shows the photograph of the

front and back sides of the test vehicle whose cross-sec-

tional structure is shown in Fig. 1b. The test structure

includes the MSL in MMIC, TSV, L1 (the MSL on the

packaging substrate) and L2 (the MSL on backside of the

packaging substrate). The parameters of the structure are

listed in the Table 2. The electrical resistances and the

microwave transmission performance of the test vehicle

will be measured.

The resistances of the test vehicle structure are tested by

a Cascade-M150 probe-station. The theoretical resistance

is 0.52 X. The measured electrical resistance value is

within 0.719 X by Kelvin measurement. The measured

resistance is close to the theoretical resistance.

Fig. 8 BCB holes image on the edge of TSV

Fig. 9 BCB accumulate images on interval space between MMIC

chip and trench. a BCB accumulate, b BCB uniform after process

improved


123

After the RF data are de-embedded, the microwave

transmission performance of the structure is measured by

Agilent 8722D network analyzer from 14 to 40 GHz. And

the measurement results are shown in Fig. 12. The mea-

surement results reveal a return loss better than 23.8 dB

and an insertion loss better than 2.60 dB. And the mini-

mum value of S21 is 1.42 dB. Especially in the range from

14 to 26.8 GHz, the return loss is better than 15 dB. And

the simulation curve of the S11 and S21 are shown as

Fig. 13. A difference of 1.5–2.5 dB of S21 between the

measurement and the simulation of the test vehicle is

observed in the measurement frequency range.

The relatively large loss may result from several rea-

sons. The BCB coating on the substrate is nonuniform and

its thickness is hard to be precisely controlled to be con-

sistent with the designed value (25 lm thick). And the

BCB thickness around the interior via is a bit thinner than

Fig. 10 The performance of the proposed specimen, the coaxial line

case and the no shielding via case. a The insertion loss; b The return

loss

Fig. 11 Photographs of the front and back sides of the test vehicle

Table 2 Parameters of the interconnection structure

Variable Value (lm)

Length of MSL 900

TSV diameter 40

Substrate thickness 280

Length of L1 350

Length of L2 50

Fig. 12 The measurement result of the microwave transmission

performance


123

25 lm thick in the other part of the surface, as shown in

Fig. 14. Moreover, the deviation in width of the transmis-

sion line is induced by the lithography inaccuracy. All

these will lead to the impedance mismatch of the trans-

mission line. Moreover, the relatively large loss may result

from the contact resistances, interlayer connections and the

negative effect caused by the BCB-covered auxiliary sili-

con wafer which is attached below the test wafer for

backside insulation in the measurement. This 3D inter-

connection method in the microwave subsystem integration

with MMIC chips will be improved in our future work.

5 Conclusions

A wafer-level system-in-packaging structure using through

silicon via (TSV) for integration on both sides of the Si

wafer is proposed and realized. BCB/metal multilayer

interconnection is used to achieve 3D integration on the

substrate, and a specially designed TSV structure is adop-

ted to connect the components on different sides of the

wafer through the substrate. The TSV fabrication process

and the multi-interconnection is illustrated in details. The

measurement of the interconnection structure are presented

to investigate the electrical resistances and high-frequency

performance. The measurement result reveals the resis-

tances is within 0.719 X and a return loss better than

23.8 dB and an insertion loss better than 2.60 dB from 14

to 40 GHz. This 3D interconnection method will be applied

in the microwave multichip module in our future work.

Acknowledgments This work is supported by National Major Fun-

damental Research Program of China (Grant No. 2009CB320207) and

National Science and Technology Major Project—Research, Devel-

opment and Industry of RDL/Embedding Wafer-Level Packaging and

High-Density Bumping Technology (No. 2011ZX02602). The authors

would also like to thank the support of Jiangsu Changjiang Electronics

Technology Co., Ltd, Shanghai Anji Microelectronics Co., Ltd. and

Shanghai Sinyang Semiconductor Materials Co., Ltd.

References

Beica R, Siblerud P, Sharbono C, Bernt M (2008) Advanced

metallization for 3D integration. In: Proceeding of 10th

electronics packaging technology conference (ECTC 2008)

212–218

Ding XY, Geng F, Luo L (2009) Process development in metal/BCB

multilayer interconnections of MMCM with embedded chip in Si

substrate. Microelectron Eng 86:335–339. doi:10.1016/j.mee.

2008.11.005

Fang C, Corre AL, Yon D (2011) Copper electroplating into deep

microvias for the SiP application. Microelectron Eng 88:

749–753. doi:10.1016/j.mee.2010.07.034

Ho SW, Yoon SW, Zhou Q, Pasad K, Kripesh V, Lau J (2008) High

RF performance TSV silicon carrier for high frequency appli-

cation. In: Proceeding of 58th electronic components and

technology conference (ECTC 2008), pp 1946–1952

Jang DM, Ryu C, Lee KY, Cho BH, Kim J, Oh TS, Lee WJ, Yu J

(2007) Development and evaluation of 3-D SiP with vertically

interconnected through silicon vias (TSV). In: Proceeding of

57th electronic components and technology conference (ECTC

2007), pp 847–852

Kannan S, Evana SS, Gupta A, Kim B, Li L (2011) 3-D copper based

TSV for 60-GHz applications. In: Proceeding of 61st electronic

components and technology conference (ECTC 2011),

pp 1168–1175

Kumagai K, Yoneda Y, Izumino H, Shimojo H, Sunohara M,

Kurihara T, Higashi M, Mabuchi Y (2008) A silicon interposer

BGA package with Cu-filled TSV and multi-layer Cu-plating

interconnect. In: Proceeding of 58th electronic components and

technology conference (ECTC 2008), pp 571–576

Lim TG, Khoo YM, Selvanayagam CS, Ho SW, Li R, Zhang XW,

Shan G, Zhong XY (2011) Through silicon via interposer for

millimetre wave applications. In: Proceeding of 61th electronic

components and technology conference (ECTC 2011),

pp 577–582

Seok S, Rolland N, Rolland P-A (2006) Packaging methodology for

RF devices using a BCB membrane transfer technique. J Micro-

mech Microeng 16:2384–2388. doi:10.1088/0960-131

7/16/11/019

Tang JJ, Sun XW, Luo L (2011) A wafer-level multi-chip module

process with thick photosensitive benzocyclobutene as the

Fig. 13 The simulation curve of the microwave transmission

performance

Fig. 14 BCB thickness around the developed via is thinner than the

designed value 25 lm


123

http://dx.doi.org/10.1016/j.mee.2008.11.005



http://dx.doi.org/10.1088/0960-1317/16/11/019

http://dx.doi.org/10.1088/0960-1317/16/11/019

dielectric for microwave application. J Micromech Microeng 21

065035. doi:10.1088/0960-1317/21/6/065035

Tsui KYK, Yau SK, Leung VCK, Sun P, Shi DXQ (2009) Parametric

study of electroplating-based via-filling process for tsv applica-

tions. In: 2009 International Conference on electronic packaging

technology and high density packaging (ICEPT-HDP), pp 23–27

Tummala RR, Swaminathan M (2008) Introduction to system-on-

package (SoP): miniaturization of the entire system. McGraw-

Hill, USA, pp 81–144


123

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