Production and Testing of tProduction and Testing of the DØ he DØ Silicon Microstrip TrackerSilicon Microstrip Tracker

Frank FilthautUniversity of Nijmegen / NIKHEF

For the DØ Collaboration

NSS-MIC, 15-20 October 2000

DD

The DØ Run II upgrade

The Silicon Microstrip Tracker design

Detector production

Testing

Expected performance

Conclusions

2

DD

Addition of central axial 2T magnetic field (SC solenoid in front of calorimeter cryostat)

Extend muon chamber coverage, smaller granularity (better lepton ID)

Upgraded calorimeter, trigger, DAQ electronics

DØ Run II UpgradeDØ Run II Upgrade

Bunch spacing: from 3.5 s to 132 ns (start @396 ns) Aim: collect 2-3 fb-1 in several years #MB interactions/crossing: 2-5 (@ 2-5 ·1032 cm-2 s-1) Interaction region: z = 25 cm

3

DDDØ Run II UpgradeDØ Run II Upgrade - Tracking - Tracking

ForwardPreshower

Fiber Tracker

Solenoid Central Preshower

Silicon Microstrip Tracker

B-tagging based on b lifetime (scintillating fibre tracker complemented by silicon strip detector)

Improved muon and electron (preshower detectors) identification and triggering

Charge sign determination

High-pT central physics in dense environment redundancy B physics, QCD studies good forward coverage

Physics requirements impacting tracker design:

All these detectors use the SVX2 digital front-end chip

4

DD

1 2 3 4 5 6

1 2 3 4

5 67 8

9101112

SMT DesignSMT Design

Basic SMT Design:

Barrels F-Disks H-Disks

Layers/planes 4 12 4ReadoutLength

12.4 cm 7.5 cm 14.6 cm

Inner Radius 2.7 cm 2.6 cm 9.5 cmOuter Radius 9.4 cm 10.5 cm 26 cm

6 barrels 12 F disks 4 H disks

Axial strips to be used in L2 Silicon Track Trigger (STT):

stringent requirements on barrel alignment

six-fold azimuthal symmetry

Should be radiation-hard to several Mrad (from pp interactions)

Totals: 793k channels, 768 modules

3.0 m2 (of which 1.6 m2 DS)

1.5 M wire bonds

5

DDSMT DesignSMT Design

Layers 1 (3): 12 (24) DS, DM 90º ladders produced from 6” wafers (6 chips) (barrels 1 & 6: SS axial ladders from 4” wafers: 3 chips)

Layers 2 (4): 12 (24) DS 2º ladders produced from 4” wafers (9 chips)

SMT barrel cross-section:

Ladder count: 72 SS + 144 DS (90º) + 216 DS (2º)

SMT disks:

F disks: 12 DS ±15º wedges (8+6 chips)

H disks: 96 SS 7.5º half-wedges made into full wedges and glued back to back (2x6 chips)

Wedge count: 144 F + 96 H

6

DDAnatomy of a LadderAnatomy of a Ladder

Ladders supported by “active” (cooled) and “passive” beryllium bulkheads

Ladders fixed by engaging precision notches in beryllium substrates on posts on bulkheads

Beryllium cools electronics expect chips to operate at 25 ºC using

70% H2O/30% ethyl glycol mixture at –10 ºC hottest Si point should be at 5-10 ºC (DS), 0 ºC

(SS) High Density Interconnect (HDI) tail routed out radially

between outer layers Carbon-fibre/Rohacell rails glued to sensors for

structural stiffness

7

DDHigh Density InterconnectHigh Density Interconnect

Two-layer flex-circuit mounted directly on silicon, housing SVX chips as well as passive electronics

Kapton based, trace pitch 200 m Connects to “low-mass” cable using Hirose connector 9 different types for the 5 sensor types

2 for each sensor type except H disks 2 types for each ladder differ only in tail length

Laminated to beryllium substrate (total mass 0.041 X0, of which 0.014 X0 from Si)

Need 912 HDI’s

9-chip HDI H-wedge HDI

8

DDLadder Production in steps (9-chip)Ladder Production in steps (9-chip)

1. Apply pattern of non-conductive epoxy on p-side beryllium

2. Align beryllium with respect to active sensor, apply pressure and cure for 24 hr

3. Align active & passive sensors w.r.t. each other, apply wire bonds.

Then use separate fixture to position carbon-fibre rails. Use conductive epoxy to ground “passive” beryllium. Cure for 24 hr

0. HDI laminated to beryllium substrates, all chips & passive components mounted and tested

9

DDLadder Production in steps (9-chip)Ladder Production in steps (9-chip)

4. Use “flip fixture” to have n-side on top

5. Apply epoxy to n-side beryllium, fold over and secure HDI. Apply pressure and cure for 24 hr.

Then apply n-side Si-Si and Si-SVX wirebonds

6. Encapsulate bonds at HDI edges.

Connect “active” beryllium to cable ground

10

DDTesting & RepairsTesting & Repairs

Bonds need to be plucked

- 50

0

50

100

150

200

250

0 128 256 384 512 640 768 896 1024 1152

mean

noise x10

diff . noise x- 1

Bad ground connection

Broken capacitors: cause SVX front-end to saturate, tends to affect neighbouring channels as well pluck corresponding bonds

Bad grounding of beryllium substrates causes large pedestal structures (bad for common threshold) as well as high noise ensure RBe-gnd < 10 (in fact now better than 1)

Repair broken / wrong bonds Replace chips / repair tails damaged during processing

DAQ run stand-alone from spreadsheet program (+ help from probe station, logic analyzer) to check pedestals, (selective) test charge inject, sparsification

11

DDBurn-in & Laser TestsBurn-in & Laser Tests

0

64

128

192

256

0 128 256 384

pulse height

Dead Channel

Laser

Laser Test:

Energy just < Si bandgap (atten. length 400 m test full sensor thickness)

Find dead & noisy channels Determine initial operating

voltages (from pulse height plateau, Ileak-V curve)

Burn-in Test:

Long-term (72 hr, 30’ between runs) test of whole ladder/wedge (conditions close to those in experiment)

x-y movable laser head

12

DDSensorsSensors

Double-sided, double-metal sensors:

Sensor delivery from Micron has been slow (30% yield) mainly due to p-stop defects on mask (noise affecting 10-15 strips)

Schedule problem

Single-sided sensors:

Sensor flatness marginal for trigger purposes (understood to be due to processing: generic)

Module assembly modified to minimise problem

13

DDMicro-dischargesMicro-discharges

Potential difference across coupling capacitor oxide layer high fringe field at edge in silicon bulk (see KEK 93-129)

Above certain voltage, micro-discharges (avalanche breakdown) cause burst noise inhibiting operation

Correlates with sudden increase of leakage current Sensitive to implant-metal alignment Worst at junction side (n+ side after type inversion) Potentially limiting factor for lifetime of detector

Worry for DS sensors using integrated coupling capacitors:

0

1

10

100

1000

10000

-70 -60 -50 -40 -30 -20 -10 0

-HV bias (V)

I_s

trip

(nA

)

1625-7-2 strip450,ACpad on GND

1625-7-2 strip450,ACpad floating

1625-7-2 strip400,ACpad GND

1625-7-2 strip400,ACpad floating

1615-9-4 strip219,ACpad float

1615-9-4 strip219,ACpad GND

Example for un-irradiated detector (bias on p+-side):

p+ metal at ground

p+ metal floating

14

DDMicro-dischargesMicro-discharges

Irradiated with neutrons, fluence 1014 cm-2 (corresponding to several fb-1 for innermost DØ silicon layer, type inverted)

Kept at room temperature for 4 months for accelerated reverse annealing

Test on irradiated DSDM detector:

6399 noise on p-side

0

0.5

1

1.5

2

2.5

3

3.5

0 50 100 150

Total HV

AD

C C

ou

nts

-10V

-30V

-50V

-70V

-90V

6399 noise on n-side

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

0 20 40 60 80 100 120 140 160

Total HV

AD

C C

ou

nts

-10V

-30V

-50V

-70V

-90V

p-side noise

n-side noise

After type inversion, problem worst at n+ side

Different curves Different curves correspond to different correspond to different pp++ bias (-HV) for same bias (-HV) for same total biastotal bias

Applying bias to both p+ and n+ sides, total bias limited to 120-130 V (aim to keep noise below 3 counts)

Assuming a 20-30 V overbias to retain high charge collection efficiency on p+ side, this limits the maximum depletion voltage to 100 V good for 4 fb-1

Noise for un-irradiated Noise for un-irradiated detectors detectors 2 ADC 2 ADC countscounts

15

DDProduction status and overall qualityProduction status and overall quality

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Detector classification:

Dead channel: laser response < 40 ADC counts Noisy channel: (burn-in) pedestal width > 6 ADC counts

(normally < 2 counts excluding coherent noise) Grade A: less than 2.6% dead/noisy channels Grade B: less than 5.2% dead/noisy channels

Use only detector grades A,B; mechanically OK

Example for 9-chip detectors (better for other detector types):

Dead Noisy

All sensors delivered All HDIs delivered Ladder and wedge production, testing essentially

complete (driven by HDI/sensor delivery)

Production status:

16

DDBarrel Assembly in stepsBarrel Assembly in steps

1. Insert individual ladders into rotating fixture using 3D movable table

2. Manually push notches against posts (all under CMM)

Rule of thumb: Align to 20 m (trigger) Survey to 5 m (offline)

Precisely machined bulkheads Barrel assembly done inside out (protect wire bonds)

17

DDBarrel AssemblyBarrel Assembly

Layer 4 glued to bulkheads (providing structural stiffness, holding passive BH)

Thermally conductive grease applied (active BH only) for other layers

First 4 barrels assembled ( 4 weeks/barrel, excluding survey)

3. Secure ladder using tapered pins

18

DDF-Disk AssemblyF-Disk Assembly

F-disk assembly less critical (not included in trigger), nevertheless performed under CMM (5-10 m accuracy)

Quick process After assembly, “central” F-disk cooling rings screwed onto

active barrel bulkheads

z=0

Vdepl H H H HHHL ML L LM

All disks are not created equally!

Distribution of different quality devices over disks:

H/M = Micron high/medium Vdepl, L = Eurisys low Vdepl

Prefer high Vdepl now to reach micro-discharge limit later

19

DDHalf-cylinder assemblyHalf-cylinder assembly

“Mating” of central F disks to barrels:

Disk lowered on support arm, cooling ring screwed onto barrel BH Accuracy ~ 75 m in transverse plane

Individual barrel-disk assemblies lowered into CF support trough

Central part of first half-cylinder

20

DDHalf-cylinder assemblyHalf-cylinder assembly

Installation of end disks:

End disks assembled and lowered into support trough

First half-cylinder complete on 28/9

Afterwards: put on top cover, cut HDI tails to length, connect to “low-mass” cables, verify cooling circuit, test… almost done

21

DDReadout ElectronicsReadout Electronics

For 5% occupancy, 1 kHz trigger rate: 1010 bits/s need error rate 10-15

Exercise readout system as much as possible before installation in experiment 10% system test using full readout chain (readout full F disk, barrel, barrel-disk assembly, H disk)

Complete readout chain (including L3 analysis, data storage) tested on several detectors

Monitoring Control

platformplatform

SEQ

SEQ

SEQ

SEQ

SEQ

SEQ

VRB Controller

Optical Link1Gb/s

VBD

V R B68k

Secondary Datapath

VME

3M

1553

NRZ/ CLK

IB

L3 HOST

ExamineExamine

HDI

Low Mass

22

DDConclusions & lessonsConclusions & lessons

Huge effort: large amount of silicon stringent constraints (alignment, material budget) many different parts (5 sensor types, 9 HDI types), …

Now nearing (successful) completion, confident that the whole detector will be in place by 1/3/2001 startup date (even if not all electronics might be)

Think this detector should last at least ~ 4 fb-1

Good:

But:

We know it will not last for all of the Tevatron Run II (current projections by beams division ~ 15 fb-1, rather than original estimate of 2 fb-1)

We’re thinking of our next detector! If we have the luxury to learn from our experience this time:

Abandon DS silicon sensors (radiation hardness) Lower number of sensor/hybrid types Attempt to automate production as much as possible

We have an exciting time ahead of us!